+ panic("move not supported for this mode");
+ }
+}
+
+static void emit_be_Perm(const ir_node *node)
+{
+ const arch_register_t *in0, *in1;
+ const arch_register_class_t *cls0, *cls1;
+
+ in0 = arch_get_irn_register(get_irn_n(node, 0));
+ in1 = arch_get_irn_register(get_irn_n(node, 1));
+
+ cls0 = arch_register_get_class(in0);
+ cls1 = arch_register_get_class(in1);
+
+ assert(cls0 == cls1 && "Register class mismatch at Perm");
+
+ amd64_emitf(node, "xchg %R, %R", in0, in1);
+
+ if (cls0 != &amd64_reg_classes[CLASS_amd64_gp]) {
+ panic("unexpected register class in be_Perm (%+F)", node);