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add support for thread scheduling (POSIX TPS option)
[musl]
/
arch
/
x86_64
/
atomic.h
diff --git
a/arch/x86_64/atomic.h
b/arch/x86_64/atomic.h
index
7a665c1
..
0d3da6f
100644
(file)
--- a/
arch/x86_64/atomic.h
+++ b/
arch/x86_64/atomic.h
@@
-1,5
+1,5
@@
-#ifndef _INTERNA
A
_ATOMIC_H
-#define _INTERNA
A
_ATOMIC_H
+#ifndef _INTERNA
L
_ATOMIC_H
+#define _INTERNA
L
_ATOMIC_H
#include <stdint.h>
#include <stdint.h>
@@
-10,6
+10,12
@@
static inline int a_ctz_64(uint64_t x)
return r;
}
return r;
}
+static inline int a_ctz_l(unsigned long x)
+{
+ long r;
+ __asm__( "bsf %1,%0" : "=r"(r) : "r"(x) );
+ return r;
+}
static inline void a_and_64(volatile uint64_t *p, uint64_t v)
{
static inline void a_and_64(volatile uint64_t *p, uint64_t v)
{
@@
-48,6
+54,13
@@
static inline long a_cas_l(volatile void *p, long t, long s)
return t;
}
return t;
}
+static inline int a_cas(volatile int *p, int t, int s)
+{
+ __asm__( "lock ; cmpxchgl %3, %1"
+ : "=a"(t), "=m"(*p) : "a"(t), "r"(s) : "memory" );
+ return t;
+}
+
static inline void *a_swap_p(void *volatile *x, void *v)
{
__asm__( "xchg %0, %1" : "=r"(v), "=m"(*(void **)x) : "0"(v) : "memory" );
static inline void *a_swap_p(void *volatile *x, void *v)
{
__asm__( "xchg %0, %1" : "=r"(v), "=m"(*(void **)x) : "0"(v) : "memory" );
@@
-105,5
+118,10
@@
static inline void a_spin()
__asm__ __volatile__( "pause" : : : "memory" );
}
__asm__ __volatile__( "pause" : : : "memory" );
}
+static inline void a_crash()
+{
+ __asm__ __volatile__( "hlt" : : : "memory" );
+}
+
#endif
#endif