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$(FirmRoot)\ir\be\sparc $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\sparc $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs) $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c.inl;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;%(Outputs) Translate Spec: %(FullPath) $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\sparc $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\sparc $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\sparc 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%(FullPath) $(FirmRoot)\ir\be\sparc $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs) $(FirmRoot)\ir\be\sparc\gen_sparc_emitter.c;$(FirmRoot)\ir\be\sparc\gen_sparc_emitter.h;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.c.inl;$(FirmRoot)\ir\be\sparc\gen_sparc_new_nodes.h;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.c;$(FirmRoot)\ir\be\sparc\gen_sparc_regalloc_if.h;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.c;$(FirmRoot)\ir\be\sparc\gen_sparc_machine.h;%(Outputs) Translate Spec: %(FullPath) $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs) $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs) Translate Spec: %(FullPath) $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs) $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs) Translate Spec: %(FullPath) $(FirmRoot)\ir\be\scripts\generate_emitter.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_machine.pl %(FullPath) $(FirmRoot)\ir\be\amd64 $(FirmRoot)\ir\be\scripts\generate_emitter.pl;$(FirmRoot)\ir\be\scripts\generate_new_opcodes.pl;$(FirmRoot)\ir\be\scripts\generate_regalloc_if.pl;$(FirmRoot)\ir\be\scripts\generate_machine.pl;%(AdditionalInputs) $(FirmRoot)\ir\be\amd64\gen_amd64_emitter.c;$(FirmRoot)\ir\be\amd64\gen_amd64_emitter.h;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.c.inl;$(FirmRoot)\ir\be\amd64\gen_amd64_new_nodes.h;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.c;$(FirmRoot)\ir\be\amd64\gen_amd64_regalloc_if.h;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.c;$(FirmRoot)\ir\be\amd64\gen_amd64_machine.h;%(Outputs) Generating I/O code: %(FullPath) python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir ..\scrip..\..\ir_spec.py;%(AdditionalInputs) ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs) Generating I/O code: %(FullPath) python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir ..\scrip..\..\ir_spec.py;%(AdditionalInputs) ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs) Generating I/O code: %(FullPath) python %(FullPath) ..\scrip..\..\ir_spec.py ..\..\ir\ir ..\scrip..\..\ir_spec.py;%(AdditionalInputs) ..\..\ir\ir\gen_irio_import.inl;..\..\ir\ir\gen_irio_export.inl;..\..\ir\ir\gen_irio_lex.inl;%(Outputs) Translate IR-Spec: %(FullPath) python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir ..\..\scripts\gen_ir.py;%(AdditionalInputs) ..\..\ir\ir\gen_ir_cons.c.inl;%(Outputs) Translate IR-Spec: %(FullPath) python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir ..\..\scripts\gen_ir.py;%(AdditionalInputs) $(FirmRoot)\ir\ir\gen_ir_cons.c.inl;$(FirmRoot)\ir\ir\gen_irnode.h;$(FirmRoot)\ir\ir\gen_irnode.c.inl;$(FirmRoot)\ir\ir\gen_irop.c.inl;%(Outputs) Translate IR-Spec: %(FullPath) python ..\..\scripts\gen_ir.py %(FullPath) ..\..\ir\ir ..\..\scripts\gen_ir.py;%(AdditionalInputs) ..\..\ir\ir\gen_ir_cons.c.inl;%(Outputs)