nsz Git - libfirm/blob - testprograms/ref-results/IRR_LOOP_main-cfg.vcg

   1 graph: { title: "ir graph of IRR_LOOP_main"
   2 display_edge_labels: yes
   3 layoutalgorithm: mindepth
   4 manhattan_edges: yes
   5 port_sharing: no
   6 orientation: bottom_to_top
   7 classname 1:  "intrablock Data"
   8 classname 16: "interblock Data"
   9 classname 2:  "Block"
  10 classname 13: "Control Flow"
  11 classname 14: "intrablock Memory"
  12 classname 17: "interblock Memory"
  13 classname 15: "Dominators"
  14 classname 3:  "Entity type"
  15 classname 4:  "Entity owner"
  16 classname 5:  "Method Param"
  17 classname 6:  "Method Res"
  18 classname 7:  "Super"
  19 classname 8:  "Union"
  20 classname 9:  "Points-to"
  21 classname 10: "Array Element Type"
  22 classname 11: "Overwrites"
  23 classname 12: "Member"
  24 infoname 1: "Attribute"
  25 infoname 2: "Verification errors"
  26
  27 node: {title: "n60" label: "Block n60" }
  28 edge: { sourcename: "n60" targetname: "n62"}
  29 node: {title: "n62" label: "Block n62" }
  30 edge: { sourcename: "n62" targetname: "n66"}
  31 edge: { sourcename: "n62" targetname: "n64"}
  32 node: {title: "n64" label: "Block n64" }
  33 edge: { sourcename: "n64" targetname: "n77"}
  34 edge: { sourcename: "n64" targetname: "n66"}
  35 node: {title: "n66" label: "Block n66" }
  36 edge: { sourcename: "n66" targetname: "n77"}
  37 edge: { sourcename: "n66" targetname: "n64"}
  38 node: {title: "n77" label: "Block n77" }
  39 edge: { sourcename: "n77" targetname: "n72"}
  40 node: {title: "n72" label: "Block n72" }
  41 edge: { sourcename: "n72" targetname: "n72"}
  42 node: {title: "n94" label: "Bad  94"  info1: "visited: 0
  43 irg:     IRR_LOOP_main
  44 arity: 0
  45 "}
  46 }