2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Lower some High-level constructs, moved from the firmlower.
23 * @author Boris Boesler, Goetz Lindenmaier, Michael Beck
42 * Lower a Sel node. Do not touch Sels accessing entities on the frame type.
44 static void lower_sel(ir_node *sel) {
45 ir_graph *irg = current_ir_graph;
47 ir_node *newn, *cnst, *index, *ptr, *bl;
49 ir_mode *basemode, *mode, *mode_Int;
50 ir_type *basetyp, *owner;
55 ent = get_Sel_entity(sel);
56 owner = get_entity_owner(ent);
58 /* Do not lower frame type access: must be lowered by the backend. */
59 if (is_frame_type(owner))
63 * Cannot handle value param entities here.
64 * Must be lowered by the backend.
66 if (is_value_param_type(owner))
69 ptr = get_Sel_ptr(sel);
70 dbg = get_irn_dbg_info(sel);
71 mode = get_irn_mode(sel);
73 mode_Int = get_reference_mode_signed_eq(mode);
75 /* TLS access, must be handled by the linker */
76 if (get_tls_type() == owner) {
80 bl = get_nodes_block(sel);
82 cnst = new_rd_SymConst(dbg, irg, bl, sym, symconst_addr_ent);
83 newn = new_rd_Add(dbg, irg, bl, ptr, cnst, mode);
87 assert(get_type_state(get_entity_owner(ent)) == layout_fixed);
88 assert(get_type_state(get_entity_type(ent)) == layout_fixed);
90 bl = get_nodes_block(sel);
91 if (0 < get_Sel_n_indexs(sel)) {
93 basetyp = get_entity_type(ent);
94 if (is_Primitive_type(basetyp))
95 basemode = get_type_mode(basetyp);
97 basemode = mode_P_data;
99 assert(basemode && "no mode for lowering Sel");
100 assert((get_mode_size_bytes(basemode) != -1) && "can not deal with unorthodox modes");
101 index = get_Sel_index(sel, 0);
103 if (is_Array_type(owner)) {
105 ir_type *arr_ty = owner;
106 int dims = get_array_n_dimensions(arr_ty);
107 int *map = alloca(sizeof(int) * dims);
110 assert(dims == get_Sel_n_indexs(sel)
111 && "array dimension must match number of indices of Sel node");
113 for (i = 0; i < dims; i++) {
114 int order = get_array_order(arr_ty, i);
116 assert(order < dims &&
117 "order of a dimension must be smaller than the arrays dim");
120 newn = get_Sel_ptr(sel);
122 /* Size of the array element */
123 tv = new_tarval_from_long(get_type_size_bytes(basetyp), mode_Int);
124 last_size = new_rd_Const(dbg, irg, get_irg_start_block(irg), mode_Int, tv);
127 * We compute the offset part of dimension d_i recursively
128 * with the the offset part of dimension d_{i-1}
130 * off_0 = sizeof(array_element_type);
131 * off_i = (u_i - l_i) * off_{i-1} ; i >= 1
133 * whereas u_i is the upper bound of the current dimension
134 * and l_i the lower bound of the current dimension.
136 for (i = dims - 1; i >= 0; i--) {
138 ir_node *lb, *ub, *elms, *n, *ind;
141 lb = get_array_lower_bound(arr_ty, dim);
142 ub = get_array_upper_bound(arr_ty, dim);
144 assert(irg == current_ir_graph);
145 if (get_irn_op(lb) != op_Unknown)
146 lb = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), lb), mode_Int);
150 if (get_irn_op(ub) != op_Unknown)
151 ub = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), ub), mode_Int);
156 * If the array has more than one dimension, lower and upper
157 * bounds have to be set in the non-last dimension.
160 assert(lb && "lower bound has to be set in multi-dim array");
161 assert(lb && "upper bound has to be set in multi-dim array");
163 /* Elements in one Dimension */
164 elms = new_rd_Sub(dbg, irg, bl, ub, lb, mode_Int);
167 ind = new_rd_Conv(dbg, irg, bl, get_Sel_index(sel, dim), mode_Int);
170 * Normalize index, id lower bound is set, also assume
174 ind = new_rd_Sub(dbg, irg, bl, ind, lb, mode_Int);
176 n = new_rd_Mul(dbg, irg, bl, ind, last_size, mode_Int);
182 last_size = new_rd_Mul(dbg, irg, bl, last_size, elms, mode_Int);
184 newn = new_rd_Add(dbg, irg, bl, newn, n, mode);
188 ir_mode *idx_mode = get_irn_mode(index);
189 tarval *tv = new_tarval_from_long(get_mode_size_bytes(basemode), idx_mode);
191 newn = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel),
192 new_rd_Mul(dbg, irg, bl, index,
193 new_r_Const(irg, get_irg_start_block(irg), idx_mode, tv),
197 } else if (is_Method_type(get_entity_type(ent)) &&
198 is_Class_type(owner) &&
199 (owner != get_glob_type()) &&
200 (!is_frame_type(owner))) {
202 ir_mode *ent_mode = get_type_mode(get_entity_type(ent));
204 /* We need an additional load when accessing methods from a dispatch table. */
205 tv = new_tarval_from_long(get_entity_offset(ent), mode_Int);
206 cnst = new_rd_Const(dbg, irg, get_irg_start_block(irg), mode_Int, tv);
207 add = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel), cnst, mode);
208 #ifdef DO_CACHEOPT /* cacheopt version */
209 newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), sel, ent_mode);
210 cacheopt_map_addrs_register_node(newn);
211 set_Load_ptr(newn, add);
212 #else /* normal code */
213 newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), add, ent_mode);
215 newn = new_r_Proj(irg, bl, newn, ent_mode, pn_Load_res);
217 } else if (get_entity_owner(ent) != get_glob_type()) {
218 /* replace Sel by add(obj, const(ent.offset)) */
219 assert(!(get_entity_allocation(ent) == allocation_static &&
220 (get_entity_n_overwrites(ent) == 0 && get_entity_n_overwrittenby(ent) == 0)));
221 tv = new_tarval_from_long(get_entity_offset(ent), mode_Int);
222 cnst = new_r_Const(irg, get_irg_start_block(irg), mode_Int, tv);
223 newn = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel), cnst, mode);
226 newn = new_rd_SymConst_addr_ent(NULL, current_ir_graph, ent, firm_unknown_type);
236 * Lower a all possible SymConst nodes.
238 static void lower_symconst(ir_node *symc) {
246 switch (get_SymConst_kind(symc)) {
247 case symconst_type_tag:
248 assert(!"SymConst kind symconst_type_tag not implemented");
250 case symconst_type_size:
251 /* rewrite the SymConst node by a Const node */
252 tp = get_SymConst_type(symc);
253 assert(get_type_state(tp) == layout_fixed);
254 mode = get_irn_mode(symc);
255 tv = new_tarval_from_long(get_type_size_bytes(tp), mode);
256 newn = new_r_Const(current_ir_graph,
257 get_irg_start_block(current_ir_graph),
258 get_irn_mode(symc), tv);
262 exchange(symc, newn);
264 case symconst_type_align:
265 /* rewrite the SymConst node by a Const node */
266 tp = get_SymConst_type(symc);
267 assert(get_type_state(tp) == layout_fixed);
268 mode = get_irn_mode(symc);
269 tv = new_tarval_from_long(get_type_alignment_bytes(tp), mode);
270 newn = new_r_Const(current_ir_graph,
271 get_irg_start_block(current_ir_graph),
276 exchange(symc, newn);
278 case symconst_addr_name:
279 /* do not rewrite - pass info to back end */
281 case symconst_addr_ent:
284 case symconst_ofs_ent:
285 /* rewrite the SymConst node by a Const node */
286 ent = get_SymConst_entity(symc);
287 assert(get_type_state(get_entity_type(ent)) == layout_fixed);
288 mode = get_irn_mode(symc);
289 tv = new_tarval_from_long(get_entity_offset(ent), mode);
290 newn = new_r_Const(current_ir_graph,
291 get_irg_start_block(current_ir_graph),
296 exchange(symc, newn);
298 case symconst_enum_const:
299 /* rewrite the SymConst node by a Const node */
300 ec = get_SymConst_enum(symc);
301 assert(get_type_state(get_enumeration_owner(ec)) == layout_fixed);
302 tv = get_enumeration_value(ec);
303 newn = new_r_Const(current_ir_graph,
304 get_irg_start_block(current_ir_graph),
305 get_irn_mode(symc), tv);
309 exchange(symc, newn);
316 assert(!"unknown SymConst kind");
319 } /* lower_symconst */
322 * Checks, whether a size is an integral size
324 * @param size the size on bits
326 static int is_integral_size(int size) {
330 /* must be at least byte size */
332 } /* is_integral_size */
335 * lower bitfield load access.
337 * @param proj the Proj(result) node
338 * @param load the Load node
340 static void lower_bitfields_loads(ir_node *proj, ir_node *load) {
341 ir_node *sel = get_Load_ptr(load);
342 ir_node *block, *n_proj, *res, *ptr;
345 ir_mode *bf_mode, *mode;
346 int offset, bit_offset, bits, bf_bits, old_cse;
349 if (get_irn_op(sel) != op_Sel)
352 ent = get_Sel_entity(sel);
353 bf_type = get_entity_type(ent);
355 /* must be a bitfield type */
356 if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
359 /* We have a bitfield access, if either a bit offset is given, or
360 the size is not integral. */
361 bf_mode = get_type_mode(bf_type);
365 mode = get_irn_mode(proj);
366 block = get_nodes_block(proj);
367 bf_bits = get_mode_size_bits(bf_mode);
368 bit_offset = get_entity_offset_bits_remainder(ent);
370 if (bit_offset == 0 && is_integral_size(bf_bits) && bf_mode == get_Load_mode(load))
373 bits = get_mode_size_bits(mode);
374 offset = get_entity_offset(ent);
377 * ok, here we are: now convert the Proj_mode_bf(Load) into And(Shr(Proj_mode(Load)) for unsigned
378 * and Shr(Shl(Proj_mode(load)) for signed
381 /* abandon bitfield sel */
382 ptr = get_Sel_ptr(sel);
383 db = get_irn_dbg_info(sel);
384 ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
386 set_Load_ptr(load, ptr);
387 set_Load_mode(load, mode);
390 /* create new proj, switch off CSE or we may get the old one back */
391 old_cse = get_opt_cse();
393 res = n_proj = new_r_Proj(current_ir_graph, block, load, mode, pn_Load_res);
394 set_opt_cse(old_cse);
396 if (mode_is_signed(mode)) { /* signed */
397 int shift_count_up = bits - (bf_bits + bit_offset);
398 int shift_count_down = bits - bf_bits;
400 if (shift_count_up) {
401 res = new_r_Shl(current_ir_graph, block, res,
402 new_r_Const(current_ir_graph, block, mode_Iu, new_tarval_from_long(shift_count_up, mode_Iu)), mode);
404 if (shift_count_down) {
405 res = new_r_Shrs(current_ir_graph, block, res,
406 new_r_Const(current_ir_graph, block, mode_Iu, new_tarval_from_long(shift_count_down, mode_Iu)), mode);
408 } else { /* unsigned */
409 int shift_count_down = bit_offset;
410 unsigned mask = ((unsigned)-1) >> (bits - bf_bits);
412 if (shift_count_down) {
413 res = new_r_Shr(current_ir_graph, block, res,
414 new_r_Const(current_ir_graph, block, mode_Iu, new_tarval_from_long(shift_count_down, mode_Iu)), mode);
416 if (bits != bf_bits) {
417 res = new_r_And(current_ir_graph, block, res,
418 new_r_Const(current_ir_graph, block, mode, new_tarval_from_long(mask, mode)), mode);
423 } /* lower_bitfields_loads */
426 * lower bitfield store access.
428 * @todo: It adds a load which may produce an exception!
430 static void lower_bitfields_stores(ir_node *store) {
431 ir_node *sel = get_Store_ptr(store);
432 ir_node *ptr, *value;
435 ir_mode *bf_mode, *mode;
436 ir_node *mem, *irn, *block;
437 unsigned mask, neg_mask;
438 int bf_bits, bits_mask, offset, bit_offset;
441 /* check bitfield access */
442 if (get_irn_op(sel) != op_Sel)
445 ent = get_Sel_entity(sel);
446 bf_type = get_entity_type(ent);
448 /* must be a bitfield type */
449 if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
452 /* We have a bitfield access, if either a bit offset is given, or
453 the size is not integral. */
454 bf_mode = get_type_mode(bf_type);
458 value = get_Store_value(store);
459 mode = get_irn_mode(value);
460 block = get_nodes_block(store);
462 bf_bits = get_mode_size_bits(bf_mode);
463 bit_offset = get_entity_offset_bits_remainder(ent);
465 if (bit_offset == 0 && is_integral_size(bf_bits) && bf_mode == get_irn_mode(value))
469 * ok, here we are: now convert the Store(Sel(), value) into Or(And(Load(Sel),c), And(Value,c))
471 mem = get_Store_mem(store);
472 offset = get_entity_offset(ent);
474 bits_mask = get_mode_size_bits(mode) - bf_bits;
475 mask = ((unsigned)-1) >> bits_mask;
479 /* abandon bitfield sel */
480 ptr = get_Sel_ptr(sel);
481 db = get_irn_dbg_info(sel);
482 ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
485 /* there are some bits, normal case */
486 irn = new_r_Load(current_ir_graph, block, mem, ptr, mode);
487 mem = new_r_Proj(current_ir_graph, block, irn, mode_M, pn_Load_M);
488 irn = new_r_Proj(current_ir_graph, block, irn, mode, pn_Load_res);
490 irn = new_r_And(current_ir_graph, block, irn,
491 new_r_Const(current_ir_graph, block, mode, new_tarval_from_long(neg_mask, mode)), mode);
493 if (bit_offset > 0) {
494 value = new_r_Shl(current_ir_graph, block, value,
495 new_r_Const(current_ir_graph, block, mode_Iu, new_tarval_from_long(bit_offset, mode_Iu)), mode);
498 value = new_r_And(current_ir_graph, block, value,
499 new_r_Const(current_ir_graph, block, mode, new_tarval_from_long(mask, mode)), mode);
501 value = new_r_Or(current_ir_graph, block, value, irn, mode);
504 set_Store_mem(store, mem);
505 set_Store_value(store, value);
506 set_Store_ptr(store, ptr);
507 } /* lower_bitfields_stores */
510 * Lowers unaligned Loads.
512 static void lower_unaligned_Load(ir_node *load) {
518 * Lowers unaligned Stores
520 static void lower_unaligned_Store(ir_node *store) {
526 * lowers IR-nodes, called from walker
528 static void lower_irnode(ir_node *irn, void *env) {
530 switch (get_irn_opcode(irn)) {
538 if (env != NULL && get_Load_align(irn) == align_non_aligned)
539 lower_unaligned_Load(irn);
542 if (env != NULL && get_Store_align(irn) == align_non_aligned)
543 lower_unaligned_Store(irn);
546 exchange(irn, get_Cast_op(irn));
554 * Walker: lowers IR-nodes for bitfield access
556 static void lower_bf_access(ir_node *irn, void *env) {
558 switch (get_irn_opcode(irn)) {
561 long proj = get_Proj_proj(irn);
562 ir_node *pred = get_Proj_pred(irn);
563 ir_op *op = get_irn_op(pred);
565 if ((proj == pn_Load_res) && (op == op_Load))
566 lower_bitfields_loads(irn, pred);
570 lower_bitfields_stores(irn);
576 } /* lower_bf_access */
579 * Replaces SymConsts by a real constant if possible.
580 * Replace Sel nodes by address computation. Also resolves array access.
581 * Handle Bitfields by added And/Or calculations.
583 void lower_highlevel(void) {
586 n = get_irp_n_irgs();
587 for (i = 0; i < n; ++i) {
588 ir_graph *irg = get_irp_irg(i);
590 /* First step: lower bitfield access: must be run as long as Sels still exists. */
591 irg_walk_graph(irg, NULL, lower_bf_access, NULL);
593 /* Finally: lower SymConst-Size and Sel nodes, Casts, unaligned Load/Stores. */
594 irg_walk_graph(irg, NULL, lower_irnode, NULL);
596 set_irg_phase_low(irg);
598 } /* lower_highlevel */