2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Lower some High-level constructs, moved from the firmlower.
23 * @author Boris Boesler, Goetz Lindenmaier, Michael Beck
40 * Lower a Sel node. Do not touch Sels accessing entities on the frame type.
42 static void lower_sel(ir_node *sel) {
43 ir_graph *irg = current_ir_graph;
45 ir_node *newn, *cnst, *index, *ptr, *bl;
47 ir_mode *basemode, *mode, *mode_Int;
48 ir_type *basetyp, *owner;
53 /* Do not lower frame type/global offset table access: must be lowered by the backend. */
54 ptr = get_Sel_ptr(sel);
55 if (ptr == get_irg_frame(current_ir_graph))
58 ent = get_Sel_entity(sel);
59 owner = get_entity_owner(ent);
62 * Cannot handle value param entities here.
63 * Must be lowered by the backend.
65 if (is_value_param_type(owner))
68 dbg = get_irn_dbg_info(sel);
69 mode = get_irn_mode(sel);
71 mode_Int = get_reference_mode_signed_eq(mode);
73 /* TLS access, must be handled by the linker */
74 if (get_tls_type() == owner) {
78 bl = get_nodes_block(sel);
80 cnst = new_rd_SymConst(dbg, irg, bl, mode, sym, symconst_addr_ent);
81 newn = new_rd_Add(dbg, irg, bl, ptr, cnst, mode);
85 assert(get_type_state(get_entity_owner(ent)) == layout_fixed);
86 assert(get_type_state(get_entity_type(ent)) == layout_fixed);
88 bl = get_nodes_block(sel);
89 if (0 < get_Sel_n_indexs(sel)) {
91 basetyp = get_entity_type(ent);
92 if (is_Primitive_type(basetyp))
93 basemode = get_type_mode(basetyp);
95 basemode = mode_P_data;
97 assert(basemode && "no mode for lowering Sel");
98 assert((get_mode_size_bits(basemode) % 8 == 0) && "can not deal with unorthodox modes");
99 index = get_Sel_index(sel, 0);
101 if (is_Array_type(owner)) {
102 ir_type *arr_ty = owner;
103 int dims = get_array_n_dimensions(arr_ty);
104 int *map = ALLOCAN(int, dims);
108 assert(dims == get_Sel_n_indexs(sel)
109 && "array dimension must match number of indices of Sel node");
111 for (i = 0; i < dims; i++) {
112 int order = get_array_order(arr_ty, i);
114 assert(order < dims &&
115 "order of a dimension must be smaller than the arrays dim");
118 newn = get_Sel_ptr(sel);
120 /* Size of the array element */
121 tv = new_tarval_from_long(get_type_size_bytes(basetyp), mode_Int);
122 last_size = new_rd_Const(dbg, irg, mode_Int, tv);
125 * We compute the offset part of dimension d_i recursively
126 * with the the offset part of dimension d_{i-1}
128 * off_0 = sizeof(array_element_type);
129 * off_i = (u_i - l_i) * off_{i-1} ; i >= 1
131 * whereas u_i is the upper bound of the current dimension
132 * and l_i the lower bound of the current dimension.
134 for (i = dims - 1; i >= 0; i--) {
136 ir_node *lb, *ub, *elms, *n, *ind;
139 lb = get_array_lower_bound(arr_ty, dim);
140 ub = get_array_upper_bound(arr_ty, dim);
142 assert(irg == current_ir_graph);
143 if (! is_Unknown(lb))
144 lb = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), lb), mode_Int);
148 if (! is_Unknown(ub))
149 ub = new_rd_Conv(dbg, irg, bl, copy_const_value(get_irn_dbg_info(sel), ub), mode_Int);
154 * If the array has more than one dimension, lower and upper
155 * bounds have to be set in the non-last dimension.
158 assert(lb != NULL && "lower bound has to be set in multi-dim array");
159 assert(ub != NULL && "upper bound has to be set in multi-dim array");
161 /* Elements in one Dimension */
162 elms = new_rd_Sub(dbg, irg, bl, ub, lb, mode_Int);
165 ind = new_rd_Conv(dbg, irg, bl, get_Sel_index(sel, dim), mode_Int);
168 * Normalize index, id lower bound is set, also assume
172 ind = new_rd_Sub(dbg, irg, bl, ind, lb, mode_Int);
174 n = new_rd_Mul(dbg, irg, bl, ind, last_size, mode_Int);
180 last_size = new_rd_Mul(dbg, irg, bl, last_size, elms, mode_Int);
182 newn = new_rd_Add(dbg, irg, bl, newn, n, mode);
186 ir_mode *idx_mode = get_irn_mode(index);
187 tarval *tv = new_tarval_from_long(get_mode_size_bytes(basemode), idx_mode);
189 newn = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel),
190 new_rd_Mul(dbg, irg, bl, index,
191 new_r_Const(irg, idx_mode, tv),
195 } else if (is_Method_type(get_entity_type(ent)) &&
196 is_Class_type(owner) &&
197 (owner != get_glob_type()) &&
198 (!is_frame_type(owner))) {
200 ir_mode *ent_mode = get_type_mode(get_entity_type(ent));
202 /* We need an additional load when accessing methods from a dispatch table. */
203 tv = new_tarval_from_long(get_entity_offset(ent), mode_Int);
204 cnst = new_rd_Const(dbg, irg, mode_Int, tv);
205 add = new_rd_Add(dbg, irg, bl, get_Sel_ptr(sel), cnst, mode);
206 #ifdef DO_CACHEOPT /* cacheopt version */
207 newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), sel, ent_mode);
208 cacheopt_map_addrs_register_node(newn);
209 set_Load_ptr(newn, add);
210 #else /* normal code */
211 newn = new_rd_Load(dbg, irg, bl, get_Sel_mem(sel), add, ent_mode);
213 newn = new_r_Proj(irg, bl, newn, ent_mode, pn_Load_res);
215 } else if (get_entity_owner(ent) != get_glob_type()) {
218 /* replace Sel by add(obj, const(ent.offset)) */
219 assert(!(get_entity_allocation(ent) == allocation_static &&
220 (get_entity_n_overwrites(ent) == 0 && get_entity_n_overwrittenby(ent) == 0)));
221 newn = get_Sel_ptr(sel);
222 offset = get_entity_offset(ent);
224 ir_mode *mode_UInt = get_reference_mode_unsigned_eq(mode);
226 tv = new_tarval_from_long(offset, mode_UInt);
227 cnst = new_r_Const(irg, mode_UInt, tv);
228 newn = new_rd_Add(dbg, irg, bl, newn, cnst, mode);
232 newn = new_rd_SymConst_addr_ent(NULL, current_ir_graph, mode, ent, firm_unknown_type);
242 * Lower a all possible SymConst nodes.
244 static void lower_symconst(ir_node *symc) {
252 switch (get_SymConst_kind(symc)) {
253 case symconst_type_tag:
254 assert(!"SymConst kind symconst_type_tag not implemented");
256 case symconst_type_size:
257 /* rewrite the SymConst node by a Const node */
258 tp = get_SymConst_type(symc);
259 assert(get_type_state(tp) == layout_fixed);
260 mode = get_irn_mode(symc);
261 tv = new_tarval_from_long(get_type_size_bytes(tp), mode);
262 newn = new_Const(get_irn_mode(symc), tv);
266 exchange(symc, newn);
268 case symconst_type_align:
269 /* rewrite the SymConst node by a Const node */
270 tp = get_SymConst_type(symc);
271 assert(get_type_state(tp) == layout_fixed);
272 mode = get_irn_mode(symc);
273 tv = new_tarval_from_long(get_type_alignment_bytes(tp), mode);
274 newn = new_Const(mode, tv);
278 exchange(symc, newn);
280 case symconst_addr_name:
281 /* do not rewrite - pass info to back end */
283 case symconst_addr_ent:
286 case symconst_ofs_ent:
287 /* rewrite the SymConst node by a Const node */
288 ent = get_SymConst_entity(symc);
289 assert(get_type_state(get_entity_type(ent)) == layout_fixed);
290 mode = get_irn_mode(symc);
291 tv = new_tarval_from_long(get_entity_offset(ent), mode);
292 newn = new_Const(mode, tv);
296 exchange(symc, newn);
298 case symconst_enum_const:
299 /* rewrite the SymConst node by a Const node */
300 ec = get_SymConst_enum(symc);
301 assert(get_type_state(get_enumeration_owner(ec)) == layout_fixed);
302 tv = get_enumeration_value(ec);
303 newn = new_Const(get_irn_mode(symc), tv);
307 exchange(symc, newn);
314 assert(!"unknown SymConst kind");
317 } /* lower_symconst */
320 * Checks, whether a size is an integral size
322 * @param size the size on bits
324 static int is_integral_size(int size) {
328 /* must be at least byte size */
330 } /* is_integral_size */
333 * lower bitfield load access.
335 * @param proj the Proj(result) node
336 * @param load the Load node
338 static void lower_bitfields_loads(ir_node *proj, ir_node *load) {
339 ir_node *sel = get_Load_ptr(load);
340 ir_node *block, *n_proj, *res, *ptr;
343 ir_mode *bf_mode, *mode;
344 int offset, bit_offset, bits, bf_bits, old_cse;
350 ent = get_Sel_entity(sel);
351 bf_type = get_entity_type(ent);
353 /* must be a bitfield type */
354 if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
357 /* We have a bitfield access, if either a bit offset is given, or
358 the size is not integral. */
359 bf_mode = get_type_mode(bf_type);
363 mode = get_irn_mode(proj);
364 block = get_nodes_block(proj);
365 bf_bits = get_mode_size_bits(bf_mode);
366 bit_offset = get_entity_offset_bits_remainder(ent);
368 if (bit_offset == 0 && is_integral_size(bf_bits) && bf_mode == get_Load_mode(load))
371 bits = get_mode_size_bits(mode);
372 offset = get_entity_offset(ent);
375 * ok, here we are: now convert the Proj_mode_bf(Load) into And(Shr(Proj_mode(Load)) for unsigned
376 * and Shr(Shl(Proj_mode(load)) for signed
379 /* abandon bitfield sel */
380 ptr = get_Sel_ptr(sel);
381 db = get_irn_dbg_info(sel);
382 ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
384 set_Load_ptr(load, ptr);
385 set_Load_mode(load, mode);
388 /* create new proj, switch off CSE or we may get the old one back */
389 old_cse = get_opt_cse();
391 res = n_proj = new_r_Proj(current_ir_graph, block, load, mode, pn_Load_res);
392 set_opt_cse(old_cse);
394 if (mode_is_signed(mode)) { /* signed */
395 int shift_count_up = bits - (bf_bits + bit_offset);
396 int shift_count_down = bits - bf_bits;
398 if (shift_count_up) {
399 res = new_r_Shl(current_ir_graph, block, res,
400 new_Const(mode_Iu, new_tarval_from_long(shift_count_up, mode_Iu)), mode);
402 if (shift_count_down) {
403 res = new_r_Shrs(current_ir_graph, block, res,
404 new_Const(mode_Iu, new_tarval_from_long(shift_count_down, mode_Iu)), mode);
406 } else { /* unsigned */
407 int shift_count_down = bit_offset;
408 unsigned mask = ((unsigned)-1) >> (bits - bf_bits);
410 if (shift_count_down) {
411 res = new_r_Shr(current_ir_graph, block, res,
412 new_Const(mode_Iu, new_tarval_from_long(shift_count_down, mode_Iu)), mode);
414 if (bits != bf_bits) {
415 res = new_r_And(current_ir_graph, block, res,
416 new_Const(mode, new_tarval_from_long(mask, mode)), mode);
421 } /* lower_bitfields_loads */
424 * lower bitfield store access.
426 * @todo: It adds a load which may produce an exception!
428 static void lower_bitfields_stores(ir_node *store) {
429 ir_node *sel = get_Store_ptr(store);
430 ir_node *ptr, *value;
433 ir_mode *bf_mode, *mode;
434 ir_node *mem, *irn, *block;
435 unsigned mask, neg_mask;
436 int bf_bits, bits_mask, offset, bit_offset;
439 /* check bitfield access */
443 ent = get_Sel_entity(sel);
444 bf_type = get_entity_type(ent);
446 /* must be a bitfield type */
447 if (!is_Primitive_type(bf_type) || get_primitive_base_type(bf_type) == NULL)
450 /* We have a bitfield access, if either a bit offset is given, or
451 the size is not integral. */
452 bf_mode = get_type_mode(bf_type);
456 value = get_Store_value(store);
457 mode = get_irn_mode(value);
458 block = get_nodes_block(store);
460 bf_bits = get_mode_size_bits(bf_mode);
461 bit_offset = get_entity_offset_bits_remainder(ent);
463 if (bit_offset == 0 && is_integral_size(bf_bits) && bf_mode == get_irn_mode(value))
467 * ok, here we are: now convert the Store(Sel(), value) into Or(And(Load(Sel),c), And(Value,c))
469 mem = get_Store_mem(store);
470 offset = get_entity_offset(ent);
472 bits_mask = get_mode_size_bits(mode) - bf_bits;
473 mask = ((unsigned)-1) >> bits_mask;
477 /* abandon bitfield sel */
478 ptr = get_Sel_ptr(sel);
479 db = get_irn_dbg_info(sel);
480 ptr = new_rd_Add(db, current_ir_graph, block, ptr, new_Const_long(mode_Is, offset), get_irn_mode(ptr));
483 /* there are some bits, normal case */
484 irn = new_r_Load(current_ir_graph, block, mem, ptr, mode);
485 mem = new_r_Proj(current_ir_graph, block, irn, mode_M, pn_Load_M);
486 irn = new_r_Proj(current_ir_graph, block, irn, mode, pn_Load_res);
488 irn = new_r_And(current_ir_graph, block, irn,
489 new_Const(mode, new_tarval_from_long(neg_mask, mode)), mode);
491 if (bit_offset > 0) {
492 value = new_r_Shl(current_ir_graph, block, value,
493 new_Const(mode_Iu, new_tarval_from_long(bit_offset, mode_Iu)), mode);
496 value = new_r_And(current_ir_graph, block, value,
497 new_Const(mode, new_tarval_from_long(mask, mode)), mode);
499 value = new_r_Or(current_ir_graph, block, value, irn, mode);
502 set_Store_mem(store, mem);
503 set_Store_value(store, value);
504 set_Store_ptr(store, ptr);
505 } /* lower_bitfields_stores */
508 * Lowers unaligned Loads.
510 static void lower_unaligned_Load(ir_node *load) {
516 * Lowers unaligned Stores
518 static void lower_unaligned_Store(ir_node *store) {
524 * lowers IR-nodes, called from walker
526 static void lower_irnode(ir_node *irn, void *env) {
528 switch (get_irn_opcode(irn)) {
536 if (env != NULL && get_Load_align(irn) == align_non_aligned)
537 lower_unaligned_Load(irn);
540 if (env != NULL && get_Store_align(irn) == align_non_aligned)
541 lower_unaligned_Store(irn);
544 exchange(irn, get_Cast_op(irn));
552 * Walker: lowers IR-nodes for bitfield access
554 static void lower_bf_access(ir_node *irn, void *env) {
556 switch (get_irn_opcode(irn)) {
559 long proj = get_Proj_proj(irn);
560 ir_node *pred = get_Proj_pred(irn);
562 if (proj == pn_Load_res && is_Load(pred))
563 lower_bitfields_loads(irn, pred);
567 lower_bitfields_stores(irn);
573 } /* lower_bf_access */
576 * Replaces SymConsts by a real constant if possible.
577 * Replace Sel nodes by address computation. Also resolves array access.
578 * Handle Bitfields by added And/Or calculations.
580 void lower_highlevel_graph(ir_graph *irg, int lower_bitfields) {
582 if (lower_bitfields) {
583 /* First step: lower bitfield access: must be run as long as Sels still
585 irg_walk_graph(irg, NULL, lower_bf_access, NULL);
588 /* Finally: lower SymConst-Size and Sel nodes, Casts, unaligned Load/Stores. */
589 irg_walk_graph(irg, NULL, lower_irnode, NULL);
590 } /* lower_highlevel_graph */
593 * does the same as lower_highlevel() for all nodes on the const code irg
595 void lower_const_code(void) {
596 walk_const_code(NULL, lower_irnode, NULL);
597 } /* lower_const_code */
600 * Replaces SymConsts by a real constant if possible.
601 * Replace Sel nodes by address computation. Also resolves array access.
602 * Handle Bitfields by added And/Or calculations.
604 void lower_highlevel(int lower_bitfields) {
607 n = get_irp_n_irgs();
608 for (i = 0; i < n; ++i) {
609 ir_graph *irg = get_irp_irg(i);
610 lower_highlevel_graph(irg, lower_bitfields);
613 } /* lower_highlevel */