2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Lower Double word operations, ie 64bit -> 32bit, 32bit -> 16bit etc.
24 * @author Michael Beck
42 #include "irgraph_t.h"
47 #include "dbginfo_t.h"
48 #include "iropt_dbg.h"
62 /** A map from mode to a primitive type. */
63 static pmap *prim_types;
65 /** A map from (op, imode, omode) to Intrinsic functions entities. */
66 static set *intrinsic_fkt;
68 /** A map from (imode, omode) to conv function types. */
69 static set *conv_types;
71 /** A map from a method type to its lowered type. */
72 static pmap *lowered_type;
74 /** The types for the binop and unop intrinsics. */
75 static ir_type *binop_tp_u, *binop_tp_s, *unop_tp_u, *unop_tp_s, *shiftop_tp_u, *shiftop_tp_s, *tp_s, *tp_u;
77 /** the debug handle */
78 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
81 * An entry in the (op, imode, omode) -> entity map.
83 typedef struct _op_mode_entry {
84 const ir_op *op; /**< the op */
85 const ir_mode *imode; /**< the input mode */
86 const ir_mode *omode; /**< the output mode */
87 ir_entity *ent; /**< the associated entity of this (op, imode, omode) triple */
91 * An entry in the (imode, omode) -> tp map.
93 typedef struct _conv_tp_entry {
94 const ir_mode *imode; /**< the input mode */
95 const ir_mode *omode; /**< the output mode */
96 ir_type *mtd; /**< the associated method type of this (imode, omode) pair */
100 * Every double word node will be replaced,
101 * we need some store to hold the replacement:
103 typedef struct _node_entry_t {
104 ir_node *low_word; /**< the low word */
105 ir_node *high_word; /**< the high word */
109 MUST_BE_LOWERED = 1, /**< graph must be lowered */
110 CF_CHANGED = 2, /**< control flow was changed */
114 * The lower environment.
116 typedef struct _lower_env_t {
117 node_entry_t **entries; /**< entries per node */
118 struct obstack obst; /**< an obstack holding the temporary data */
119 tarval *tv_mode_bytes; /**< a tarval containing the number of bytes in the lowered modes */
120 tarval *tv_mode_bits; /**< a tarval containing the number of bits in the lowered modes */
121 pdeq *waitq; /**< a wait queue of all nodes that must be handled later */
122 pmap *proj_2_block; /**< a map from ProjX to its destination blocks */
123 const lwrdw_param_t *params; /**< transformation parameter */
124 unsigned flags; /**< some flags */
125 int n_entries; /**< number of entries */
129 * Get a primitive mode for a mode.
131 static ir_type *get_primitive_type(ir_mode *mode) {
132 pmap_entry *entry = pmap_find(prim_types, mode);
139 snprintf(buf, sizeof(buf), "_prim_%s", get_mode_name(mode));
140 tp = new_type_primitive(new_id_from_str(buf), mode);
142 pmap_insert(prim_types, mode, tp);
144 } /* get_primitive_type */
147 * Create a method type for a Conv emulation from imode to omode.
149 static ir_type *get_conv_type(ir_mode *imode, ir_mode *omode, lower_env_t *env) {
150 conv_tp_entry_t key, *entry;
157 entry = set_insert(conv_types, &key, sizeof(key), HASH_PTR(imode) ^ HASH_PTR(omode));
159 int n_param = 1, n_res = 1;
162 if (imode == env->params->high_signed || imode == env->params->high_unsigned)
164 if (omode == env->params->high_signed || omode == env->params->high_unsigned)
167 /* create a new one */
168 snprintf(buf, sizeof(buf), "LConv%s%s", get_mode_name(imode), get_mode_name(omode));
169 mtd = new_type_method(new_id_from_str(buf), n_param, n_res);
171 /* set param types and result types */
173 if (imode == env->params->high_signed) {
174 set_method_param_type(mtd, n_param++, tp_u);
175 set_method_param_type(mtd, n_param++, tp_s);
176 } else if (imode == env->params->high_unsigned) {
177 set_method_param_type(mtd, n_param++, tp_u);
178 set_method_param_type(mtd, n_param++, tp_u);
180 ir_type *tp = get_primitive_type(imode);
181 set_method_param_type(mtd, n_param++, tp);
185 if (omode == env->params->high_signed) {
186 set_method_res_type(mtd, n_res++, tp_u);
187 set_method_res_type(mtd, n_res++, tp_s);
188 } else if (omode == env->params->high_unsigned) {
189 set_method_res_type(mtd, n_res++, tp_u);
190 set_method_res_type(mtd, n_res++, tp_u);
192 ir_type *tp = get_primitive_type(omode);
193 set_method_res_type(mtd, n_res++, tp);
200 } /* get_conv_type */
203 * Add an additional control flow input to a block.
204 * Patch all Phi nodes. The new Phi inputs are copied from
205 * old input number nr.
207 static void add_block_cf_input_nr(ir_node *block, int nr, ir_node *cf)
209 int i, arity = get_irn_arity(block);
214 NEW_ARR_A(ir_node *, in, arity + 1);
215 for (i = 0; i < arity; ++i)
216 in[i] = get_irn_n(block, i);
219 set_irn_in(block, i + 1, in);
221 for (phi = get_irn_link(block); phi; phi = get_irn_link(phi)) {
222 for (i = 0; i < arity; ++i)
223 in[i] = get_irn_n(phi, i);
225 set_irn_in(phi, i + 1, in);
227 } /* add_block_cf_input_nr */
230 * Add an additional control flow input to a block.
231 * Patch all Phi nodes. The new Phi inputs are copied from
232 * old input from cf tmpl.
234 static void add_block_cf_input(ir_node *block, ir_node *tmpl, ir_node *cf)
236 int i, arity = get_irn_arity(block);
239 for (i = 0; i < arity; ++i) {
240 if (get_irn_n(block, i) == tmpl) {
246 add_block_cf_input_nr(block, nr, cf);
247 } /* add_block_cf_input */
250 * Return the "operational" mode of a Firm node.
252 static ir_mode *get_irn_op_mode(ir_node *node)
254 switch (get_irn_opcode(node)) {
256 return get_Load_mode(node);
258 return get_irn_mode(get_Store_value(node));
260 return get_irn_mode(get_DivMod_left(node));
262 return get_irn_mode(get_Div_left(node));
264 return get_irn_mode(get_Mod_left(node));
266 return get_irn_mode(get_Cmp_left(node));
268 return get_irn_mode(node);
270 } /* get_irn_op_mode */
273 * Walker, prepare the node links.
275 static void prepare_links(ir_node *node, void *env)
277 lower_env_t *lenv = env;
278 ir_mode *mode = get_irn_op_mode(node);
282 if (mode == lenv->params->high_signed ||
283 mode == lenv->params->high_unsigned) {
284 /* ok, found a node that will be lowered */
285 link = obstack_alloc(&lenv->obst, sizeof(*link));
287 memset(link, 0, sizeof(*link));
289 lenv->entries[get_irn_idx(node)] = link;
290 lenv->flags |= MUST_BE_LOWERED;
291 } else if (get_irn_op(node) == op_Conv) {
292 /* Conv nodes have two modes */
293 ir_node *pred = get_Conv_op(node);
294 mode = get_irn_mode(pred);
296 if (mode == lenv->params->high_signed ||
297 mode == lenv->params->high_unsigned) {
298 /* must lower this node either but don't need a link */
299 lenv->flags |= MUST_BE_LOWERED;
305 /* link all Proj nodes to its predecessor:
306 Note that Tuple Proj's and its Projs are linked either. */
307 ir_node *pred = get_Proj_pred(node);
309 set_irn_link(node, get_irn_link(pred));
310 set_irn_link(pred, node);
311 } else if (is_Phi(node)) {
312 /* link all Phi nodes to its block */
313 ir_node *block = get_nodes_block(node);
315 set_irn_link(node, get_irn_link(block));
316 set_irn_link(block, node);
317 } else if (is_Block(node)) {
318 /* fill the Proj -> Block map */
319 for (i = get_Block_n_cfgpreds(node) - 1; i >= 0; --i) {
320 ir_node *pred = get_Block_cfgpred(node, i);
323 pmap_insert(lenv->proj_2_block, pred, node);
326 } /* prepare_links */
329 * Translate a Constant: create two.
331 static void lower_Const(ir_node *node, ir_mode *mode, lower_env_t *env) {
332 tarval *tv, *tv_l, *tv_h;
334 dbg_info *dbg = get_irn_dbg_info(node);
335 ir_node *block = get_nodes_block(node);
337 ir_graph *irg = current_ir_graph;
338 ir_mode *low_mode = env->params->low_unsigned;
340 tv = get_Const_tarval(node);
342 tv_l = tarval_convert_to(tv, low_mode);
343 low = new_rd_Const(dbg, irg, block, low_mode, tv_l);
345 tv_h = tarval_convert_to(tarval_shrs(tv, env->tv_mode_bits), mode);
346 high = new_rd_Const(dbg, irg, block, mode, tv_h);
348 idx = get_irn_idx(node);
349 assert(idx < env->n_entries);
350 env->entries[idx]->low_word = low;
351 env->entries[idx]->high_word = high;
355 * Translate a Load: create two.
357 static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env) {
358 ir_mode *low_mode = env->params->low_unsigned;
359 ir_graph *irg = current_ir_graph;
360 ir_node *adr = get_Load_ptr(node);
361 ir_node *mem = get_Load_mem(node);
362 ir_node *low, *high, *proj;
364 ir_node *block = get_nodes_block(node);
367 if (env->params->little_endian) {
369 high = new_r_Add(irg, block, adr,
370 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
373 low = new_r_Add(irg, block, adr,
374 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
379 /* create two loads */
380 dbg = get_irn_dbg_info(node);
381 low = new_rd_Load(dbg, irg, block, mem, low, low_mode);
382 proj = new_r_Proj(irg, block, low, mode_M, pn_Load_M);
383 high = new_rd_Load(dbg, irg, block, proj, high, mode);
385 set_Load_volatility(low, get_Load_volatility(node));
386 set_Load_volatility(high, get_Load_volatility(node));
388 idx = get_irn_idx(node);
389 assert(idx < env->n_entries);
390 env->entries[idx]->low_word = low;
391 env->entries[idx]->high_word = high;
393 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
394 idx = get_irn_idx(proj);
396 switch (get_Proj_proj(proj)) {
397 case pn_Load_M: /* Memory result. */
398 /* put it to the second one */
399 set_Proj_pred(proj, high);
401 case pn_Load_X_except: /* Execution result if exception occurred. */
402 /* put it to the first one */
403 set_Proj_pred(proj, low);
405 case pn_Load_res: /* Result of load operation. */
406 assert(idx < env->n_entries);
407 env->entries[idx]->low_word = new_r_Proj(irg, block, low, low_mode, pn_Load_res);
408 env->entries[idx]->high_word = new_r_Proj(irg, block, high, mode, pn_Load_res);
411 assert(0 && "unexpected Proj number");
413 /* mark this proj: we have handled it already, otherwise we might fall into
415 mark_irn_visited(proj);
420 * Translate a Store: create two.
422 static void lower_Store(ir_node *node, ir_mode *mode, lower_env_t *env) {
424 ir_node *block, *adr, *mem;
425 ir_node *low, *high, *irn, *proj;
432 irn = get_Store_value(node);
433 entry = env->entries[get_irn_idx(irn)];
436 if (! entry->low_word) {
437 /* not ready yet, wait */
438 pdeq_putr(env->waitq, node);
442 irg = current_ir_graph;
443 adr = get_Store_ptr(node);
444 mem = get_Store_mem(node);
445 block = get_nodes_block(node);
447 if (env->params->little_endian) {
449 high = new_r_Add(irg, block, adr,
450 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
453 low = new_r_Add(irg, block, adr,
454 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
459 /* create two Stores */
460 dbg = get_irn_dbg_info(node);
461 low = new_rd_Store(dbg, irg, block, mem, low, entry->low_word);
462 proj = new_r_Proj(irg, block, low, mode_M, pn_Store_M);
463 high = new_rd_Store(dbg, irg, block, proj, high, entry->high_word);
465 set_Store_volatility(low, get_Store_volatility(node));
466 set_Store_volatility(high, get_Store_volatility(node));
468 idx = get_irn_idx(node);
469 assert(idx < env->n_entries);
470 env->entries[idx]->low_word = low;
471 env->entries[idx]->high_word = high;
473 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
474 idx = get_irn_idx(proj);
476 switch (get_Proj_proj(proj)) {
477 case pn_Store_M: /* Memory result. */
478 /* put it to the second one */
479 set_Proj_pred(proj, high);
481 case pn_Store_X_except: /* Execution result if exception occurred. */
482 /* put it to the first one */
483 set_Proj_pred(proj, low);
486 assert(0 && "unexpected Proj number");
488 /* mark this proj: we have handled it already, otherwise we might fall into
490 mark_irn_visited(proj);
495 * Return a node containing the address of the intrinsic emulation function.
497 * @param method the method type of the emulation function
498 * @param op the emulated ir_op
499 * @param imode the input mode of the emulated opcode
500 * @param omode the output mode of the emulated opcode
501 * @param block where the new mode is created
502 * @param env the lower environment
504 static ir_node *get_intrinsic_address(ir_type *method, ir_op *op,
505 ir_mode *imode, ir_mode *omode,
506 ir_node *block, lower_env_t *env) {
509 op_mode_entry_t key, *entry;
516 entry = set_insert(intrinsic_fkt, &key, sizeof(key),
517 HASH_PTR(op) ^ HASH_PTR(imode) ^ (HASH_PTR(omode) << 8));
519 /* create a new one */
520 ent = env->params->create_intrinsic(method, op, imode, omode, env->params->ctx);
522 assert(ent && "Intrinsic creator must return an entity");
528 return new_r_SymConst(current_ir_graph, block, sym, symconst_addr_ent);
529 } /* get_intrinsic_address */
534 * Create an intrinsic Call.
536 static void lower_Div(ir_node *node, ir_mode *mode, lower_env_t *env) {
537 ir_node *block, *irn, *call, *proj;
546 irn = get_Div_left(node);
547 entry = env->entries[get_irn_idx(irn)];
550 if (! entry->low_word) {
551 /* not ready yet, wait */
552 pdeq_putr(env->waitq, node);
556 in[0] = entry->low_word;
557 in[1] = entry->high_word;
559 irn = get_Div_right(node);
560 entry = env->entries[get_irn_idx(irn)];
563 if (! entry->low_word) {
564 /* not ready yet, wait */
565 pdeq_putr(env->waitq, node);
569 in[2] = entry->low_word;
570 in[3] = entry->high_word;
572 dbg = get_irn_dbg_info(node);
573 block = get_nodes_block(node);
574 irg = current_ir_graph;
576 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
577 opmode = get_irn_op_mode(node);
578 irn = get_intrinsic_address(mtp, get_irn_op(node), opmode, opmode, block, env);
579 call = new_rd_Call(dbg, irg, block, get_Div_mem(node),
581 set_irn_pinned(call, get_irn_pinned(node));
582 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
584 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
585 switch (get_Proj_proj(proj)) {
586 case pn_Div_M: /* Memory result. */
587 /* reroute to the call */
588 set_Proj_pred(proj, call);
589 set_Proj_proj(proj, pn_Call_M_except);
591 case pn_Div_X_except: /* Execution result if exception occurred. */
592 /* reroute to the call */
593 set_Proj_pred(proj, call);
594 set_Proj_proj(proj, pn_Call_X_except);
596 case pn_Div_res: /* Result of computation. */
597 idx = get_irn_idx(proj);
598 assert(idx < env->n_entries);
599 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, env->params->low_unsigned, 0);
600 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
603 assert(0 && "unexpected Proj number");
605 /* mark this proj: we have handled it already, otherwise we might fall into
607 mark_irn_visited(proj);
614 * Create an intrinsic Call.
616 static void lower_Mod(ir_node *node, ir_mode *mode, lower_env_t *env) {
617 ir_node *block, *proj, *irn, *call;
626 irn = get_Mod_left(node);
627 entry = env->entries[get_irn_idx(irn)];
630 if (! entry->low_word) {
631 /* not ready yet, wait */
632 pdeq_putr(env->waitq, node);
636 in[0] = entry->low_word;
637 in[1] = entry->high_word;
639 irn = get_Mod_right(node);
640 entry = env->entries[get_irn_idx(irn)];
643 if (! entry->low_word) {
644 /* not ready yet, wait */
645 pdeq_putr(env->waitq, node);
649 in[2] = entry->low_word;
650 in[3] = entry->high_word;
652 dbg = get_irn_dbg_info(node);
653 block = get_nodes_block(node);
654 irg = current_ir_graph;
656 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
657 opmode = get_irn_op_mode(node);
658 irn = get_intrinsic_address(mtp, get_irn_op(node), opmode, opmode, block, env);
659 call = new_rd_Call(dbg, irg, block, get_Mod_mem(node),
661 set_irn_pinned(call, get_irn_pinned(node));
662 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
664 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
665 switch (get_Proj_proj(proj)) {
666 case pn_Mod_M: /* Memory result. */
667 /* reroute to the call */
668 set_Proj_pred(proj, call);
669 set_Proj_proj(proj, pn_Call_M_except);
671 case pn_Mod_X_except: /* Execution result if exception occurred. */
672 /* reroute to the call */
673 set_Proj_pred(proj, call);
674 set_Proj_proj(proj, pn_Call_X_except);
676 case pn_Mod_res: /* Result of computation. */
677 idx = get_irn_idx(proj);
678 assert(idx < env->n_entries);
679 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
680 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
683 assert(0 && "unexpected Proj number");
685 /* mark this proj: we have handled it already, otherwise we might fall into
687 mark_irn_visited(proj);
692 * Translate a DivMod.
694 * Create two intrinsic Calls.
696 static void lower_DivMod(ir_node *node, ir_mode *mode, lower_env_t *env) {
697 ir_node *block, *proj, *irn, *mem, *callDiv, *callMod;
698 ir_node *resDiv = NULL;
699 ir_node *resMod = NULL;
709 /* check if both results are needed */
710 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
711 switch (get_Proj_proj(proj)) {
712 case pn_DivMod_res_div: flags |= 1; break;
713 case pn_DivMod_res_mod: flags |= 2; break;
718 irn = get_DivMod_left(node);
719 entry = env->entries[get_irn_idx(irn)];
722 if (! entry->low_word) {
723 /* not ready yet, wait */
724 pdeq_putr(env->waitq, node);
728 in[0] = entry->low_word;
729 in[1] = entry->high_word;
731 irn = get_DivMod_right(node);
732 entry = env->entries[get_irn_idx(irn)];
735 if (! entry->low_word) {
736 /* not ready yet, wait */
737 pdeq_putr(env->waitq, node);
741 in[2] = entry->low_word;
742 in[3] = entry->high_word;
744 dbg = get_irn_dbg_info(node);
745 block = get_nodes_block(node);
746 irg = current_ir_graph;
748 mem = get_DivMod_mem(node);
750 callDiv = callMod = NULL;
751 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
753 opmode = get_irn_op_mode(node);
754 irn = get_intrinsic_address(mtp, op_Div, opmode, opmode, block, env);
755 callDiv = new_rd_Call(dbg, irg, block, mem,
757 set_irn_pinned(callDiv, get_irn_pinned(node));
758 resDiv = new_r_Proj(irg, block, callDiv, mode_T, pn_Call_T_result);
762 mem = new_r_Proj(irg, block, callDiv, mode_M, pn_Call_M);
763 opmode = get_irn_op_mode(node);
764 irn = get_intrinsic_address(mtp, op_Mod, opmode, opmode, block, env);
765 callMod = new_rd_Call(dbg, irg, block, mem,
767 set_irn_pinned(callMod, get_irn_pinned(node));
768 resMod = new_r_Proj(irg, block, callMod, mode_T, pn_Call_T_result);
771 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
772 switch (get_Proj_proj(proj)) {
773 case pn_DivMod_M: /* Memory result. */
774 /* reroute to the first call */
775 set_Proj_pred(proj, callDiv ? callDiv : (callMod ? callMod : mem));
776 set_Proj_proj(proj, pn_Call_M_except);
778 case pn_DivMod_X_except: /* Execution result if exception occurred. */
779 /* reroute to the first call */
780 set_Proj_pred(proj, callDiv ? callDiv : (callMod ? callMod : mem));
781 set_Proj_proj(proj, pn_Call_X_except);
783 case pn_DivMod_res_div: /* Result of Div. */
784 idx = get_irn_idx(proj);
785 assert(idx < env->n_entries);
786 env->entries[idx]->low_word = new_r_Proj(irg, block, resDiv, env->params->low_unsigned, 0);
787 env->entries[idx]->high_word = new_r_Proj(irg, block, resDiv, mode, 1);
789 case pn_DivMod_res_mod: /* Result of Mod. */
790 idx = get_irn_idx(proj);
791 env->entries[idx]->low_word = new_r_Proj(irg, block, resMod, env->params->low_unsigned, 0);
792 env->entries[idx]->high_word = new_r_Proj(irg, block, resMod, mode, 1);
795 assert(0 && "unexpected Proj number");
797 /* mark this proj: we have handled it already, otherwise we might fall into
799 mark_irn_visited(proj);
806 * Create an intrinsic Call.
808 static void lower_Binop(ir_node *node, ir_mode *mode, lower_env_t *env) {
809 ir_node *block, *irn;
817 irn = get_binop_left(node);
818 entry = env->entries[get_irn_idx(irn)];
821 if (! entry->low_word) {
822 /* not ready yet, wait */
823 pdeq_putr(env->waitq, node);
827 in[0] = entry->low_word;
828 in[1] = entry->high_word;
830 irn = get_binop_right(node);
831 entry = env->entries[get_irn_idx(irn)];
834 if (! entry->low_word) {
835 /* not ready yet, wait */
836 pdeq_putr(env->waitq, node);
840 in[2] = entry->low_word;
841 in[3] = entry->high_word;
843 dbg = get_irn_dbg_info(node);
844 block = get_nodes_block(node);
845 irg = current_ir_graph;
847 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
848 irn = get_intrinsic_address(mtp, get_irn_op(node), mode, mode, block, env);
849 irn = new_rd_Call(dbg, irg, block, get_irg_no_mem(current_ir_graph),
851 set_irn_pinned(irn, get_irn_pinned(node));
852 irn = new_r_Proj(irg, block, irn, mode_T, pn_Call_T_result);
854 idx = get_irn_idx(node);
855 assert(idx < env->n_entries);
856 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
857 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
861 * Translate a Shiftop.
863 * Create an intrinsic Call.
865 static void lower_Shiftop(ir_node *node, ir_mode *mode, lower_env_t *env) {
866 ir_node *block, *irn;
874 irn = get_binop_left(node);
875 entry = env->entries[get_irn_idx(irn)];
878 if (! entry->low_word) {
879 /* not ready yet, wait */
880 pdeq_putr(env->waitq, node);
884 in[0] = entry->low_word;
885 in[1] = entry->high_word;
887 /* The shift count is always mode_Iu in firm, so there is no need for lowering */
888 in[2] = get_binop_right(node);
890 dbg = get_irn_dbg_info(node);
891 block = get_nodes_block(node);
892 irg = current_ir_graph;
894 mtp = mode_is_signed(mode) ? shiftop_tp_s : shiftop_tp_u;
895 irn = get_intrinsic_address(mtp, get_irn_op(node), mode, mode, block, env);
896 irn = new_rd_Call(dbg, irg, block, get_irg_no_mem(current_ir_graph),
898 set_irn_pinned(irn, get_irn_pinned(node));
899 irn = new_r_Proj(irg, block, irn, mode_T, pn_Call_T_result);
901 idx = get_irn_idx(node);
902 assert(idx < env->n_entries);
903 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
904 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
905 } /* lower_Shiftop */
908 * Translate a Shr and handle special cases.
910 static void lower_Shr(ir_node *node, ir_mode *mode, lower_env_t *env) {
911 ir_node *right = get_Shr_right(node);
912 ir_graph *irg = current_ir_graph;
914 if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
915 tarval *tv = get_Const_tarval(right);
917 if (tarval_is_long(tv) &&
918 get_tarval_long(tv) >= get_mode_size_bits(mode)) {
919 ir_node *block = get_nodes_block(node);
920 ir_node *left = get_Shr_left(node);
922 long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
923 int idx = get_irn_idx(left);
925 left = env->entries[idx]->high_word;
926 idx = get_irn_idx(node);
929 c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
930 env->entries[idx]->low_word = new_r_Shr(irg, block, left, c, mode);
932 env->entries[idx]->low_word = left;
934 env->entries[idx]->high_word = new_r_Const(irg, block, mode, get_mode_null(mode));
939 lower_Shiftop(node, mode, env);
943 * Translate a Shl and handle special cases.
945 static void lower_Shl(ir_node *node, ir_mode *mode, lower_env_t *env) {
946 ir_node *right = get_Shl_right(node);
947 ir_graph *irg = current_ir_graph;
949 if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
950 tarval *tv = get_Const_tarval(right);
952 if (tarval_is_long(tv) &&
953 get_tarval_long(tv) >= get_mode_size_bits(mode)) {
954 ir_node *block = get_nodes_block(node);
955 ir_node *left = get_Shl_left(node);
957 long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
958 int idx = get_irn_idx(left);
960 left = env->entries[idx]->low_word;
961 idx = get_irn_idx(node);
964 c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
965 env->entries[idx]->high_word = new_r_Shl(irg, block, left, c, mode);
967 env->entries[idx]->high_word = left;
969 env->entries[idx]->low_word = new_r_Const(irg, block, mode, get_mode_null(mode));
974 lower_Shiftop(node, mode, env);
978 * Translate a Shrs and handle special cases.
980 static void lower_Shrs(ir_node *node, ir_mode *mode, lower_env_t *env) {
981 ir_node *right = get_Shrs_right(node);
982 ir_graph *irg = current_ir_graph;
984 if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
985 tarval *tv = get_Const_tarval(right);
987 if (tarval_is_long(tv) &&
988 get_tarval_long(tv) >= get_mode_size_bits(mode)) {
989 ir_node *block = get_nodes_block(node);
990 ir_node *left = get_Shrs_left(node);
991 long shf_cnt = get_tarval_long(tv) - get_mode_size_bits(mode);
993 int idx = get_irn_idx(left);
995 left = env->entries[idx]->high_word;
996 idx = get_irn_idx(node);
999 c = new_r_Const_long(irg, block, mode_Iu, shf_cnt);
1000 env->entries[idx]->low_word = new_r_Shrs(irg, block, left, c, mode);
1002 env->entries[idx]->low_word = left;
1004 c = new_r_Const_long(irg, block, mode_Iu, get_mode_size_bits(mode) - 1);
1005 env->entries[idx]->high_word = new_r_Shrs(irg, block, left, c, mode);
1010 lower_Shiftop(node, mode, env);
1014 * Translate a Rot and handle special cases.
1016 static void lower_Rot(ir_node *node, ir_mode *mode, lower_env_t *env) {
1017 ir_node *right = get_Rot_right(node);
1019 if (get_mode_arithmetic(mode) == irma_twos_complement && is_Const(right)) {
1020 tarval *tv = get_Const_tarval(right);
1022 if (tarval_is_long(tv) &&
1023 get_tarval_long(tv) == get_mode_size_bits(mode)) {
1024 ir_node *left = get_Rot_left(node);
1026 int idx = get_irn_idx(left);
1028 l = env->entries[idx]->low_word;
1029 h = env->entries[idx]->high_word;
1030 idx = get_irn_idx(node);
1032 env->entries[idx]->low_word = h;
1033 env->entries[idx]->high_word = l;
1038 lower_Shiftop(node, mode, env);
1042 * Translate an Unop.
1044 * Create an intrinsic Call.
1046 static void lower_Unop(ir_node *node, ir_mode *mode, lower_env_t *env) {
1047 ir_node *block, *irn;
1053 node_entry_t *entry;
1055 irn = get_unop_op(node);
1056 entry = env->entries[get_irn_idx(irn)];
1059 if (! entry->low_word) {
1060 /* not ready yet, wait */
1061 pdeq_putr(env->waitq, node);
1065 in[0] = entry->low_word;
1066 in[1] = entry->high_word;
1068 dbg = get_irn_dbg_info(node);
1069 block = get_nodes_block(node);
1070 irg = current_ir_graph;
1072 mtp = mode_is_signed(mode) ? unop_tp_s : unop_tp_u;
1073 irn = get_intrinsic_address(mtp, get_irn_op(node), mode, mode, block, env);
1074 irn = new_rd_Call(dbg, irg, block, get_irg_no_mem(current_ir_graph),
1076 set_irn_pinned(irn, get_irn_pinned(node));
1077 irn = new_r_Proj(irg, block, irn, mode_T, pn_Call_T_result);
1079 idx = get_irn_idx(node);
1080 assert(idx < env->n_entries);
1081 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, env->params->low_unsigned, 0);
1082 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, mode, 1);
1086 * Translate a logical Binop.
1088 * Create two logical Binops.
1090 static void lower_Binop_logical(ir_node *node, ir_mode *mode, lower_env_t *env,
1091 ir_node *(*constr_rd)(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) ) {
1092 ir_node *block, *irn;
1093 ir_node *lop_l, *lop_h, *rop_l, *rop_h;
1097 node_entry_t *entry;
1099 irn = get_binop_left(node);
1100 entry = env->entries[get_irn_idx(irn)];
1103 if (! entry->low_word) {
1104 /* not ready yet, wait */
1105 pdeq_putr(env->waitq, node);
1109 lop_l = entry->low_word;
1110 lop_h = entry->high_word;
1112 irn = get_binop_right(node);
1113 entry = env->entries[get_irn_idx(irn)];
1116 if (! entry->low_word) {
1117 /* not ready yet, wait */
1118 pdeq_putr(env->waitq, node);
1122 rop_l = entry->low_word;
1123 rop_h = entry->high_word;
1125 dbg = get_irn_dbg_info(node);
1126 block = get_nodes_block(node);
1128 idx = get_irn_idx(node);
1129 assert(idx < env->n_entries);
1130 irg = current_ir_graph;
1131 env->entries[idx]->low_word = constr_rd(dbg, irg, block, lop_l, rop_l, env->params->low_unsigned);
1132 env->entries[idx]->high_word = constr_rd(dbg, irg, block, lop_h, rop_h, mode);
1133 } /* lower_Binop_logical */
1135 /** create a logical operation tranformation */
1136 #define lower_logical(op) \
1137 static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \
1138 lower_Binop_logical(node, mode, env, new_rd_##op); \
1148 * Create two logical Nots.
1150 static void lower_Not(ir_node *node, ir_mode *mode, lower_env_t *env) {
1151 ir_node *block, *irn;
1152 ir_node *op_l, *op_h;
1156 node_entry_t *entry;
1158 irn = get_Not_op(node);
1159 entry = env->entries[get_irn_idx(irn)];
1162 if (! entry->low_word) {
1163 /* not ready yet, wait */
1164 pdeq_putr(env->waitq, node);
1168 op_l = entry->low_word;
1169 op_h = entry->high_word;
1171 dbg = get_irn_dbg_info(node);
1172 block = get_nodes_block(node);
1173 irg = current_ir_graph;
1175 idx = get_irn_idx(node);
1176 assert(idx < env->n_entries);
1177 env->entries[idx]->low_word = new_rd_Not(dbg, current_ir_graph, block, op_l, env->params->low_unsigned);
1178 env->entries[idx]->high_word = new_rd_Not(dbg, current_ir_graph, block, op_h, mode);
1184 static void lower_Cond(ir_node *node, ir_mode *mode, lower_env_t *env) {
1185 ir_node *cmp, *left, *right, *block;
1186 ir_node *sel = get_Cond_selector(node);
1187 ir_mode *m = get_irn_mode(sel);
1192 node_entry_t *lentry, *rentry;
1193 ir_node *proj, *projT = NULL, *projF = NULL;
1194 ir_node *new_bl, *cmpH, *cmpL, *irn;
1195 ir_node *projHF, *projHT;
1204 cmp = get_Proj_pred(sel);
1208 left = get_Cmp_left(cmp);
1209 idx = get_irn_idx(left);
1210 lentry = env->entries[idx];
1217 right = get_Cmp_right(cmp);
1218 idx = get_irn_idx(right);
1219 rentry = env->entries[idx];
1222 if (! lentry->low_word || !rentry->low_word) {
1224 pdeq_putr(env->waitq, node);
1228 /* all right, build the code */
1229 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
1230 long proj_nr = get_Proj_proj(proj);
1232 if (proj_nr == pn_Cond_true) {
1233 assert(projT == NULL && "more than one Proj(true)");
1236 assert(proj_nr == pn_Cond_false);
1237 assert(projF == NULL && "more than one Proj(false)");
1240 mark_irn_visited(proj);
1242 assert(projT && projF);
1244 /* create a new high compare */
1245 block = get_nodes_block(cmp);
1246 dbg = get_irn_dbg_info(cmp);
1247 irg = current_ir_graph;
1249 cmpH = new_rd_Cmp(dbg, irg, block, lentry->high_word, rentry->high_word);
1251 pnc = get_Proj_proj(sel);
1252 if (pnc == pn_Cmp_Eq) {
1253 /* simple case:a == b <==> a_h == b_h && a_l == b_l */
1254 pmap_entry *entry = pmap_find(env->proj_2_block, projF);
1257 dst_blk = entry->value;
1259 irn = new_r_Proj(irg, block, cmpH, mode_b, pn_Cmp_Eq);
1260 dbg = get_irn_dbg_info(node);
1261 irn = new_rd_Cond(dbg, irg, block, irn);
1263 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
1264 mark_irn_visited(projHF);
1265 exchange(projF, projHF);
1267 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
1268 mark_irn_visited(projHT);
1270 new_bl = new_r_Block(irg, 1, &projHT);
1272 dbg = get_irn_dbg_info(cmp);
1273 cmpL = new_rd_Cmp(dbg, irg, new_bl, lentry->low_word, rentry->low_word);
1274 irn = new_r_Proj(irg, new_bl, cmpL, mode_b, pn_Cmp_Eq);
1275 dbg = get_irn_dbg_info(node);
1276 irn = new_rd_Cond(dbg, irg, new_bl, irn);
1278 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_false);
1279 mark_irn_visited(proj);
1280 add_block_cf_input(dst_blk, projHF, proj);
1282 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_true);
1283 mark_irn_visited(proj);
1284 exchange(projT, proj);
1285 } else if (pnc == pn_Cmp_Lg) {
1286 /* simple case:a != b <==> a_h != b_h || a_l != b_l */
1287 pmap_entry *entry = pmap_find(env->proj_2_block, projT);
1290 dst_blk = entry->value;
1292 irn = new_r_Proj(irg, block, cmpH, mode_b, pn_Cmp_Lg);
1293 dbg = get_irn_dbg_info(node);
1294 irn = new_rd_Cond(dbg, irg, block, irn);
1296 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
1297 mark_irn_visited(projHT);
1298 exchange(projT, projHT);
1300 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
1301 mark_irn_visited(projHF);
1303 new_bl = new_r_Block(irg, 1, &projHF);
1305 dbg = get_irn_dbg_info(cmp);
1306 cmpL = new_rd_Cmp(dbg, irg, new_bl, lentry->low_word, rentry->low_word);
1307 irn = new_r_Proj(irg, new_bl, cmpL, mode_b, pn_Cmp_Lg);
1308 dbg = get_irn_dbg_info(node);
1309 irn = new_rd_Cond(dbg, irg, new_bl, irn);
1311 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_true);
1312 mark_irn_visited(proj);
1313 add_block_cf_input(dst_blk, projHT, proj);
1315 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_false);
1316 mark_irn_visited(proj);
1317 exchange(projF, proj);
1319 /* a rel b <==> a_h REL b_h || (a_h == b_h && a_l rel b_l) */
1320 ir_node *dstT, *dstF, *newbl_eq, *newbl_l;
1323 entry = pmap_find(env->proj_2_block, projT);
1325 dstT = entry->value;
1327 entry = pmap_find(env->proj_2_block, projF);
1329 dstF = entry->value;
1331 irn = new_r_Proj(irg, block, cmpH, mode_b, pnc & ~pn_Cmp_Eq);
1332 dbg = get_irn_dbg_info(node);
1333 irn = new_rd_Cond(dbg, irg, block, irn);
1335 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
1336 mark_irn_visited(projHT);
1337 exchange(projT, projHT);
1340 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
1341 mark_irn_visited(projHF);
1343 newbl_eq = new_r_Block(irg, 1, &projHF);
1345 irn = new_r_Proj(irg, newbl_eq, cmpH, mode_b, pn_Cmp_Eq);
1346 irn = new_rd_Cond(dbg, irg, newbl_eq, irn);
1348 proj = new_r_Proj(irg, newbl_eq, irn, mode_X, pn_Cond_false);
1349 mark_irn_visited(proj);
1350 exchange(projF, proj);
1353 proj = new_r_Proj(irg, newbl_eq, irn, mode_X, pn_Cond_true);
1354 mark_irn_visited(proj);
1356 newbl_l = new_r_Block(irg, 1, &proj);
1358 dbg = get_irn_dbg_info(cmp);
1359 cmpL = new_rd_Cmp(dbg, irg, newbl_l, lentry->low_word, rentry->low_word);
1360 irn = new_r_Proj(irg, newbl_l, cmpL, mode_b, pnc);
1361 dbg = get_irn_dbg_info(node);
1362 irn = new_rd_Cond(dbg, irg, newbl_l, irn);
1364 proj = new_r_Proj(irg, newbl_l, irn, mode_X, pn_Cond_true);
1365 mark_irn_visited(proj);
1366 add_block_cf_input(dstT, projT, proj);
1368 proj = new_r_Proj(irg, newbl_l, irn, mode_X, pn_Cond_false);
1369 mark_irn_visited(proj);
1370 add_block_cf_input(dstF, projF, proj);
1373 /* we have changed the control flow */
1374 env->flags |= CF_CHANGED;
1376 idx = get_irn_idx(sel);
1378 if (env->entries[idx]) {
1380 Bad, a jump-table with double-word index.
1381 This should not happen, but if it does we handle
1382 it like a Conv were between (in other words, ignore
1386 if (! env->entries[idx]->low_word) {
1387 /* not ready yet, wait */
1388 pdeq_putr(env->waitq, node);
1391 set_Cond_selector(node, env->entries[idx]->low_word);
1397 * Translate a Conv to higher_signed
1399 static void lower_Conv_to_Ls(ir_node *node, lower_env_t *env) {
1400 ir_node *op = get_Conv_op(node);
1401 ir_mode *imode = get_irn_mode(op);
1402 ir_mode *dst_mode_l = env->params->low_unsigned;
1403 ir_mode *dst_mode_h = env->params->low_signed;
1404 int idx = get_irn_idx(node);
1405 ir_graph *irg = current_ir_graph;
1406 ir_node *block = get_nodes_block(node);
1407 dbg_info *dbg = get_irn_dbg_info(node);
1409 assert(idx < env->n_entries);
1411 if (mode_is_int(imode) || mode_is_reference(imode)) {
1412 if (imode == env->params->high_unsigned) {
1413 /* a Conv from Lu to Ls */
1414 int op_idx = get_irn_idx(op);
1416 if (! env->entries[op_idx]->low_word) {
1417 /* not ready yet, wait */
1418 pdeq_putr(env->waitq, node);
1421 env->entries[idx]->low_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->low_word, dst_mode_l);
1422 env->entries[idx]->high_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->high_word, dst_mode_h);
1424 /* simple case: create a high word */
1425 if (imode != dst_mode_l)
1426 op = new_rd_Conv(dbg, irg, block, op, dst_mode_l);
1428 env->entries[idx]->low_word = op;
1430 if (mode_is_signed(imode)) {
1431 env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
1432 new_Const_long(mode_Iu, get_mode_size_bits(dst_mode_h) - 1), dst_mode_h);
1434 env->entries[idx]->high_word = new_Const(dst_mode_h, get_mode_null(dst_mode_h));
1438 ir_node *irn, *call;
1439 ir_mode *omode = env->params->high_signed;
1440 ir_type *mtp = get_conv_type(imode, omode, env);
1442 irn = get_intrinsic_address(mtp, get_irn_op(node), imode, omode, block, env);
1443 call = new_rd_Call(dbg, irg, block, get_irg_no_mem(irg), irn, 1, &op, mtp);
1444 set_irn_pinned(call, get_irn_pinned(node));
1445 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
1447 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, dst_mode_l, 0);
1448 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, dst_mode_h, 1);
1450 } /* lower_Conv_to_Ls */
1453 * Translate a Conv to higher_unsigned
1455 static void lower_Conv_to_Lu(ir_node *node, lower_env_t *env) {
1456 ir_node *op = get_Conv_op(node);
1457 ir_mode *imode = get_irn_mode(op);
1458 ir_mode *dst_mode = env->params->low_unsigned;
1459 int idx = get_irn_idx(node);
1460 ir_graph *irg = current_ir_graph;
1461 ir_node *block = get_nodes_block(node);
1462 dbg_info *dbg = get_irn_dbg_info(node);
1464 assert(idx < env->n_entries);
1466 if (mode_is_int(imode) || mode_is_reference(imode)) {
1467 if (imode == env->params->high_signed) {
1468 /* a Conv from Ls to Lu */
1469 int op_idx = get_irn_idx(op);
1471 if (! env->entries[op_idx]->low_word) {
1472 /* not ready yet, wait */
1473 pdeq_putr(env->waitq, node);
1476 env->entries[idx]->low_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->low_word, dst_mode);
1477 env->entries[idx]->high_word = new_rd_Conv(dbg, irg, block, env->entries[op_idx]->high_word, dst_mode);
1479 /* simple case: create a high word */
1480 if (imode != dst_mode)
1481 op = new_rd_Conv(dbg, irg, block, op, dst_mode);
1483 env->entries[idx]->low_word = op;
1485 if (mode_is_signed(imode)) {
1486 env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
1487 new_Const_long(mode_Iu, get_mode_size_bits(dst_mode) - 1), dst_mode);
1489 env->entries[idx]->high_word = new_Const(dst_mode, get_mode_null(dst_mode));
1493 ir_node *irn, *call;
1494 ir_mode *omode = env->params->high_unsigned;
1495 ir_type *mtp = get_conv_type(imode, omode, env);
1497 /* do an intrinsic call */
1498 irn = get_intrinsic_address(mtp, get_irn_op(node), imode, omode, block, env);
1499 call = new_rd_Call(dbg, irg, block, get_irg_no_mem(irg), irn, 1, &op, mtp);
1500 set_irn_pinned(call, get_irn_pinned(node));
1501 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
1503 env->entries[idx]->low_word = new_r_Proj(irg, block, irn, dst_mode, 0);
1504 env->entries[idx]->high_word = new_r_Proj(irg, block, irn, dst_mode, 1);
1506 } /* lower_Conv_to_Lu */
1509 * Translate a Conv from higher_signed
1511 static void lower_Conv_from_Ls(ir_node *node, lower_env_t *env) {
1512 ir_node *op = get_Conv_op(node);
1513 ir_mode *omode = get_irn_mode(node);
1514 ir_node *block = get_nodes_block(node);
1515 dbg_info *dbg = get_irn_dbg_info(node);
1516 int idx = get_irn_idx(op);
1517 ir_graph *irg = current_ir_graph;
1519 assert(idx < env->n_entries);
1521 if (! env->entries[idx]->low_word) {
1522 /* not ready yet, wait */
1523 pdeq_putr(env->waitq, node);
1527 if (mode_is_int(omode) || mode_is_reference(omode)) {
1528 op = env->entries[idx]->low_word;
1530 /* simple case: create a high word */
1531 if (omode != env->params->low_signed)
1532 op = new_rd_Conv(dbg, irg, block, op, omode);
1534 set_Conv_op(node, op);
1536 ir_node *irn, *call, *in[2];
1537 ir_mode *imode = env->params->high_signed;
1538 ir_type *mtp = get_conv_type(imode, omode, env);
1540 irn = get_intrinsic_address(mtp, get_irn_op(node), imode, omode, block, env);
1541 in[0] = env->entries[idx]->low_word;
1542 in[1] = env->entries[idx]->high_word;
1544 call = new_rd_Call(dbg, irg, block, get_irg_no_mem(irg), irn, 2, in, mtp);
1545 set_irn_pinned(call, get_irn_pinned(node));
1546 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
1548 exchange(node, new_r_Proj(irg, block, irn, omode, 0));
1550 } /* lower_Conv_from_Ls */
1553 * Translate a Conv from higher_unsigned
1555 static void lower_Conv_from_Lu(ir_node *node, lower_env_t *env) {
1556 ir_node *op = get_Conv_op(node);
1557 ir_mode *omode = get_irn_mode(node);
1558 ir_node *block = get_nodes_block(node);
1559 dbg_info *dbg = get_irn_dbg_info(node);
1560 int idx = get_irn_idx(op);
1561 ir_graph *irg = current_ir_graph;
1563 assert(idx < env->n_entries);
1565 if (! env->entries[idx]->low_word) {
1566 /* not ready yet, wait */
1567 pdeq_putr(env->waitq, node);
1571 if (mode_is_int(omode) || mode_is_reference(omode)) {
1572 op = env->entries[idx]->low_word;
1574 /* simple case: create a high word */
1575 if (omode != env->params->low_unsigned)
1576 op = new_rd_Conv(dbg, irg, block, op, omode);
1578 set_Conv_op(node, op);
1580 ir_node *irn, *call, *in[2];
1581 ir_mode *imode = env->params->high_unsigned;
1582 ir_type *mtp = get_conv_type(imode, omode, env);
1584 irn = get_intrinsic_address(mtp, get_irn_op(node), imode, omode, block, env);
1585 in[0] = env->entries[idx]->low_word;
1586 in[1] = env->entries[idx]->high_word;
1588 call = new_rd_Call(dbg, irg, block, get_irg_no_mem(irg), irn, 2, in, mtp);
1589 set_irn_pinned(call, get_irn_pinned(node));
1590 irn = new_r_Proj(irg, block, call, mode_T, pn_Call_T_result);
1592 exchange(node, new_r_Proj(irg, block, irn, omode, 0));
1594 } /* lower_Conv_from_Lu */
1599 static void lower_Conv(ir_node *node, ir_mode *mode, lower_env_t *env) {
1600 mode = get_irn_mode(node);
1602 if (mode == env->params->high_signed) {
1603 lower_Conv_to_Ls(node, env);
1604 } else if (mode == env->params->high_unsigned) {
1605 lower_Conv_to_Lu(node, env);
1607 ir_mode *mode = get_irn_mode(get_Conv_op(node));
1609 if (mode == env->params->high_signed) {
1610 lower_Conv_from_Ls(node, env);
1611 } else if (mode == env->params->high_unsigned) {
1612 lower_Conv_from_Lu(node, env);
1618 * Lower the method type.
1620 static ir_type *lower_mtp(ir_type *mtp, lower_env_t *env) {
1625 if (is_lowered_type(mtp))
1628 entry = pmap_find(lowered_type, mtp);
1630 int i, n, r, n_param, n_res;
1632 /* count new number of params */
1633 n_param = n = get_method_n_params(mtp);
1634 for (i = n_param - 1; i >= 0; --i) {
1635 ir_type *tp = get_method_param_type(mtp, i);
1637 if (is_Primitive_type(tp)) {
1638 ir_mode *mode = get_type_mode(tp);
1640 if (mode == env->params->high_signed ||
1641 mode == env->params->high_unsigned)
1646 /* count new number of results */
1647 n_res = r = get_method_n_ress(mtp);
1648 for (i = n_res - 1; i >= 0; --i) {
1649 ir_type *tp = get_method_res_type(mtp, i);
1651 if (is_Primitive_type(tp)) {
1652 ir_mode *mode = get_type_mode(tp);
1654 if (mode == env->params->high_signed ||
1655 mode == env->params->high_unsigned)
1660 id = mangle_u(new_id_from_chars("L", 1), get_type_ident(mtp));
1661 res = new_type_method(id, n_param, n_res);
1663 /* set param types and result types */
1664 for (i = n_param = 0; i < n; ++i) {
1665 ir_type *tp = get_method_param_type(mtp, i);
1667 if (is_Primitive_type(tp)) {
1668 ir_mode *mode = get_type_mode(tp);
1670 if (mode == env->params->high_signed) {
1671 set_method_param_type(res, n_param++, tp_u);
1672 set_method_param_type(res, n_param++, tp_s);
1673 } else if (mode == env->params->high_unsigned) {
1674 set_method_param_type(res, n_param++, tp_u);
1675 set_method_param_type(res, n_param++, tp_u);
1677 set_method_param_type(res, n_param++, tp);
1680 set_method_param_type(res, n_param++, tp);
1683 for (i = n_res = 0; i < r; ++i) {
1684 ir_type *tp = get_method_res_type(mtp, i);
1686 if (is_Primitive_type(tp)) {
1687 ir_mode *mode = get_type_mode(tp);
1689 if (mode == env->params->high_signed) {
1690 set_method_res_type(res, n_res++, tp_u);
1691 set_method_res_type(res, n_res++, tp_s);
1692 } else if (mode == env->params->high_unsigned) {
1693 set_method_res_type(res, n_res++, tp_u);
1694 set_method_res_type(res, n_res++, tp_u);
1696 set_method_res_type(res, n_res++, tp);
1699 set_method_res_type(res, n_res++, tp);
1702 set_lowered_type(mtp, res);
1703 pmap_insert(lowered_type, mtp, res);
1711 * Translate a Return.
1713 static void lower_Return(ir_node *node, ir_mode *mode, lower_env_t *env) {
1714 ir_graph *irg = current_ir_graph;
1715 ir_entity *ent = get_irg_entity(irg);
1716 ir_type *mtp = get_entity_type(ent);
1722 /* check if this return must be lowered */
1723 for (i = 0, n = get_Return_n_ress(node); i < n; ++i) {
1724 ir_node *pred = get_Return_res(node, i);
1725 ir_mode *mode = get_irn_op_mode(pred);
1727 if (mode == env->params->high_signed ||
1728 mode == env->params->high_unsigned) {
1729 idx = get_irn_idx(pred);
1730 if (! env->entries[idx]->low_word) {
1731 /* not ready yet, wait */
1732 pdeq_putr(env->waitq, node);
1741 ent = get_irg_entity(irg);
1742 mtp = get_entity_type(ent);
1744 mtp = lower_mtp(mtp, env);
1745 set_entity_type(ent, mtp);
1747 /* create a new in array */
1748 NEW_ARR_A(ir_node *, in, get_method_n_ress(mtp) + 1);
1749 in[0] = get_Return_mem(node);
1751 for (j = i = 0, n = get_Return_n_ress(node); i < n; ++i) {
1752 ir_node *pred = get_Return_res(node, i);
1754 idx = get_irn_idx(pred);
1755 assert(idx < env->n_entries);
1757 if (env->entries[idx]) {
1758 in[++j] = env->entries[idx]->low_word;
1759 in[++j] = env->entries[idx]->high_word;
1765 set_irn_in(node, j+1, in);
1766 } /* lower_Return */
1769 * Translate the parameters.
1771 static void lower_Start(ir_node *node, ir_mode *mode, lower_env_t *env) {
1772 ir_graph *irg = current_ir_graph;
1773 ir_entity *ent = get_irg_entity(irg);
1774 ir_type *tp = get_entity_type(ent);
1777 int i, j, n_params, rem;
1778 ir_node *proj, *args;
1781 if (is_lowered_type(tp)) {
1782 mtp = get_associated_type(tp);
1786 assert(! is_lowered_type(mtp));
1788 n_params = get_method_n_params(mtp);
1792 NEW_ARR_A(long, new_projs, n_params);
1794 /* first check if we have parameters that must be fixed */
1795 for (i = j = 0; i < n_params; ++i, ++j) {
1796 ir_type *tp = get_method_param_type(mtp, i);
1799 if (is_Primitive_type(tp)) {
1800 ir_mode *mode = get_type_mode(tp);
1802 if (mode == env->params->high_signed ||
1803 mode == env->params->high_unsigned)
1810 mtp = lower_mtp(mtp, env);
1811 set_entity_type(ent, mtp);
1813 /* switch off optimization for new Proj nodes or they might be CSE'ed
1814 with not patched one's */
1815 rem = get_optimize();
1818 /* ok, fix all Proj's and create new ones */
1819 args = get_irg_args(irg);
1820 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
1821 ir_node *pred = get_Proj_pred(proj);
1827 /* do not visit this node again */
1828 mark_irn_visited(proj);
1833 proj_nr = get_Proj_proj(proj);
1834 set_Proj_proj(proj, new_projs[proj_nr]);
1836 idx = get_irn_idx(proj);
1837 if (env->entries[idx]) {
1838 ir_mode *low_mode = env->params->low_unsigned;
1840 mode = get_irn_mode(proj);
1842 if (mode == env->params->high_signed) {
1843 mode = env->params->low_signed;
1845 mode = env->params->low_unsigned;
1848 dbg = get_irn_dbg_info(proj);
1849 env->entries[idx]->low_word =
1850 new_rd_Proj(dbg, irg, get_nodes_block(proj), args, low_mode, new_projs[proj_nr]);
1851 env->entries[idx]->high_word =
1852 new_rd_Proj(dbg, irg, get_nodes_block(proj), args, mode, new_projs[proj_nr] + 1);
1861 static void lower_Call(ir_node *node, ir_mode *mode, lower_env_t *env) {
1862 ir_graph *irg = current_ir_graph;
1863 ir_type *tp = get_Call_type(node);
1865 ir_node **in, *proj, *results;
1866 int n_params, n_res, need_lower = 0;
1868 long *res_numbers = NULL;
1871 if (is_lowered_type(tp)) {
1872 call_tp = get_associated_type(tp);
1877 assert(! is_lowered_type(call_tp));
1879 n_params = get_method_n_params(call_tp);
1880 for (i = 0; i < n_params; ++i) {
1881 ir_type *tp = get_method_param_type(call_tp, i);
1883 if (is_Primitive_type(tp)) {
1884 ir_mode *mode = get_type_mode(tp);
1886 if (mode == env->params->high_signed ||
1887 mode == env->params->high_unsigned) {
1893 n_res = get_method_n_ress(call_tp);
1895 NEW_ARR_A(long, res_numbers, n_res);
1897 for (i = j = 0; i < n_res; ++i, ++j) {
1898 ir_type *tp = get_method_res_type(call_tp, i);
1901 if (is_Primitive_type(tp)) {
1902 ir_mode *mode = get_type_mode(tp);
1904 if (mode == env->params->high_signed ||
1905 mode == env->params->high_unsigned) {
1916 /* let's lower it */
1917 call_tp = lower_mtp(call_tp, env);
1918 set_Call_type(node, call_tp);
1920 NEW_ARR_A(ir_node *, in, get_method_n_params(call_tp) + 2);
1922 in[0] = get_Call_mem(node);
1923 in[1] = get_Call_ptr(node);
1925 for (j = 2, i = 0; i < n_params; ++i) {
1926 ir_node *pred = get_Call_param(node, i);
1927 int idx = get_irn_idx(pred);
1929 if (env->entries[idx]) {
1930 if (! env->entries[idx]->low_word) {
1931 /* not ready yet, wait */
1932 pdeq_putr(env->waitq, node);
1935 in[j++] = env->entries[idx]->low_word;
1936 in[j++] = env->entries[idx]->high_word;
1942 set_irn_in(node, j, in);
1944 /* fix the results */
1946 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
1947 long proj_nr = get_Proj_proj(proj);
1949 if (proj_nr == pn_Call_T_result && get_Proj_pred(proj) == node) {
1950 /* found the result proj */
1956 if (results) { /* there are results */
1957 int rem = get_optimize();
1959 /* switch off optimization for new Proj nodes or they might be CSE'ed
1960 with not patched one's */
1962 for (i = j = 0, proj = get_irn_link(results); proj; proj = get_irn_link(proj), ++i, ++j) {
1963 if (get_Proj_pred(proj) == results) {
1964 long proj_nr = get_Proj_proj(proj);
1967 /* found a result */
1968 set_Proj_proj(proj, res_numbers[proj_nr]);
1969 idx = get_irn_idx(proj);
1970 if (env->entries[idx]) {
1971 ir_mode *mode = get_irn_mode(proj);
1972 ir_mode *low_mode = env->params->low_unsigned;
1975 if (mode == env->params->high_signed) {
1976 mode = env->params->low_signed;
1978 mode = env->params->low_unsigned;
1981 dbg = get_irn_dbg_info(proj);
1982 env->entries[idx]->low_word =
1983 new_rd_Proj(dbg, irg, get_nodes_block(proj), results, low_mode, res_numbers[proj_nr]);
1984 env->entries[idx]->high_word =
1985 new_rd_Proj(dbg, irg, get_nodes_block(proj), results, mode, res_numbers[proj_nr] + 1);
1987 mark_irn_visited(proj);
1995 * Translate an Unknown into two.
1997 static void lower_Unknown(ir_node *node, ir_mode *mode, lower_env_t *env) {
1998 int idx = get_irn_idx(node);
1999 ir_graph *irg = current_ir_graph;
2001 env->entries[idx]->low_word =
2002 env->entries[idx]->high_word = new_r_Unknown(irg, mode);
2003 } /* lower_Unknown */
2008 * First step: just create two templates
2010 static void lower_Phi(ir_node *phi, ir_mode *mode, lower_env_t *env) {
2011 ir_mode *mode_l = env->params->low_unsigned;
2012 ir_graph *irg = current_ir_graph;
2016 ir_node **inl, **inh;
2018 int idx, i, arity = get_Phi_n_preds(phi);
2021 idx = get_irn_idx(phi);
2022 if (env->entries[idx]->low_word) {
2023 /* Phi nodes already build, check for inputs */
2024 ir_node *phil = env->entries[idx]->low_word;
2025 ir_node *phih = env->entries[idx]->high_word;
2027 for (i = 0; i < arity; ++i) {
2028 ir_node *pred = get_Phi_pred(phi, i);
2029 int idx = get_irn_idx(pred);
2031 if (env->entries[idx]->low_word) {
2032 set_Phi_pred(phil, i, env->entries[idx]->low_word);
2033 set_Phi_pred(phih, i, env->entries[idx]->high_word);
2035 /* still not ready */
2036 pdeq_putr(env->waitq, phi);
2042 /* first create a new in array */
2043 NEW_ARR_A(ir_node *, inl, arity);
2044 NEW_ARR_A(ir_node *, inh, arity);
2045 unk_l = new_r_Unknown(irg, mode_l);
2046 unk_h = new_r_Unknown(irg, mode);
2048 for (i = 0; i < arity; ++i) {
2049 ir_node *pred = get_Phi_pred(phi, i);
2050 int idx = get_irn_idx(pred);
2052 if (env->entries[idx]->low_word) {
2053 inl[i] = env->entries[idx]->low_word;
2054 inh[i] = env->entries[idx]->high_word;
2062 dbg = get_irn_dbg_info(phi);
2063 block = get_nodes_block(phi);
2065 idx = get_irn_idx(phi);
2066 assert(idx < env->n_entries);
2067 env->entries[idx]->low_word = new_rd_Phi(dbg, irg, block, arity, inl, mode_l);
2068 env->entries[idx]->high_word = new_rd_Phi(dbg, irg, block, arity, inh, mode);
2071 /* not yet finished */
2072 pdeq_putr(env->waitq, phi);
2079 static void lower_Psi(ir_node *psi, ir_mode *mode, lower_env_t *env) {
2080 ir_graph *irg = current_ir_graph;
2081 ir_node *block, *val;
2082 ir_node **valsl, **valsh, **conds;
2084 int idx, i, n_conds = get_Psi_n_conds(psi);
2086 /* first create a new in array */
2087 NEW_ARR_A(ir_node *, valsl, n_conds + 1);
2088 NEW_ARR_A(ir_node *, valsh, n_conds + 1);
2090 for (i = 0; i < n_conds; ++i) {
2091 val = get_Psi_val(psi, i);
2092 idx = get_irn_idx(val);
2093 if (env->entries[idx]->low_word) {
2094 /* Values already build */
2095 valsl[i] = env->entries[idx]->low_word;
2096 valsh[i] = env->entries[idx]->high_word;
2098 /* still not ready */
2099 pdeq_putr(env->waitq, psi);
2103 val = get_Psi_default(psi);
2104 idx = get_irn_idx(val);
2105 if (env->entries[idx]->low_word) {
2106 /* Values already build */
2107 valsl[i] = env->entries[idx]->low_word;
2108 valsh[i] = env->entries[idx]->high_word;
2110 /* still not ready */
2111 pdeq_putr(env->waitq, psi);
2116 NEW_ARR_A(ir_node *, conds, n_conds);
2117 for (i = 0; i < n_conds; ++i) {
2118 conds[i] = get_Psi_cond(psi, i);
2121 dbg = get_irn_dbg_info(psi);
2122 block = get_nodes_block(psi);
2124 idx = get_irn_idx(psi);
2125 assert(idx < env->n_entries);
2126 env->entries[idx]->low_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsl, mode);
2127 env->entries[idx]->high_word = new_rd_Psi(dbg, irg, block, n_conds, conds, valsh, mode);
2131 * check for opcodes that must always be lowered.
2133 static int always_lower(ir_opcode code) {
2145 } /* always_lower */
2148 * lower boolean Proj(Cmp)
2150 static ir_node *lower_boolean_Proj_Cmp(ir_node *proj, ir_node *cmp, lower_env_t *env) {
2152 ir_node *l, *r, *low, *high, *t, *res;
2155 ir_graph *irg = current_ir_graph;
2158 l = get_Cmp_left(cmp);
2159 lidx = get_irn_idx(l);
2160 if (! env->entries[lidx]->low_word) {
2161 /* still not ready */
2165 r = get_Cmp_right(cmp);
2166 ridx = get_irn_idx(r);
2167 if (! env->entries[ridx]->low_word) {
2168 /* still not ready */
2172 pnc = get_Proj_proj(proj);
2173 blk = get_nodes_block(cmp);
2174 db = get_irn_dbg_info(cmp);
2175 low = new_rd_Cmp(db, irg, blk, env->entries[lidx]->low_word, env->entries[ridx]->low_word);
2176 high = new_rd_Cmp(db, irg, blk, env->entries[lidx]->high_word, env->entries[ridx]->high_word);
2178 if (pnc == pn_Cmp_Eq) {
2179 /* simple case:a == b <==> a_h == b_h && a_l == b_l */
2180 res = new_rd_And(db, irg, blk,
2181 new_r_Proj(irg, blk, low, mode_b, pnc),
2182 new_r_Proj(irg, blk, high, mode_b, pnc),
2184 } else if (pnc == pn_Cmp_Lg) {
2185 /* simple case:a != b <==> a_h != b_h || a_l != b_l */
2186 res = new_rd_Or(db, irg, blk,
2187 new_r_Proj(irg, blk, low, mode_b, pnc),
2188 new_r_Proj(irg, blk, high, mode_b, pnc),
2191 /* a rel b <==> a_h REL b_h || (a_h == b_h && a_l rel b_l) */
2192 t = new_rd_And(db, irg, blk,
2193 new_r_Proj(irg, blk, low, mode_b, pnc),
2194 new_r_Proj(irg, blk, high, mode_b, pn_Cmp_Eq),
2196 res = new_rd_Or(db, irg, blk,
2197 new_r_Proj(irg, blk, high, mode_b, pnc & ~pn_Cmp_Eq),
2202 } /* lower_boolean_Proj_Cmp */
2205 * The type of a lower function.
2207 * @param node the node to be lowered
2208 * @param mode the low mode for the destination node
2209 * @param env the lower environment
2211 typedef void (*lower_func)(ir_node *node, ir_mode *mode, lower_env_t *env);
2216 static void lower_ops(ir_node *node, void *env)
2218 lower_env_t *lenv = env;
2219 node_entry_t *entry;
2220 int idx = get_irn_idx(node);
2221 ir_mode *mode = get_irn_mode(node);
2223 if (mode == mode_b || get_irn_op(node) == op_Psi) {
2226 for (i = get_irn_arity(node) - 1; i >= 0; --i) {
2227 ir_node *proj = get_irn_n(node, i);
2229 if (is_Proj(proj)) {
2230 ir_node *cmp = get_Proj_pred(proj);
2233 ir_node *arg = get_Cmp_left(cmp);
2235 mode = get_irn_mode(arg);
2236 if (mode == lenv->params->high_signed ||
2237 mode == lenv->params->high_unsigned) {
2238 ir_node *res = lower_boolean_Proj_Cmp(proj, cmp, lenv);
2241 /* could not lower because predecessors not ready */
2242 waitq_put(lenv->waitq, node);
2245 set_irn_n(node, i, res);
2252 entry = idx < lenv->n_entries ? lenv->entries[idx] : NULL;
2253 if (entry || always_lower(get_irn_opcode(node))) {
2254 ir_op *op = get_irn_op(node);
2255 lower_func func = (lower_func)op->ops.generic;
2258 mode = get_irn_op_mode(node);
2260 if (mode == lenv->params->high_signed)
2261 mode = lenv->params->low_signed;
2263 mode = lenv->params->low_unsigned;
2265 DB((dbg, LEVEL_1, " %+F\n", node));
2266 func(node, mode, lenv);
2271 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
2274 * Compare two op_mode_entry_t's.
2276 static int cmp_op_mode(const void *elt, const void *key, size_t size) {
2277 const op_mode_entry_t *e1 = elt;
2278 const op_mode_entry_t *e2 = key;
2281 return (e1->op - e2->op) | (e1->imode - e2->imode) | (e1->omode - e2->omode);
2285 * Compare two conv_tp_entry_t's.
2287 static int cmp_conv_tp(const void *elt, const void *key, size_t size) {
2288 const conv_tp_entry_t *e1 = elt;
2289 const conv_tp_entry_t *e2 = key;
2292 return (e1->imode - e2->imode) | (e1->omode - e2->omode);
2293 } /* static int cmp_conv_tp */
2298 void lower_dw_ops(const lwrdw_param_t *param)
2307 if (! param->enable)
2310 FIRM_DBG_REGISTER(dbg, "firm.lower.dw");
2312 assert(2 * get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->high_signed));
2313 assert(2 * get_mode_size_bits(param->low_unsigned) == get_mode_size_bits(param->high_unsigned));
2314 assert(get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->low_unsigned));
2316 /* create the necessary maps */
2318 prim_types = pmap_create();
2319 if (! intrinsic_fkt)
2320 intrinsic_fkt = new_set(cmp_op_mode, iro_MaxOpcode);
2322 conv_types = new_set(cmp_conv_tp, 16);
2324 lowered_type = pmap_create();
2326 /* create a primitive unsigned and signed type */
2328 tp_u = get_primitive_type(param->low_unsigned);
2330 tp_s = get_primitive_type(param->low_signed);
2332 /* create method types for the created binop calls */
2334 binop_tp_u = new_type_method(IDENT("binop_u_intrinsic"), 4, 2);
2335 set_method_param_type(binop_tp_u, 0, tp_u);
2336 set_method_param_type(binop_tp_u, 1, tp_u);
2337 set_method_param_type(binop_tp_u, 2, tp_u);
2338 set_method_param_type(binop_tp_u, 3, tp_u);
2339 set_method_res_type(binop_tp_u, 0, tp_u);
2340 set_method_res_type(binop_tp_u, 1, tp_u);
2343 binop_tp_s = new_type_method(IDENT("binop_s_intrinsic"), 4, 2);
2344 set_method_param_type(binop_tp_s, 0, tp_u);
2345 set_method_param_type(binop_tp_s, 1, tp_s);
2346 set_method_param_type(binop_tp_s, 2, tp_u);
2347 set_method_param_type(binop_tp_s, 3, tp_s);
2348 set_method_res_type(binop_tp_s, 0, tp_u);
2349 set_method_res_type(binop_tp_s, 1, tp_s);
2351 if (! shiftop_tp_u) {
2352 shiftop_tp_u = new_type_method(IDENT("shiftop_u_intrinsic"), 3, 2);
2353 set_method_param_type(shiftop_tp_u, 0, tp_u);
2354 set_method_param_type(shiftop_tp_u, 1, tp_u);
2355 set_method_param_type(shiftop_tp_u, 2, tp_u);
2356 set_method_res_type(shiftop_tp_u, 0, tp_u);
2357 set_method_res_type(shiftop_tp_u, 1, tp_u);
2359 if (! shiftop_tp_s) {
2360 shiftop_tp_s = new_type_method(IDENT("shiftop_s_intrinsic"), 3, 2);
2361 set_method_param_type(shiftop_tp_s, 0, tp_u);
2362 set_method_param_type(shiftop_tp_s, 1, tp_s);
2363 /* beware: shift count is always mode_Iu */
2364 set_method_param_type(shiftop_tp_s, 2, tp_u);
2365 set_method_res_type(shiftop_tp_s, 0, tp_u);
2366 set_method_res_type(shiftop_tp_s, 1, tp_s);
2369 unop_tp_u = new_type_method(IDENT("unop_u_intrinsic"), 2, 2);
2370 set_method_param_type(unop_tp_u, 0, tp_u);
2371 set_method_param_type(unop_tp_u, 1, tp_u);
2372 set_method_res_type(unop_tp_u, 0, tp_u);
2373 set_method_res_type(unop_tp_u, 1, tp_u);
2376 unop_tp_s = new_type_method(IDENT("unop_s_intrinsic"), 2, 2);
2377 set_method_param_type(unop_tp_s, 0, tp_u);
2378 set_method_param_type(unop_tp_s, 1, tp_s);
2379 set_method_res_type(unop_tp_s, 0, tp_u);
2380 set_method_res_type(unop_tp_s, 1, tp_s);
2383 lenv.tv_mode_bytes = new_tarval_from_long(get_mode_size_bytes(param->low_unsigned), mode_Iu);
2384 lenv.tv_mode_bits = new_tarval_from_long(get_mode_size_bits(param->low_unsigned), mode_Iu);
2385 lenv.waitq = new_pdeq();
2386 lenv.params = param;
2388 /* first clear the generic function pointer for all ops */
2389 clear_irp_opcodes_generic_func();
2391 #define LOWER2(op, fkt) op_##op->ops.generic = (op_func)fkt
2392 #define LOWER(op) LOWER2(op, lower_##op)
2393 #define LOWER_BIN(op) LOWER2(op, lower_Binop)
2394 #define LOWER_UN(op) LOWER2(op, lower_Unop)
2396 /* the table of all operations that must be lowered follows */
2432 /* transform all graphs */
2433 rem = current_ir_graph;
2434 for (i = get_irp_n_irgs() - 1; i >= 0; --i) {
2435 ir_graph *irg = get_irp_irg(i);
2438 obstack_init(&lenv.obst);
2440 n_idx = get_irg_last_idx(irg);
2441 lenv.n_entries = n_idx;
2442 lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0]));
2443 memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0]));
2445 /* first step: link all nodes and allocate data */
2447 lenv.proj_2_block = pmap_create();
2448 irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv);
2450 if (lenv.flags & MUST_BE_LOWERED) {
2451 DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg));
2453 /* must do some work */
2454 irg_walk_graph(irg, NULL, lower_ops, &lenv);
2456 /* last step: all waiting nodes */
2457 DB((dbg, LEVEL_1, "finishing waiting nodes:\n"));
2458 current_ir_graph = irg;
2459 while (! pdeq_empty(lenv.waitq)) {
2460 ir_node *node = pdeq_getl(lenv.waitq);
2462 lower_ops(node, &lenv);
2465 /* outs are invalid, we changed the graph */
2466 set_irg_outs_inconsistent(irg);
2468 if (lenv.flags & CF_CHANGED) {
2469 /* control flow changed, dominance info is invalid */
2470 set_irg_doms_inconsistent(irg);
2471 set_irg_extblk_inconsistent(irg);
2472 set_irg_loopinfo_inconsistent(irg);
2475 pmap_destroy(lenv.proj_2_block);
2477 obstack_free(&lenv.obst, NULL);
2479 del_pdeq(lenv.waitq);
2480 current_ir_graph = rem;
2481 } /* lower_dw_ops */
2483 /* Default implementation. */
2484 ir_entity *def_create_intrinsic_fkt(ir_type *method, const ir_op *op,
2485 const ir_mode *imode, const ir_mode *omode,
2493 if (imode == omode) {
2494 snprintf(buf, sizeof(buf), "__l%s%s", get_op_name(op), get_mode_name(imode));
2496 snprintf(buf, sizeof(buf), "__l%s%s%s", get_op_name(op),
2497 get_mode_name(imode), get_mode_name(omode));
2499 id = new_id_from_str(buf);
2501 ent = new_entity(get_glob_type(), id, method);
2502 set_entity_ld_ident(ent, get_entity_ident(ent));
2503 set_entity_visibility(ent, visibility_external_allocated);
2505 } /* def_create_intrinsic_fkt */