5 * @brief Lower Double word operations, ie Mode L -> I.
29 #include "irgraph_t.h"
34 #include "dbginfo_t.h"
35 #include "iropt_dbg.h"
49 /** A map from ir_op to Intrinsic functions entities. */
50 static set *intrinsic_fkt;
52 /** A map from a method type to its lowered type. */
53 static pmap *lowered_type;
55 /** The types for the binop and unop intrinsics. */
56 static ir_type *binop_tp_u, *binop_tp_s, *unop_tp_u, *unop_tp_s, *tp_s, *tp_u;
58 /** the debug handle */
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 * An entry in the (op, mode) -> entity map.
64 typedef struct _op_mode_entry {
65 const ir_op *op; /**< the op */
66 const ir_mode *mode; /**< the mode */
67 entity *ent; /**< the associated entity of this (op, mode) pair */
71 * Every double word node will be replaced,
72 * we need some store to hold the replacement:
74 typedef struct _node_entry_t {
75 ir_node *low_word; /**< the low word */
76 ir_node *high_word; /**< the high word */
80 MUST_BE_LOWERED = 1, /**< graph must be lowered */
81 CF_CHANGED = 2, /**< control flow was changed */
85 * The lower environment.
87 typedef struct _lower_env_t {
88 node_entry_t **entries; /**< entries per node */
89 struct obstack obst; /**< an obstack holding the temporary data */
90 tarval *tv_mode_bytes; /**< a tarval containing the number of bits in the lowered modes */
91 pdeq *waitq; /**< a wait queue of all nodes that must be handled later */
92 pmap *proj_2_block; /**< a map from ProjX to its destination blocks */
93 const lwrdw_param_t *params; /**< transformation parameter */
94 unsigned flags; /**< some flags */
95 int n_entries; /**< number of entries */
99 * Add an additional control flow input to a block.
100 * Patch all Phi nodes. The new Phi inputs are copied from
101 * old input number nr.
103 static void add_block_cf_input_nr(ir_node *block, int nr, ir_node *cf)
105 int i, arity = get_irn_arity(block);
110 NEW_ARR_A(ir_node *, in, arity + 1);
111 for (i = 0; i < arity; ++i)
112 in[i] = get_irn_n(block, i);
115 set_irn_in(block, i + 1, in);
117 for (phi = get_irn_link(block); phi; phi = get_irn_link(phi)) {
118 for (i = 0; i < arity; ++i)
119 in[i] = get_irn_n(phi, i);
121 set_irn_in(phi, i + 1, in);
126 * Add an additional control flow input to a block.
127 * Patch all Phi nodes. The new Phi inputs are copied from
128 * old input from cf tmpl.
130 static void add_block_cf_input(ir_node *block, ir_node *tmpl, ir_node *cf)
132 int i, arity = get_irn_arity(block);
135 for (i = 0; i < arity; ++i) {
136 if (get_irn_n(block, i) == tmpl) {
142 add_block_cf_input_nr(block, nr, cf);
146 * Return the "operational" mode of a Firm node.
148 static ir_mode *get_irn_op_mode(ir_node *node)
150 switch (get_irn_opcode(node)) {
152 return get_Load_mode(node);
155 return get_irn_mode(get_Store_value(node));
158 return get_irn_mode(get_DivMod_left(node));
161 return get_irn_mode(get_Div_left(node));
164 return get_irn_mode(get_Mod_left(node));
167 return get_irn_mode(get_Cmp_left(node));
170 return get_irn_mode(node);
175 * walker, prepare the node links
177 static void prepare_links(ir_node *node, void *env)
179 lower_env_t *lenv = env;
180 ir_mode *mode = get_irn_op_mode(node);
184 if (mode == lenv->params->high_signed ||
185 mode == lenv->params->high_unsigned) {
186 /* ok, found a node that will be lowered */
187 link = obstack_alloc(&lenv->obst, sizeof(*link));
189 memset(link, 0, sizeof(*link));
191 lenv->entries[get_irn_idx(node)] = link;
192 lenv->flags |= MUST_BE_LOWERED;
194 else if (get_irn_op(node) == op_Conv) {
195 /* Conv nodes have two modes */
196 ir_node *pred = get_Conv_op(node);
197 mode = get_irn_mode(pred);
199 if (mode == lenv->params->high_signed ||
200 mode == lenv->params->high_unsigned) {
201 /* must lower this node either */
202 link = obstack_alloc(&lenv->obst, sizeof(*link));
204 memset(link, 0, sizeof(*link));
206 lenv->entries[get_irn_idx(node)] = link;
207 lenv->flags |= MUST_BE_LOWERED;
213 /* link all Proj nodes to its predecessor:
214 Note that Tuple Proj's and its Projs are linked either. */
215 ir_node *pred = get_Proj_pred(node);
217 set_irn_link(node, get_irn_link(pred));
218 set_irn_link(pred, node);
220 else if (is_Phi(node)) {
221 /* link all Phi nodes to its block */
222 ir_node *block = get_nodes_block(node);
224 set_irn_link(node, get_irn_link(block));
225 set_irn_link(block, node);
227 else if (is_Block(node)) {
228 /* fill the Proj -> Block map */
229 for (i = get_Block_n_cfgpreds(node) - 1; i >= 0; --i) {
230 ir_node *pred = get_Block_cfgpred(node, i);
233 pmap_insert(lenv->proj_2_block, pred, node);
239 * Translate a Constant: create two.
241 static void lower_Const(ir_node *node, ir_mode *mode, lower_env_t *env) {
242 tarval *tv, *tv_l, *tv_h;
244 dbg_info *dbg = get_irn_dbg_info(node);
245 ir_node *block = get_nodes_block(node);
248 tv = get_Const_tarval(node);
250 tv_l = tarval_convert_to(tv, mode);
251 low = new_rd_Const(dbg, current_ir_graph, block, mode, tv_l);
253 tv_h = tarval_convert_to(tarval_shrs(tv, env->tv_mode_bytes), mode);
254 high = new_rd_Const(dbg, current_ir_graph, block, mode, tv_h);
256 idx = get_irn_idx(node);
257 assert(idx < env->n_entries);
258 env->entries[idx]->low_word = low;
259 env->entries[idx]->high_word = high;
263 * Translate a Load: create two.
265 static void lower_Load(ir_node *node, ir_mode *mode, lower_env_t *env) {
266 ir_graph *irg = current_ir_graph;
267 ir_node *adr = get_Load_ptr(node);
268 ir_node *mem = get_Load_mem(node);
269 ir_node *low, *high, *proj;
271 ir_node *block = get_nodes_block(node);
274 if (env->params->little_endian) {
276 high = new_r_Add(irg, block, adr,
277 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
281 low = new_r_Add(irg, block, adr,
282 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
287 /* create two loads */
288 dbg = get_irn_dbg_info(node);
289 low = new_rd_Load(dbg, irg, block, mem, low, mode);
290 proj = new_r_Proj(irg, block, low, mode_M, pn_Load_M);
291 high = new_rd_Load(dbg, irg, block, proj, high, mode);
293 set_Load_volatility(low, get_Load_volatility(node));
294 set_Load_volatility(high, get_Load_volatility(node));
296 idx = get_irn_idx(node);
297 assert(idx < env->n_entries);
298 env->entries[idx]->low_word = low;
299 env->entries[idx]->high_word = high;
301 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
302 idx = get_irn_idx(proj);
304 switch (get_Proj_proj(proj)) {
305 case pn_Load_M: /* Memory result. */
306 /* put it to the second one */
307 set_Proj_pred(proj, high);
309 case pn_Load_X_except: /* Execution result if exception occurred. */
310 /* put it to the first one */
311 set_Proj_pred(proj, low);
313 case pn_Load_res: /* Result of load operation. */
314 assert(idx < env->n_entries);
315 env->entries[idx]->low_word = new_r_Proj(irg, block, low, mode, pn_Load_res);
316 env->entries[idx]->high_word = new_r_Proj(irg, block, high, mode, pn_Load_res);
319 assert(0 && "unexpected Proj number");
321 /* mark this proj: we have handled it already, otherwise we might fall into
323 mark_irn_visited(proj);
328 * Translate a Store: create two.
330 static void lower_Store(ir_node *node, ir_mode *mode, lower_env_t *env) {
332 ir_node *block, *adr, *mem;
333 ir_node *low, *high, *irn, *proj;
338 irn = get_Store_value(node);
339 entry = env->entries[get_irn_idx(irn)];
342 if (! entry->low_word) {
343 /* not ready yet, wait */
344 pdeq_putr(env->waitq, node);
348 irg = current_ir_graph;
349 adr = get_Store_ptr(node);
350 mem = get_Store_mem(node);
351 block = get_nodes_block(node);
353 if (env->params->little_endian) {
355 high = new_r_Add(irg, block, adr,
356 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
360 low = new_r_Add(irg, block, adr,
361 new_r_Const(irg, block, get_tarval_mode(env->tv_mode_bytes), env->tv_mode_bytes),
366 /* create two Stores */
367 dbg = get_irn_dbg_info(node);
368 low = new_rd_Store(dbg, irg, block, mem, low, entry->low_word);
369 proj = new_r_Proj(irg, block, low, mode_M, pn_Store_M);
370 high = new_rd_Store(dbg, irg, block, proj, high, entry->high_word);
372 set_Store_volatility(low, get_Store_volatility(node));
373 set_Store_volatility(high, get_Store_volatility(node));
375 idx = get_irn_idx(node);
376 assert(idx < env->n_entries);
377 env->entries[idx]->low_word = low;
378 env->entries[idx]->high_word = high;
380 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
381 idx = get_irn_idx(proj);
383 switch (get_Proj_proj(proj)) {
384 case pn_Store_M: /* Memory result. */
385 /* put it to the second one */
386 set_Proj_pred(proj, high);
388 case pn_Store_X_except: /* Execution result if exception occurred. */
389 /* put it to the first one */
390 set_Proj_pred(proj, low);
393 assert(0 && "unexpected Proj number");
395 /* mark this proj: we have handled it already, otherwise we might fall into
397 mark_irn_visited(proj);
402 * Return a node containing the address of the intrinsic emulation function.
404 static ir_node *get_intrinsic_address(ir_type *method, ir_op *op, ir_mode *mode, ir_node *block, lower_env_t *env) {
407 op_mode_entry_t key, *entry;
413 entry = set_insert(intrinsic_fkt, &key, sizeof(key), HASH_PTR(op) ^ HASH_PTR(mode));
415 /* create a new one */
416 ent = env->params->create_intrinsic(method, op, mode, env->params->ctx);
418 assert(ent && "Intrinsic creator must return an entity");
425 return new_r_SymConst(current_ir_graph, block, sym, symconst_addr_ent);
431 * Create an intrinsic Call.
433 static void lower_Div(ir_node *node, ir_mode *mode, lower_env_t *env) {
434 ir_node *block, *irn, *call, *proj;
441 irn = get_Div_left(node);
442 entry = env->entries[get_irn_idx(irn)];
445 if (! entry->low_word) {
446 /* not ready yet, wait */
447 pdeq_putr(env->waitq, node);
451 in[0] = entry->low_word;
452 in[1] = entry->high_word;
454 irn = get_Div_right(node);
455 entry = env->entries[get_irn_idx(irn)];
458 if (! entry->low_word) {
459 /* not ready yet, wait */
460 pdeq_putr(env->waitq, node);
464 in[2] = entry->low_word;
465 in[3] = entry->high_word;
467 dbg = get_irn_dbg_info(node);
468 block = get_nodes_block(node);
470 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
471 irn = get_intrinsic_address(mtp, get_irn_op(node), get_irn_op_mode(node), block, env);
472 call = new_rd_Call(dbg, current_ir_graph, block, get_Div_mem(node),
474 set_irn_pinned(call, get_irn_pinned(node));
475 irn = new_r_Proj(current_ir_graph, block, call, mode_T, pn_Call_T_result);
477 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
478 switch (get_Proj_proj(proj)) {
479 case pn_Div_M: /* Memory result. */
480 /* reroute to the call */
481 set_Proj_pred(proj, call);
482 set_Proj_proj(proj, pn_Call_M_except);
484 case pn_Div_X_except: /* Execution result if exception occurred. */
485 /* reroute to the call */
486 set_Proj_pred(proj, call);
487 set_Proj_proj(proj, pn_Call_X_except);
489 case pn_Div_res: /* Result of computation. */
490 idx = get_irn_idx(proj);
491 assert(idx < env->n_entries);
492 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, mode, 0);
493 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
496 assert(0 && "unexpected Proj number");
498 /* mark this proj: we have handled it already, otherwise we might fall into
500 mark_irn_visited(proj);
507 * Create an intrinsic Call.
509 static void lower_Mod(ir_node *node, ir_mode *mode, lower_env_t *env) {
510 ir_node *block, *proj, *irn, *call;
517 irn = get_Mod_left(node);
518 entry = env->entries[get_irn_idx(irn)];
521 if (! entry->low_word) {
522 /* not ready yet, wait */
523 pdeq_putr(env->waitq, node);
527 in[0] = entry->low_word;
528 in[1] = entry->high_word;
530 irn = get_Mod_right(node);
531 entry = env->entries[get_irn_idx(irn)];
534 if (! entry->low_word) {
535 /* not ready yet, wait */
536 pdeq_putr(env->waitq, node);
540 in[2] = entry->low_word;
541 in[3] = entry->high_word;
543 dbg = get_irn_dbg_info(node);
544 block = get_nodes_block(node);
546 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
547 irn = get_intrinsic_address(mtp, get_irn_op(node), get_irn_op_mode(node), block, env);
548 call = new_rd_Call(dbg, current_ir_graph, block, get_Mod_mem(node),
550 set_irn_pinned(call, get_irn_pinned(node));
551 irn = new_r_Proj(current_ir_graph, block, call, mode_T, pn_Call_T_result);
553 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
554 switch (get_Proj_proj(proj)) {
555 case pn_Mod_M: /* Memory result. */
556 /* reroute to the call */
557 set_Proj_pred(proj, call);
558 set_Proj_proj(proj, pn_Call_M_except);
560 case pn_Mod_X_except: /* Execution result if exception occurred. */
561 /* reroute to the call */
562 set_Proj_pred(proj, call);
563 set_Proj_proj(proj, pn_Call_X_except);
565 case pn_Mod_res: /* Result of computation. */
566 idx = get_irn_idx(proj);
567 assert(idx < env->n_entries);
568 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, mode, 0);
569 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
572 assert(0 && "unexpected Proj number");
574 /* mark this proj: we have handled it already, otherwise we might fall into
576 mark_irn_visited(proj);
581 * Translate a DivMod.
583 * Create two intrinsic Calls.
585 static void lower_DivMod(ir_node *node, ir_mode *mode, lower_env_t *env) {
586 ir_node *block, *proj, *irn, *mem, *callDiv, *callMod, *resDiv, *resMod;
594 /* check if both results are needed */
595 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
596 switch (get_Proj_proj(proj)) {
597 case pn_DivMod_res_div: flags |= 1; break;
598 case pn_DivMod_res_mod: flags |= 2; break;
603 irn = get_DivMod_left(node);
604 entry = env->entries[get_irn_idx(irn)];
607 if (! entry->low_word) {
608 /* not ready yet, wait */
609 pdeq_putr(env->waitq, node);
613 in[0] = entry->low_word;
614 in[1] = entry->high_word;
616 irn = get_DivMod_right(node);
617 entry = env->entries[get_irn_idx(irn)];
620 if (! entry->low_word) {
621 /* not ready yet, wait */
622 pdeq_putr(env->waitq, node);
626 in[2] = entry->low_word;
627 in[3] = entry->high_word;
629 dbg = get_irn_dbg_info(node);
630 block = get_nodes_block(node);
632 mem = get_DivMod_mem(node);
634 callDiv = callMod = NULL;
635 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
637 irn = get_intrinsic_address(mtp, op_Div, get_irn_op_mode(node), block, env);
638 callDiv = new_rd_Call(dbg, current_ir_graph, block, mem,
640 set_irn_pinned(callDiv, get_irn_pinned(node));
641 resDiv = new_r_Proj(current_ir_graph, block, callDiv, mode_T, pn_Call_T_result);
645 mem = new_r_Proj(current_ir_graph, block, callDiv, mode_M, pn_Call_M);
646 irn = get_intrinsic_address(mtp, op_Mod, get_irn_op_mode(node), block, env);
647 callMod = new_rd_Call(dbg, current_ir_graph, block, mem,
649 set_irn_pinned(callMod, get_irn_pinned(node));
650 resMod = new_r_Proj(current_ir_graph, block, callMod, mode_T, pn_Call_T_result);
653 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
654 switch (get_Proj_proj(proj)) {
655 case pn_DivMod_M: /* Memory result. */
656 /* reroute to the first call */
657 set_Proj_pred(proj, callDiv ? callDiv : (callMod ? callMod : mem));
658 set_Proj_proj(proj, pn_Call_M_except);
660 case pn_DivMod_X_except: /* Execution result if exception occurred. */
661 /* reroute to the first call */
662 set_Proj_pred(proj, callDiv ? callDiv : (callMod ? callMod : mem));
663 set_Proj_proj(proj, pn_Call_X_except);
665 case pn_DivMod_res_div: /* Result of Div. */
666 idx = get_irn_idx(proj);
667 assert(idx < env->n_entries);
668 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, resDiv, mode, 0);
669 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, resDiv, mode, 1);
671 case pn_DivMod_res_mod: /* Result of Mod. */
672 idx = get_irn_idx(proj);
673 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, resMod, mode, 0);
674 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, resMod, mode, 1);
677 assert(0 && "unexpected Proj number");
679 /* mark this proj: we have handled it already, otherwise we might fall into
681 mark_irn_visited(proj);
688 * Create an intrinsic Call.
690 static void lower_Binop(ir_node *node, ir_mode *mode, lower_env_t *env) {
691 ir_node *block, *irn;
698 irn = get_binop_left(node);
699 entry = env->entries[get_irn_idx(irn)];
702 if (! entry->low_word) {
703 /* not ready yet, wait */
704 pdeq_putr(env->waitq, node);
708 in[0] = entry->low_word;
709 in[1] = entry->high_word;
711 irn = get_binop_right(node);
712 entry = env->entries[get_irn_idx(irn)];
715 if (! entry->low_word) {
716 /* not ready yet, wait */
717 pdeq_putr(env->waitq, node);
721 in[2] = entry->low_word;
722 in[3] = entry->high_word;
724 dbg = get_irn_dbg_info(node);
725 block = get_nodes_block(node);
727 mtp = mode_is_signed(mode) ? binop_tp_s : binop_tp_u;
728 irn = get_intrinsic_address(mtp, get_irn_op(node), get_irn_mode(node), block, env);
729 irn = new_rd_Call(dbg, current_ir_graph, block, get_irg_no_mem(current_ir_graph),
731 set_irn_pinned(irn, get_irn_pinned(node));
732 irn = new_r_Proj(current_ir_graph, block, irn, mode_T, pn_Call_T_result);
734 idx = get_irn_idx(node);
735 assert(idx < env->n_entries);
736 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, mode, 0);
737 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
743 * Create an intrinsic Call.
745 static void lower_Unop(ir_node *node, ir_mode *mode, lower_env_t *env) {
746 ir_node *block, *irn;
753 irn = get_unop_op(node);
754 entry = env->entries[get_irn_idx(irn)];
757 if (! entry->low_word) {
758 /* not ready yet, wait */
759 pdeq_putr(env->waitq, node);
763 in[0] = entry->low_word;
764 in[1] = entry->high_word;
766 dbg = get_irn_dbg_info(node);
767 block = get_nodes_block(node);
769 mtp = mode_is_signed(mode) ? unop_tp_s : unop_tp_u;
770 irn = get_intrinsic_address(mtp, get_irn_op(node), get_irn_mode(node), block, env);
771 irn = new_rd_Call(dbg, current_ir_graph, block, get_irg_no_mem(current_ir_graph),
773 set_irn_pinned(irn, get_irn_pinned(node));
774 irn = new_r_Proj(current_ir_graph, block, irn, mode_T, pn_Call_T_result);
776 idx = get_irn_idx(node);
777 assert(idx < env->n_entries);
778 env->entries[idx]->low_word = new_r_Proj(current_ir_graph, block, irn, mode, 0);
779 env->entries[idx]->high_word = new_r_Proj(current_ir_graph, block, irn, mode, 1);
783 * Translate a logical Binop.
785 * Create two logical Binops.
787 static void lower_Binop_logical(ir_node *node, ir_mode *mode, lower_env_t *env,
788 ir_node *(*constr_rd)(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode) ) {
789 ir_node *block, *irn;
790 ir_node *lop_l, *lop_h, *rop_l, *rop_h;
795 irn = get_binop_left(node);
796 entry = env->entries[get_irn_idx(irn)];
799 if (! entry->low_word) {
800 /* not ready yet, wait */
801 pdeq_putr(env->waitq, node);
805 lop_l = entry->low_word;
806 lop_h = entry->high_word;
808 irn = get_binop_right(node);
809 entry = env->entries[get_irn_idx(irn)];
812 if (! entry->low_word) {
813 /* not ready yet, wait */
814 pdeq_putr(env->waitq, node);
818 rop_l = entry->low_word;
819 rop_h = entry->high_word;
821 dbg = get_irn_dbg_info(node);
822 block = get_nodes_block(node);
824 idx = get_irn_idx(node);
825 assert(idx < env->n_entries);
826 env->entries[idx]->low_word = constr_rd(dbg, current_ir_graph, block, lop_l, rop_l, mode);
827 env->entries[idx]->high_word = constr_rd(dbg, current_ir_graph, block, lop_h, rop_h, mode);
830 #define lower_logical(op) \
831 static void lower_##op(ir_node *node, ir_mode *mode, lower_env_t *env) { \
832 lower_Binop_logical(node, mode, env, new_rd_##op); \
842 * Create two logical Nots.
844 static void lower_Not(ir_node *node, ir_mode *mode, lower_env_t *env) {
845 ir_node *block, *irn;
846 ir_node *op_l, *op_h;
851 irn = get_Not_op(node);
852 entry = env->entries[get_irn_idx(irn)];
855 if (! entry->low_word) {
856 /* not ready yet, wait */
857 pdeq_putr(env->waitq, node);
861 op_l = entry->low_word;
862 op_h = entry->high_word;
864 dbg = get_irn_dbg_info(node);
865 block = get_nodes_block(node);
867 idx = get_irn_idx(node);
868 assert(idx < env->n_entries);
869 env->entries[idx]->low_word = new_rd_Not(dbg, current_ir_graph, block, op_l, mode);
870 env->entries[idx]->high_word = new_rd_Not(dbg, current_ir_graph, block, op_h, mode);
876 static void lower_Cond(ir_node *node, ir_mode *mode, lower_env_t *env) {
877 ir_node *cmp, *left, *right, *block;
878 ir_node *sel = get_Cond_selector(node);
879 ir_mode *m = get_irn_mode(sel);
883 node_entry_t *lentry, *rentry;
884 ir_node *proj, *projT = NULL, *projF = NULL;
885 ir_node *new_bl, *cmpH, *cmpL, *irn;
886 ir_node *projHF, *projHT;
892 cmp = get_Proj_pred(sel);
893 left = get_Cmp_left(cmp);
894 idx = get_irn_idx(left);
895 lentry = env->entries[idx];
901 right = get_Cmp_right(cmp);
902 idx = get_irn_idx(right);
903 rentry = env->entries[idx];
906 if (! lentry->low_word || !rentry->low_word) {
908 pdeq_putr(env->waitq, node);
912 /* all right, build the code */
913 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
914 long proj_nr = get_Proj_proj(proj);
916 if (proj_nr == pn_Cond_true) {
917 assert(projT == NULL && "more than one Proj(true)");
921 assert(proj_nr == pn_Cond_false);
922 assert(projF == NULL && "more than one Proj(false)");
925 mark_irn_visited(proj);
927 assert(projT && projF);
929 /* create a new high compare */
930 block = get_nodes_block(cmp);
931 dbg = get_irn_dbg_info(cmp);
932 irg = current_ir_graph;
934 cmpH = new_rd_Cmp(dbg, irg, block, lentry->high_word, rentry->high_word);
936 pnc = get_Proj_proj(sel);
937 if (pnc == pn_Cmp_Eq) {
938 /* simple case:a == b <==> a_h == b_h && a_l == b_l */
939 pmap_entry *entry = pmap_find(env->proj_2_block, projF);
942 dst_blk = entry->value;
944 irn = new_r_Proj(irg, block, cmpH, mode_b, pn_Cmp_Eq);
945 dbg = get_irn_dbg_info(node);
946 irn = new_rd_Cond(dbg, irg, block, irn);
948 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
949 mark_irn_visited(projHF);
950 exchange(projF, projHF);
952 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
953 mark_irn_visited(projHT);
955 new_bl = new_r_Block(irg, 1, &projHT);
957 dbg = get_irn_dbg_info(cmp);
958 cmpL = new_rd_Cmp(dbg, irg, new_bl, lentry->low_word, rentry->low_word);
959 irn = new_r_Proj(irg, new_bl, cmpL, mode_b, pn_Cmp_Eq);
960 dbg = get_irn_dbg_info(node);
961 irn = new_rd_Cond(dbg, irg, new_bl, irn);
963 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_false);
964 mark_irn_visited(proj);
965 add_block_cf_input(dst_blk, projHF, proj);
967 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_true);
968 mark_irn_visited(proj);
969 exchange(projT, proj);
971 else if (pnc == pn_Cmp_Lg) {
972 /* simple case:a != b <==> a_h != b_h || a_l != b_l */
973 pmap_entry *entry = pmap_find(env->proj_2_block, projT);
976 dst_blk = entry->value;
978 irn = new_r_Proj(irg, block, cmpH, mode_b, pn_Cmp_Lg);
979 dbg = get_irn_dbg_info(node);
980 irn = new_rd_Cond(dbg, irg, block, irn);
982 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
983 mark_irn_visited(projHT);
984 exchange(projT, projHT);
986 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
987 mark_irn_visited(projHF);
989 new_bl = new_r_Block(irg, 1, &projHF);
991 dbg = get_irn_dbg_info(cmp);
992 cmpL = new_rd_Cmp(dbg, irg, new_bl, lentry->low_word, rentry->low_word);
993 irn = new_r_Proj(irg, new_bl, cmpL, mode_b, pn_Cmp_Lg);
994 dbg = get_irn_dbg_info(node);
995 irn = new_rd_Cond(dbg, irg, new_bl, irn);
997 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_true);
998 mark_irn_visited(proj);
999 add_block_cf_input(dst_blk, projHT, proj);
1001 proj = new_r_Proj(irg, new_bl, irn, mode_X, pn_Cond_false);
1002 mark_irn_visited(proj);
1003 exchange(projF, proj);
1006 /* a rel b <==> a_h rel b_h || (a_h == b_h && a_l rel b_l) */
1007 ir_node *dstT, *dstF, *newbl_eq, *newbl_l;
1010 entry = pmap_find(env->proj_2_block, projT);
1012 dstT = entry->value;
1014 entry = pmap_find(env->proj_2_block, projF);
1016 dstF = entry->value;
1018 irn = new_r_Proj(irg, block, cmpH, mode_b, pnc);
1019 dbg = get_irn_dbg_info(node);
1020 irn = new_rd_Cond(dbg, irg, block, irn);
1022 projHT = new_r_Proj(irg, block, irn, mode_X, pn_Cond_true);
1023 mark_irn_visited(projHT);
1024 exchange(projT, projHT);
1027 projHF = new_r_Proj(irg, block, irn, mode_X, pn_Cond_false);
1028 mark_irn_visited(projHF);
1030 newbl_eq = new_r_Block(irg, 1, &projHF);
1032 irn = new_r_Proj(irg, newbl_eq, cmpH, mode_b, pn_Cmp_Eq);
1033 irn = new_rd_Cond(dbg, irg, newbl_eq, irn);
1035 proj = new_r_Proj(irg, newbl_eq, irn, mode_X, pn_Cond_false);
1036 mark_irn_visited(proj);
1037 exchange(projF, proj);
1040 proj = new_r_Proj(irg, newbl_eq, irn, mode_X, pn_Cond_true);
1041 mark_irn_visited(proj);
1043 newbl_l = new_r_Block(irg, 1, &proj);
1045 dbg = get_irn_dbg_info(cmp);
1046 cmpL = new_rd_Cmp(dbg, irg, newbl_l, lentry->low_word, rentry->low_word);
1047 irn = new_r_Proj(irg, newbl_l, cmpL, mode_b, pnc);
1048 dbg = get_irn_dbg_info(node);
1049 irn = new_rd_Cond(dbg, irg, newbl_l, irn);
1051 proj = new_r_Proj(irg, newbl_l, irn, mode_X, pn_Cond_true);
1052 mark_irn_visited(proj);
1053 add_block_cf_input(dstT, projT, proj);
1055 proj = new_r_Proj(irg, newbl_l, irn, mode_X, pn_Cond_false);
1056 mark_irn_visited(proj);
1057 add_block_cf_input(dstF, projF, proj);
1060 /* we have changed the control flow */
1061 env->flags |= CF_CHANGED;
1064 idx = get_irn_idx(sel);
1066 if (env->entries[idx]) {
1068 Bad, a jump-table with double-word index.
1069 This should not happen, but if it does we handle
1070 it like a Conv were between (in other words, ignore
1074 if (! env->entries[idx]->low_word) {
1075 /* not ready yet, wait */
1076 pdeq_putr(env->waitq, node);
1079 set_Cond_selector(node, env->entries[idx]->low_word);
1085 * Translate a Conv to higher_signed
1087 static void lower_Conv_to_Ls(ir_node *node, lower_env_t *env) {
1088 ir_node *op = get_Conv_op(node);
1089 ir_mode *mode = get_irn_mode(op);
1091 if (mode_is_int(mode) || mode_is_reference(mode)) {
1092 ir_node *block = get_nodes_block(node);
1093 dbg_info *dbg = get_irn_dbg_info(node);
1094 int idx = get_irn_idx(node);
1095 ir_graph *irg = current_ir_graph;
1096 ir_mode *dst_mode = env->params->low_signed;
1098 assert(idx < env->n_entries);
1100 /* simple case: create a high word */
1101 if (mode != dst_mode)
1102 op = new_rd_Conv(dbg, irg, block, op, dst_mode);
1104 env->entries[idx]->low_word = op;
1105 env->entries[idx]->high_word = new_rd_Shrs(dbg, irg, block, op,
1106 new_Const_long(mode_Iu, get_mode_size_bits(dst_mode) - 1), dst_mode);
1114 * Translate a Conv to higher_unsigned
1116 static void lower_Conv_to_Lu(ir_node *node, lower_env_t *env) {
1117 ir_node *op = get_Conv_op(node);
1118 ir_mode *mode = get_irn_mode(op);
1120 if (mode_is_int(mode) || mode_is_reference(mode)) {
1121 ir_node *block = get_nodes_block(node);
1122 dbg_info *dbg = get_irn_dbg_info(node);
1123 int idx = get_irn_idx(node);
1124 ir_graph *irg = current_ir_graph;
1125 ir_mode *dst_mode = env->params->low_unsigned;
1127 assert(idx < env->n_entries);
1129 /* simple case: create a high word */
1130 if (mode != env->params->low_unsigned)
1131 op = new_rd_Conv(dbg, irg, block, op, dst_mode);
1133 env->entries[idx]->low_word = op;
1134 env->entries[idx]->high_word = new_Const(dst_mode, get_mode_null(dst_mode));
1142 * Translate a Conv from higher_signed
1144 static void lower_Conv_from_Ls(ir_node *node, lower_env_t *env) {
1145 ir_node *op = get_Conv_op(node);
1146 ir_mode *mode = get_irn_mode(node);
1148 if (mode_is_int(mode) || mode_is_reference(mode)) {
1149 ir_node *block = get_nodes_block(node);
1150 dbg_info *dbg = get_irn_dbg_info(node);
1151 int idx = get_irn_idx(op);
1152 ir_graph *irg = current_ir_graph;
1154 assert(idx < env->n_entries);
1155 op = env->entries[idx]->low_word;
1157 /* simple case: create a high word */
1158 if (mode != env->params->low_signed)
1159 op = new_rd_Conv(dbg, irg, block, op, mode);
1161 set_Conv_op(node, op);
1169 * Translate a Conv from higher_unsigned
1171 static void lower_Conv_from_Lu(ir_node *node, lower_env_t *env) {
1172 ir_node *op = get_Conv_op(node);
1173 ir_mode *mode = get_irn_mode(node);
1175 if (mode_is_int(mode) || mode_is_reference(mode)) {
1176 ir_node *block = get_nodes_block(node);
1177 dbg_info *dbg = get_irn_dbg_info(node);
1178 int idx = get_irn_idx(op);
1179 ir_graph *irg = current_ir_graph;
1181 assert(idx < env->n_entries);
1182 op = env->entries[idx]->low_word;
1184 /* simple case: create a high word */
1185 if (mode != env->params->low_unsigned)
1186 op = new_rd_Conv(dbg, irg, block, op, mode);
1188 set_Conv_op(node, op);
1198 static void lower_Conv(ir_node *node, ir_mode *mode, lower_env_t *env) {
1199 mode = get_irn_mode(node);
1201 if (mode == env->params->high_signed)
1202 lower_Conv_to_Ls(node, env);
1203 else if (mode == env->params->high_unsigned)
1204 lower_Conv_to_Lu(node, env);
1206 ir_mode *mode = get_irn_mode(get_Conv_op(node));
1208 if (mode == env->params->high_signed)
1209 lower_Conv_from_Ls(node, env);
1211 assert(mode == env->params->high_unsigned);
1212 lower_Conv_from_Lu(node, env);
1218 * Lower the method type.
1220 static ir_type *lower_mtp(ir_type *mtp, lower_env_t *env) {
1225 if (is_lowered_type(mtp))
1228 entry = pmap_find(lowered_type, mtp);
1230 int i, n, r, n_param, n_res;
1232 /* count new number of params */
1233 n_param = n = get_method_n_params(mtp);
1234 for (i = n_param - 1; i >= 0; --i) {
1235 ir_type *tp = get_method_param_type(mtp, i);
1237 if (is_Primitive_type(tp)) {
1238 ir_mode *mode = get_type_mode(tp);
1240 if (mode == env->params->high_signed ||
1241 mode == env->params->high_unsigned)
1246 /* count new number of results */
1247 n_res = r = get_method_n_ress(mtp);
1248 for (i = n_res - 1; i >= 0; --i) {
1249 ir_type *tp = get_method_res_type(mtp, i);
1251 if (is_Primitive_type(tp)) {
1252 ir_mode *mode = get_type_mode(tp);
1254 if (mode == env->params->high_signed ||
1255 mode == env->params->high_unsigned)
1260 id = mangle_u(new_id_from_chars("L", 1), get_type_ident(mtp));
1261 res = new_type_method(id, n_param, n_res);
1263 /* set param types and result types */
1264 for (i = n_param = 0; i < n; ++i) {
1265 ir_type *tp = get_method_param_type(mtp, i);
1267 if (is_Primitive_type(tp)) {
1268 ir_mode *mode = get_type_mode(tp);
1270 if (mode == env->params->high_signed) {
1271 set_method_param_type(res, n_param++, tp_s);
1272 set_method_param_type(res, n_param++, tp_s);
1274 else if (mode == env->params->high_unsigned) {
1275 set_method_param_type(res, n_param++, tp_u);
1276 set_method_param_type(res, n_param++, tp_u);
1279 set_method_param_type(res, n_param++, tp);
1282 for (i = n_res = 0; i < r; ++i) {
1283 ir_type *tp = get_method_res_type(mtp, i);
1285 if (is_Primitive_type(tp)) {
1286 ir_mode *mode = get_type_mode(tp);
1288 if (mode == env->params->high_signed) {
1289 set_method_res_type(res, n_res++, tp_s);
1290 set_method_res_type(res, n_res++, tp_s);
1292 else if (mode == env->params->high_unsigned) {
1293 set_method_res_type(res, n_res++, tp_u);
1294 set_method_res_type(res, n_res++, tp_u);
1297 set_method_res_type(res, n_res++, tp);
1300 set_lowered_type(mtp, res);
1301 pmap_insert(lowered_type, mtp, res);
1309 * Translate a Return.
1311 static void lower_Return(ir_node *node, ir_mode *mode, lower_env_t *env) {
1312 ir_graph *irg = current_ir_graph;
1313 entity *ent = get_irg_entity(irg);
1314 ir_type *mtp = get_entity_type(ent);
1319 /* check if this return must be lowered */
1320 for (i = 0, n = get_Return_n_ress(node); i < n; ++i) {
1321 ir_node *pred = get_Return_res(node, i);
1322 ir_mode *mode = get_irn_op_mode(pred);
1324 if (mode == env->params->high_signed ||
1325 mode == env->params->high_unsigned) {
1326 idx = get_irn_idx(pred);
1327 if (! env->entries[idx]->low_word) {
1328 /* not ready yet, wait */
1329 pdeq_putr(env->waitq, node);
1338 ent = get_irg_entity(irg);
1339 mtp = get_entity_type(ent);
1341 mtp = lower_mtp(mtp, env);
1342 set_entity_type(ent, mtp);
1344 /* create a new in array */
1345 NEW_ARR_A(ir_node *, in, get_method_n_ress(mtp) + 1);
1346 in[0] = get_Return_mem(node);
1348 for (j = i = 0, n = get_Return_n_ress(node); i < n; ++i) {
1349 ir_node *pred = get_Return_res(node, i);
1351 idx = get_irn_idx(pred);
1352 assert(idx < env->n_entries);
1354 if (env->entries[idx]) {
1355 in[++j] = env->entries[idx]->low_word;
1356 in[++j] = env->entries[idx]->high_word;
1362 set_irn_in(node, j+1, in);
1366 * Translate the parameters.
1368 static void lower_Start(ir_node *node, ir_mode *mode, lower_env_t *env) {
1369 ir_graph *irg = current_ir_graph;
1370 entity *ent = get_irg_entity(irg);
1371 ir_type *tp = get_entity_type(ent);
1374 int i, j, n_params, rem;
1375 ir_node *proj, *args;
1377 if (is_lowered_type(tp))
1378 mtp = get_associated_type(tp);
1382 assert(! is_lowered_type(mtp));
1384 n_params = get_method_n_params(mtp);
1388 NEW_ARR_A(long, new_projs, n_params);
1390 /* first check if we have parameters that must be fixed */
1391 for (i = j = 0; i < n_params; ++i, ++j) {
1392 ir_type *tp = get_method_param_type(mtp, i);
1395 if (is_Primitive_type(tp)) {
1396 ir_mode *mode = get_type_mode(tp);
1398 if (mode == env->params->high_signed ||
1399 mode == env->params->high_unsigned)
1406 mtp = lower_mtp(mtp, env);
1407 set_entity_type(ent, mtp);
1409 /* switch off optimization for new Proj nodes or they might be CSE'ed
1410 with not patched one's */
1411 rem = get_optimize();
1414 /* ok, fix all Proj's and create new ones */
1415 args = get_irg_args(irg);
1416 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
1417 ir_node *pred = get_Proj_pred(proj);
1423 /* do not visit this node again */
1424 mark_irn_visited(proj);
1429 proj_nr = get_Proj_proj(proj);
1430 set_Proj_proj(proj, new_projs[proj_nr]);
1432 idx = get_irn_idx(proj);
1433 if (env->entries[idx]) {
1434 mode = get_irn_mode(proj);
1436 if (mode == env->params->high_signed)
1437 mode = env->params->low_signed;
1439 mode = env->params->high_signed;
1441 dbg = get_irn_dbg_info(proj);
1442 env->entries[idx]->low_word =
1443 new_rd_Proj(dbg, irg, get_nodes_block(proj), args, mode, new_projs[proj_nr]);
1444 env->entries[idx]->high_word =
1445 new_rd_Proj(dbg, irg, get_nodes_block(proj), args, mode, new_projs[proj_nr] + 1);
1454 static void lower_Call(ir_node *node, ir_mode *mode, lower_env_t *env) {
1455 ir_graph *irg = current_ir_graph;
1456 ir_type *tp = get_Call_type(node);
1458 ir_node **in, *proj, *results;
1459 int n_params, n_res, need_lower = 0;
1461 long *res_numbers = NULL;
1463 if (is_lowered_type(tp))
1464 call_tp = get_associated_type(tp);
1468 assert(! is_lowered_type(call_tp));
1470 n_params = get_method_n_params(call_tp);
1471 for (i = 0; i < n_params; ++i) {
1472 ir_type *tp = get_method_param_type(call_tp, i);
1474 if (is_Primitive_type(tp)) {
1475 ir_mode *mode = get_type_mode(tp);
1477 if (mode == env->params->high_signed ||
1478 mode == env->params->high_unsigned) {
1484 n_res = get_method_n_ress(call_tp);
1486 NEW_ARR_A(long, res_numbers, n_res);
1488 for (i = j = 0; i < n_res; ++i, ++j) {
1489 ir_type *tp = get_method_res_type(call_tp, i);
1492 if (is_Primitive_type(tp)) {
1493 ir_mode *mode = get_type_mode(tp);
1495 if (mode == env->params->high_signed ||
1496 mode == env->params->high_unsigned) {
1507 /* let's lower it */
1508 call_tp = lower_mtp(call_tp, env);
1509 set_Call_type(node, call_tp);
1511 NEW_ARR_A(ir_node *, in, get_method_n_params(call_tp) + 2);
1513 in[0] = get_Call_mem(node);
1514 in[1] = get_Call_ptr(node);
1516 for (j = 2, i = 0; i < n_params; ++i) {
1517 ir_node *pred = get_Call_param(node, i);
1518 int idx = get_irn_idx(pred);
1520 if (env->entries[idx]) {
1521 if (! env->entries[idx]->low_word) {
1522 /* not ready yet, wait */
1523 pdeq_putr(env->waitq, node);
1526 in[j++] = env->entries[idx]->low_word;
1527 in[j++] = env->entries[idx]->high_word;
1533 set_irn_in(node, j, in);
1535 /* fix the results */
1537 for (proj = get_irn_link(node); proj; proj = get_irn_link(proj)) {
1538 long proj_nr = get_Proj_proj(proj);
1540 if (proj_nr == pn_Call_T_result && get_Proj_pred(proj) == node) {
1541 /* found the result proj */
1547 if (results) { /* there are results */
1548 int rem = get_optimize();
1550 /* switch off optimization for new Proj nodes or they might be CSE'ed
1551 with not patched one's */
1553 for (i = j = 0, proj = get_irn_link(results); proj; proj = get_irn_link(proj), ++i, ++j) {
1554 if (get_Proj_pred(proj) == results) {
1555 long proj_nr = get_Proj_proj(proj);
1558 /* found a result */
1559 set_Proj_proj(proj, res_numbers[proj_nr]);
1560 idx = get_irn_idx(proj);
1561 if (env->entries[idx]) {
1562 ir_mode *mode = get_irn_mode(proj);
1565 if (mode == env->params->high_signed)
1566 mode = env->params->low_signed;
1568 mode = env->params->low_unsigned;
1570 dbg = get_irn_dbg_info(proj);
1571 env->entries[idx]->low_word =
1572 new_rd_Proj(dbg, irg, get_nodes_block(proj), results, mode, res_numbers[proj_nr]);
1573 env->entries[idx]->high_word =
1574 new_rd_Proj(dbg, irg, get_nodes_block(proj), results, mode, res_numbers[proj_nr] + 1);
1576 mark_irn_visited(proj);
1584 * Translate an Unknown into two.
1586 static void lower_Unknown(ir_node *node, ir_mode *mode, lower_env_t *env) {
1587 int idx = get_irn_idx(node);
1589 env->entries[idx]->low_word =
1590 env->entries[idx]->high_word = new_r_Unknown(current_ir_graph, mode);
1596 * First step: just create two templates
1598 static void lower_Phi(ir_node *phi, ir_mode *mode, lower_env_t *env) {
1599 ir_node *block, *unk;
1600 ir_node **inl, **inh;
1602 int idx, i, arity = get_Phi_n_preds(phi);
1605 idx = get_irn_idx(phi);
1606 if (env->entries[idx]->low_word) {
1607 /* Phi nodes already build, check for inputs */
1608 ir_node *phil = env->entries[idx]->low_word;
1609 ir_node *phih = env->entries[idx]->high_word;
1611 for (i = 0; i < arity; ++i) {
1612 ir_node *pred = get_Phi_pred(phi, i);
1613 int idx = get_irn_idx(pred);
1615 if (env->entries[idx]->low_word) {
1616 set_Phi_pred(phil, i, env->entries[idx]->low_word);
1617 set_Phi_pred(phil, i, env->entries[idx]->high_word);
1620 /* still not ready */
1621 pdeq_putr(env->waitq, phi);
1627 /* first create a new in array */
1628 NEW_ARR_A(ir_node *, inl, arity);
1629 NEW_ARR_A(ir_node *, inh, arity);
1630 unk = new_r_Unknown(current_ir_graph, mode);
1632 for (i = 0; i < arity; ++i) {
1633 ir_node *pred = get_Phi_pred(phi, i);
1634 int idx = get_irn_idx(pred);
1636 if (env->entries[idx]->low_word) {
1637 inl[i] = env->entries[idx]->low_word;
1638 inh[i] = env->entries[idx]->high_word;
1647 dbg = get_irn_dbg_info(phi);
1648 block = get_nodes_block(phi);
1650 idx = get_irn_idx(phi);
1651 assert(idx < env->n_entries);
1652 env->entries[idx]->low_word = new_rd_Phi(dbg, current_ir_graph, block, arity, inl, mode);
1653 env->entries[idx]->high_word = new_rd_Phi(dbg, current_ir_graph, block, arity, inh, mode);
1656 /* not yet finished */
1657 pdeq_putr(env->waitq, phi);
1662 * check for opcodes that must always be lowered.
1664 static int always_lower(opcode code) {
1676 /** The type of a lower function. */
1677 typedef void (*lower_func)(ir_node *node, ir_mode *mode, lower_env_t *env);
1682 static void lower_ops(ir_node *node, void *env)
1684 lower_env_t *lenv = env;
1685 node_entry_t *entry;
1686 int idx = get_irn_idx(node);
1688 entry = lenv->entries[idx];
1689 if (entry || always_lower(get_irn_opcode(node))) {
1690 ir_op *op = get_irn_op(node);
1691 lower_func func = (lower_func)op->ops.generic;
1694 ir_mode *mode = get_irn_op_mode(node);
1696 if (mode == lenv->params->high_signed)
1697 mode = lenv->params->low_signed;
1699 mode = lenv->params->low_unsigned;
1701 DB((dbg, LEVEL_1, " %+F\n", node));
1702 func(node, mode, lenv);
1707 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
1710 * Compare two op_mode_entry_t's.
1712 static int cmp_op_mode(const void *elt, const void *key, size_t size) {
1713 const op_mode_entry_t *e1 = elt;
1714 const op_mode_entry_t *e2 = key;
1716 return (e1->op - e2->op) | (e1->mode - e2->mode);
1722 void lower_dw_ops(const lwrdw_param_t *param)
1730 if (! param->enable)
1733 FIRM_DBG_REGISTER(dbg, "firm.lower.dw");
1734 firm_dbg_set_mask(dbg, SET_LEVEL_2);
1736 assert(2 * get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->high_signed));
1737 assert(2 * get_mode_size_bits(param->low_unsigned) == get_mode_size_bits(param->high_unsigned));
1738 assert(get_mode_size_bits(param->low_signed) == get_mode_size_bits(param->low_unsigned));
1740 if (! intrinsic_fkt)
1741 intrinsic_fkt = new_set(cmp_op_mode, iro_MaxOpcode);
1743 lowered_type = pmap_create();
1746 tp_u = new_type_primitive(IDENT("_i_uint"), param->low_unsigned);
1748 tp_s = new_type_primitive(IDENT("_i_int"), param->low_signed);
1751 binop_tp_u = new_type_method(IDENT("binop_u_intrinsic"), 4, 2);
1753 set_method_param_type(binop_tp_u, 0, tp_u);
1754 set_method_param_type(binop_tp_u, 1, tp_u);
1755 set_method_param_type(binop_tp_u, 2, tp_u);
1756 set_method_param_type(binop_tp_u, 3, tp_u);
1757 set_method_res_type(binop_tp_u, 0, tp_u);
1758 set_method_res_type(binop_tp_u, 1, tp_u);
1761 binop_tp_s = new_type_method(IDENT("binop_s_intrinsic"), 4, 2);
1762 set_method_param_type(binop_tp_s, 0, tp_s);
1763 set_method_param_type(binop_tp_s, 1, tp_s);
1764 set_method_param_type(binop_tp_s, 2, tp_s);
1765 set_method_param_type(binop_tp_s, 3, tp_s);
1766 set_method_res_type(binop_tp_s, 0, tp_s);
1767 set_method_res_type(binop_tp_s, 1, tp_s);
1770 unop_tp_u = new_type_method(IDENT("unop_u_intrinsic"), 2, 2);
1771 set_method_param_type(unop_tp_u, 0, tp_u);
1772 set_method_param_type(unop_tp_u, 1, tp_u);
1773 set_method_res_type(unop_tp_u, 0, tp_u);
1774 set_method_res_type(unop_tp_u, 1, tp_u);
1777 unop_tp_s = new_type_method(IDENT("unop_s_intrinsic"), 2, 2);
1778 set_method_param_type(unop_tp_s, 0, tp_s);
1779 set_method_param_type(unop_tp_s, 1, tp_s);
1780 set_method_res_type(unop_tp_s, 0, tp_s);
1781 set_method_res_type(unop_tp_s, 1, tp_s);
1784 lenv.tv_mode_bytes = new_tarval_from_long(get_mode_size_bytes(param->low_unsigned), mode_Iu);
1785 lenv.waitq = new_pdeq();
1786 lenv.params = param;
1788 /* first clear the generic function pointer for all ops */
1789 clear_irp_opcodes_generic_func();
1791 #define LOWER2(op, fkt) op_##op->ops.generic = (op_func)fkt
1792 #define LOWER(op) LOWER2(op, lower_##op)
1793 #define LOWER_BIN(op) LOWER2(op, lower_Binop)
1794 #define LOWER_UN(op) LOWER2(op, lower_Unop)
1830 /* transform all graphs */
1831 for (i = get_irp_n_irgs() - 1; i >= 0; --i) {
1832 ir_graph *irg = get_irp_irg(i);
1835 obstack_init(&lenv.obst);
1837 n_idx = get_irg_last_idx(irg);
1838 lenv.n_entries = n_idx;
1839 lenv.entries = xmalloc(n_idx * sizeof(lenv.entries[0]));
1840 memset(lenv.entries, 0, n_idx * sizeof(lenv.entries[0]));
1842 /* first step: link all nodes and allocate data */
1844 lenv.proj_2_block = pmap_create();
1845 irg_walk_graph(irg, firm_clear_link, prepare_links, &lenv);
1847 if (lenv.flags & MUST_BE_LOWERED) {
1848 DB((dbg, LEVEL_1, "Lowering graph %+F\n", irg));
1850 /* must do some work */
1851 irg_walk_graph(irg, NULL, lower_ops, &lenv);
1853 /* last step: all waiting nodes */
1854 DB((dbg, LEVEL_1, "finishing waiting nodes:\n"));
1855 while (! pdeq_empty(lenv.waitq)) {
1856 ir_node *node = pdeq_getl(lenv.waitq);
1858 lower_ops(node, &lenv);
1861 /* outs are invalid, we changed the graph */
1862 set_irg_outs_inconsistent(irg);
1864 if (lenv.flags & CF_CHANGED) {
1865 /* control flow changed, dominance info is invalid */
1866 set_irg_doms_inconsistent(irg);
1867 set_irg_extblk_inconsistent(irg);
1868 set_irg_loopinfo_inconsistent(irg);
1871 dump_ir_block_graph(irg, "-dw");
1873 pmap_destroy(lenv.proj_2_block);
1875 obstack_free(&lenv.obst, NULL);
1877 del_pdeq(lenv.waitq);
1880 /* Default implementation. */
1881 entity *def_create_intrinsic_fkt(ir_type *method, const ir_op *op, const ir_mode *mode, void *context)
1886 snprintf(buf, sizeof(buf), "__l%s%s", get_op_name(op), get_mode_name(mode));
1887 id = new_id_from_str(buf);
1889 return new_entity(get_glob_type(), id, method);