2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Machine dependent Firm optimizations.
24 * @author Sebastian Hack, Michael Beck
38 #include "irgraph_t.h"
45 #include "dbginfo_t.h"
46 #include "iropt_dbg.h"
56 /* when we need verifying */
58 # define IRN_VRFY_IRG(res, irg)
60 # define IRN_VRFY_IRG(res, irg) irn_vrfy_irg(res, irg)
63 /** The params got from the factory in arch_dep_init(...). */
64 static const ir_settings_arch_dep_t *params = NULL;
66 /** The bit mask, which optimizations to apply. */
67 static arch_dep_opts_t opts;
69 /* we need this new pseudo op */
70 static ir_op *op_Mulh = NULL;
73 * construct a Mulh: Mulh(a,b) = (a * b) >> w, w is the with in bits of a, b
76 new_rd_Mulh (dbg_info *db, ir_graph *irg, ir_node *block,
77 ir_node *op1, ir_node *op2, ir_mode *mode) {
83 res = new_ir_node(db, irg, block, op_Mulh, mode, 2, in);
84 res = optimize_node(res);
85 IRN_VRFY_IRG(res, irg);
89 ir_op *get_op_Mulh(void) { return op_Mulh; }
91 void arch_dep_init(arch_dep_params_factory_t factory) {
98 int mulh_opc = get_next_ir_opcode();
100 /* create the Mulh operation */
101 op_Mulh = new_ir_op(mulh_opc, "Mulh", op_pin_state_floats, irop_flag_commutative, oparity_binary, 0, 0, NULL);
105 void arch_dep_set_opts(arch_dep_opts_t the_opts) {
109 /** check, whether a mode allows a Mulh instruction. */
110 static int allow_Mulh(ir_mode *mode) {
111 if (get_mode_size_bits(mode) > params->max_bits_for_mulh)
113 return (mode_is_signed(mode) && params->allow_mulhs) || (!mode_is_signed(mode) && params->allow_mulhu);
116 /* Replace Muls with Shifts and Add/Subs. */
117 ir_node *arch_dep_replace_mul_with_shifts(ir_node *irn) {
119 ir_mode *mode = get_irn_mode(irn);
121 /* If the architecture dependent optimizations were not initialized
122 or this optimization was not enabled. */
123 if (params == NULL || (opts & arch_dep_mul_to_shift) == 0)
126 if (get_irn_op(irn) == op_Mul && mode_is_int(mode)) {
127 ir_node *block = get_nodes_block(irn);
128 ir_node *left = get_binop_left(irn);
129 ir_node *right = get_binop_right(irn);
131 ir_node *operand = NULL;
133 /* Look, if one operand is a constant. */
134 if (get_irn_opcode(left) == iro_Const) {
135 tv = get_Const_tarval(left);
137 } else if(get_irn_opcode(right) == iro_Const) {
138 tv = get_Const_tarval(right);
143 int maximum_shifts = params->maximum_shifts;
144 int also_use_subs = params->also_use_subs;
145 int highest_shift_amount = params->highest_shift_amount;
147 char *bitstr = get_tarval_bitpattern(tv);
153 char compr[MAX_BITSTR];
157 int shift_with_sub[MAX_BITSTR] = { 0 };
158 int shift_without_sub[MAX_BITSTR] = { 0 };
159 int shift_with_sub_pos = 0;
160 int shift_without_sub_pos = 0;
164 long val = get_tarval_long(tv);
165 fprintf(stderr, "Found mul with %ld(%lx) = ", val, val);
166 for(p = bitstr; *p != '\0'; p++)
172 for(p = bitstr; *p != '\0'; p++) {
176 /* The last was 1 we are now at 0 OR
177 * The last was 0 and we are now at 1 */
178 compr[compr_len++] = counter;
185 compr[compr_len++] = counter;
189 const char *prefix = "";
190 for(i = 0; i < compr_len; i++, prefix = ",")
191 fprintf(stderr, "%s%d", prefix, compr[i]);
196 /* Go over all recorded one groups. */
199 for(i = 1; i < compr_len; i = end_of_group + 2) {
200 int j, zeros_in_group, ones_in_group;
202 ones_in_group = compr[i];
205 /* Scan for singular 0s in a sequence. */
206 for(j = i + 1; j < compr_len && compr[j] == 1; j += 2) {
208 ones_in_group += (j + 1 < compr_len ? compr[j + 1] : 0);
210 end_of_group = j - 1;
212 if(zeros_in_group >= ones_in_group - 1)
216 fprintf(stderr, " i:%d, eg:%d\n", i, end_of_group);
219 singleton = compr[i] == 1 && i == end_of_group;
220 for(j = i; j <= end_of_group; j += 2) {
221 int curr_ones = compr[j];
222 int biased_curr_bit = curr_bit + 1;
226 fprintf(stderr, " j:%d, ones:%d\n", j, curr_ones);
229 /* If this ones group is a singleton group (it has no
230 singleton zeros inside. */
232 shift_with_sub[shift_with_sub_pos++] = biased_curr_bit;
234 shift_with_sub[shift_with_sub_pos++] = -biased_curr_bit;
236 for(k = 0; k < curr_ones; k++)
237 shift_without_sub[shift_without_sub_pos++] = biased_curr_bit + k;
239 curr_bit += curr_ones;
240 biased_curr_bit = curr_bit + 1;
242 if(!singleton && j == end_of_group)
243 shift_with_sub[shift_with_sub_pos++] = biased_curr_bit;
244 else if(j != end_of_group)
245 shift_with_sub[shift_with_sub_pos++] = -biased_curr_bit;
247 curr_bit += compr[j + 1];
252 int *shifts = shift_with_sub;
253 int n = shift_with_sub_pos;
254 int highest_shift_wide = 0;
255 int highest_shift_seq = 0;
258 /* If we may not use subs, or we can achive the same with adds,
260 if(!also_use_subs || shift_with_sub_pos >= shift_without_sub_pos) {
261 shifts = shift_without_sub;
262 n = shift_without_sub_pos;
265 /* If the number of needed shifts exceeds the given maximum,
266 use the Mul and exit. */
267 if(n > maximum_shifts) {
269 fprintf(stderr, "Only allowed %d shifts, but %d are needed\n",
275 /* Compute the highest shift needed for both, the
276 sequential and wide representations. */
277 for(i = 0; i < n; i++) {
278 int curr = abs(shifts[i]);
279 int curr_seq = curr - last;
281 highest_shift_wide = curr > highest_shift_wide ? curr : highest_shift_wide;
282 highest_shift_seq = curr_seq > highest_shift_seq ? curr_seq : highest_shift_seq;
287 /* If the highest shift amount is greater than the given limit,
289 if(highest_shift_seq > highest_shift_amount) {
291 fprintf(stderr, "Shift argument %d exceeds maximum %d\n",
292 highest_shift_seq, highest_shift_amount);
297 /* If we have subs, we cannot do sequential. */
298 if(1 /* also_use_subs */) {
300 ir_node *curr = NULL;
305 int curr_shift = shifts[i];
306 int sub = curr_shift < 0;
307 int amount = abs(curr_shift) - 1;
308 ir_node *aux = operand;
310 assert(amount >= 0 && "What is a negative shift??");
313 ir_node *cnst = new_r_Const_long(current_ir_graph, block, mode_Iu, amount);
314 aux = new_r_Shl(current_ir_graph, block, operand, cnst, mode);
319 curr = new_r_Sub(current_ir_graph, block, curr, aux, mode);
321 curr = new_r_Add(current_ir_graph, block, curr, aux, mode);
333 const char *prefix = "";
334 for (i = 0; i < n; ++i) {
335 fprintf(stderr, "%s%d", prefix, shifts[i]);
338 fprintf(stderr, "\n");
351 hook_arch_dep_replace_mul_with_shifts(irn);
357 * calculated the ld2 of a tarval if tarval is 2^n, else returns -1.
359 static int tv_ld2(tarval *tv, int bits) {
362 for (num = i = 0; i < bits; ++i) {
363 unsigned char v = get_tarval_sub_bits(tv, i);
368 for (j = 0; j < 8; ++j)
381 /* for shorter lines */
382 #define ABS(a) tarval_abs(a)
383 #define NEG(a) tarval_neg(a)
384 #define NOT(a) tarval_not(a)
385 #define SHL(a, b) tarval_shl(a, b)
386 #define SHR(a, b) tarval_shr(a, b)
387 #define ADD(a, b) tarval_add(a, b)
388 #define SUB(a, b) tarval_sub(a, b)
389 #define MUL(a, b) tarval_mul(a, b)
390 #define DIV(a, b) tarval_div(a, b)
391 #define MOD(a, b) tarval_mod(a, b)
392 #define CMP(a, b) tarval_cmp(a, b)
393 #define CNV(a, m) tarval_convert_to(a, m)
394 #define ONE(m) get_mode_one(m)
395 #define ZERO(m) get_mode_null(m)
397 /** The result of a the magic() function. */
399 tarval *M; /**< magic number */
400 int s; /**< shift amount */
401 int need_add; /**< an additional add is needed */
402 int need_sub; /**< an additional sub is needed */
406 * Signed division by constant d: calculate the Magic multiplier M and the shift amount s
408 * see Hacker's Delight: 10-6 Integer Division by Constants: Incorporation into a Compiler
410 static struct ms magic(tarval *d) {
411 ir_mode *mode = get_tarval_mode(d);
412 ir_mode *u_mode = find_unsigned_mode(mode);
413 int bits = get_mode_size_bits(u_mode);
415 tarval *ad, *anc, *delta, *q1, *r1, *q2, *r2, *t; /* unsigned */
418 tarval *bits_minus_1, *two_bits_1;
422 tarval_int_overflow_mode_t rem = tarval_get_integer_overflow_mode();
424 /* we need overflow mode to work correctly */
425 tarval_set_integer_overflow_mode(TV_OVERFLOW_WRAP);
428 bits_minus_1 = new_tarval_from_long(bits - 1, u_mode);
429 two_bits_1 = SHL(get_mode_one(u_mode), bits_minus_1);
431 ad = CNV(ABS(d), u_mode);
432 t = ADD(two_bits_1, SHR(CNV(d, u_mode), bits_minus_1));
433 anc = SUB(SUB(t, ONE(u_mode)), MOD(t, ad)); /* Absolute value of nc */
434 p = bits - 1; /* Init: p */
435 q1 = DIV(two_bits_1, anc); /* Init: q1 = 2^p/|nc| */
436 r1 = SUB(two_bits_1, MUL(q1, anc)); /* Init: r1 = rem(2^p, |nc|) */
437 q2 = DIV(two_bits_1, ad); /* Init: q2 = 2^p/|d| */
438 r2 = SUB(two_bits_1, MUL(q2, ad)); /* Init: r2 = rem(2^p, |d|) */
442 q1 = ADD(q1, q1); /* Update q1 = 2^p/|nc| */
443 r1 = ADD(r1, r1); /* Update r1 = rem(2^p, |nc|) */
445 if (CMP(r1, anc) & pn_Cmp_Ge) {
446 q1 = ADD(q1, ONE(u_mode));
450 q2 = ADD(q2, q2); /* Update q2 = 2^p/|d| */
451 r2 = ADD(r2, r2); /* Update r2 = rem(2^p, |d|) */
453 if (CMP(r2, ad) & pn_Cmp_Ge) {
454 q2 = ADD(q2, ONE(u_mode));
459 } while (CMP(q1, delta) & pn_Cmp_Lt || (CMP(q1, delta) & pn_Cmp_Eq && CMP(r1, ZERO(u_mode)) & pn_Cmp_Eq));
461 d_cmp = CMP(d, ZERO(mode));
463 if (d_cmp & pn_Cmp_Ge)
464 mag.M = ADD(CNV(q2, mode), ONE(mode));
466 mag.M = SUB(ZERO(mode), ADD(CNV(q2, mode), ONE(mode)));
468 M_cmp = CMP(mag.M, ZERO(mode));
472 /* need an add if d > 0 && M < 0 */
473 mag.need_add = d_cmp & pn_Cmp_Gt && M_cmp & pn_Cmp_Lt;
475 /* need a sub if d < 0 && M > 0 */
476 mag.need_sub = d_cmp & pn_Cmp_Lt && M_cmp & pn_Cmp_Gt;
478 tarval_set_integer_overflow_mode(rem);
483 /** The result of the magicu() function. */
485 tarval *M; /**< magic add constant */
486 int s; /**< shift amount */
487 int need_add; /**< add indicator */
491 * Unsigned division by constant d: calculate the Magic multiplier M and the shift amount s
493 * see Hacker's Delight: 10-10 Integer Division by Constants: Incorporation into a Compiler (Unsigned)
495 static struct mu magicu(tarval *d) {
496 ir_mode *mode = get_tarval_mode(d);
497 int bits = get_mode_size_bits(mode);
499 tarval *nc, *delta, *q1, *r1, *q2, *r2;
500 tarval *bits_minus_1, *two_bits_1, *seven_ff;
504 tarval_int_overflow_mode_t rem = tarval_get_integer_overflow_mode();
506 /* we need overflow mode to work correctly */
507 tarval_set_integer_overflow_mode(TV_OVERFLOW_WRAP);
509 bits_minus_1 = new_tarval_from_long(bits - 1, mode);
510 two_bits_1 = SHL(get_mode_one(mode), bits_minus_1);
511 seven_ff = SUB(two_bits_1, ONE(mode));
513 magu.need_add = 0; /* initialize the add indicator */
514 nc = SUB(NEG(ONE(mode)), MOD(NEG(d), d));
515 p = bits - 1; /* Init: p */
516 q1 = DIV(two_bits_1, nc); /* Init: q1 = 2^p/nc */
517 r1 = SUB(two_bits_1, MUL(q1, nc)); /* Init: r1 = rem(2^p, nc) */
518 q2 = DIV(seven_ff, d); /* Init: q2 = (2^p - 1)/d */
519 r2 = SUB(seven_ff, MUL(q2, d)); /* Init: r2 = rem(2^p - 1, d) */
523 if (CMP(r1, SUB(nc, r1)) & pn_Cmp_Ge) {
524 q1 = ADD(ADD(q1, q1), ONE(mode));
525 r1 = SUB(ADD(r1, r1), nc);
532 if (CMP(ADD(r2, ONE(mode)), SUB(d, r2)) & pn_Cmp_Ge) {
533 if (CMP(q2, seven_ff) & pn_Cmp_Ge)
536 q2 = ADD(ADD(q2, q2), ONE(mode));
537 r2 = SUB(ADD(ADD(r2, r2), ONE(mode)), d);
540 if (CMP(q2, two_bits_1) & pn_Cmp_Ge)
544 r2 = ADD(ADD(r2, r2), ONE(mode));
546 delta = SUB(SUB(d, ONE(mode)), r2);
547 } while (p < 2*bits &&
548 (CMP(q1, delta) & pn_Cmp_Lt || (CMP(q1, delta) & pn_Cmp_Eq && CMP(r1, ZERO(mode)) & pn_Cmp_Eq)));
550 magu.M = ADD(q2, ONE(mode)); /* Magic number */
551 magu.s = p - bits; /* and shift amount */
553 tarval_set_integer_overflow_mode(rem);
559 * Build the Mulh replacement code for n / tv.
561 * Note that 'div' might be a mod or DivMod operation as well
563 static ir_node *replace_div_by_mulh(ir_node *div, tarval *tv) {
564 dbg_info *dbg = get_irn_dbg_info(div);
565 ir_node *n = get_binop_left(div);
566 ir_node *block = get_nodes_block(div);
567 ir_mode *mode = get_irn_mode(n);
568 int bits = get_mode_size_bits(mode);
571 /* Beware: do not transform bad code */
572 if (is_Bad(n) || is_Bad(block))
575 if (mode_is_signed(mode)) {
576 struct ms mag = magic(tv);
578 /* generate the Mulh instruction */
579 c = new_r_Const(current_ir_graph, block, mode, mag.M);
580 q = new_rd_Mulh(dbg, current_ir_graph, block, n, c, mode);
582 /* do we need an Add or Sub */
584 q = new_rd_Add(dbg, current_ir_graph, block, q, n, mode);
585 else if (mag.need_sub)
586 q = new_rd_Sub(dbg, current_ir_graph, block, q, n, mode);
588 /* Do we need the shift */
590 c = new_r_Const_long(current_ir_graph, block, mode_Iu, mag.s);
591 q = new_rd_Shrs(dbg, current_ir_graph, block, q, c, mode);
595 c = new_r_Const_long(current_ir_graph, block, mode_Iu, bits-1);
596 t = new_rd_Shr(dbg, current_ir_graph, block, q, c, mode);
598 q = new_rd_Add(dbg, current_ir_graph, block, q, t, mode);
600 struct mu mag = magicu(tv);
603 /* generate the Mulh instruction */
604 c = new_r_Const(current_ir_graph, block, mode, mag.M);
605 q = new_rd_Mulh(dbg, current_ir_graph, block, n, c, mode);
609 /* use the GM scheme */
610 t = new_rd_Sub(dbg, current_ir_graph, block, n, q, mode);
612 c = new_r_Const(current_ir_graph, block, mode_Iu, get_mode_one(mode_Iu));
613 t = new_rd_Shr(dbg, current_ir_graph, block, t, c, mode);
615 t = new_rd_Add(dbg, current_ir_graph, block, t, q, mode);
617 c = new_r_Const_long(current_ir_graph, block, mode_Iu, mag.s-1);
618 q = new_rd_Shr(dbg, current_ir_graph, block, t, c, mode);
620 /* use the default scheme */
621 q = new_rd_Add(dbg, current_ir_graph, block, q, n, mode);
623 } else if (mag.s > 0) { /* default scheme, shift needed */
624 c = new_r_Const_long(current_ir_graph, block, mode_Iu, mag.s);
625 q = new_rd_Shr(dbg, current_ir_graph, block, q, c, mode);
631 /* Replace Divs with Shifts and Add/Subs and Mulh. */
632 ir_node *arch_dep_replace_div_by_const(ir_node *irn) {
635 /* If the architecture dependent optimizations were not initialized
636 or this optimization was not enabled. */
637 if (params == NULL || (opts & arch_dep_div_by_const) == 0)
640 if (get_irn_opcode(irn) == iro_Div) {
641 ir_node *c = get_Div_right(irn);
642 ir_node *block, *left;
649 if (get_irn_op(c) != op_Const)
652 tv = get_Const_tarval(c);
654 /* check for division by zero */
655 if (classify_tarval(tv) == TV_CLASSIFY_NULL)
658 left = get_Div_left(irn);
659 mode = get_irn_mode(left);
660 block = get_nodes_block(irn);
661 dbg = get_irn_dbg_info(irn);
663 bits = get_mode_size_bits(mode);
667 if (mode_is_signed(mode)) {
668 /* for signed divisions, the algorithm works for a / -2^k by negating the result */
669 ntv = tarval_neg(tv);
679 if (k >= 0) { /* division by 2^k or -2^k */
680 if (mode_is_signed(mode)) {
682 ir_node *curr = left;
685 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k - 1);
686 curr = new_rd_Shrs(dbg, current_ir_graph, block, left, k_node, mode);
689 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, bits - k);
690 curr = new_rd_Shr(dbg, current_ir_graph, block, curr, k_node, mode);
692 curr = new_rd_Add(dbg, current_ir_graph, block, left, curr, mode);
694 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k);
695 res = new_rd_Shrs(dbg, current_ir_graph, block, curr, k_node, mode);
697 if (n_flag) { /* negate the result */
700 k_node = new_r_Const(current_ir_graph, block, mode, get_mode_null(mode));
701 res = new_rd_Sub(dbg, current_ir_graph, block, k_node, res, mode);
703 } else { /* unsigned case */
706 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k);
707 res = new_rd_Shr(dbg, current_ir_graph, block, left, k_node, mode);
711 if (allow_Mulh(mode))
712 res = replace_div_by_mulh(irn, tv);
717 hook_arch_dep_replace_division_by_const(irn);
722 /* Replace Mods with Shifts and Add/Subs and Mulh. */
723 ir_node *arch_dep_replace_mod_by_const(ir_node *irn) {
726 /* If the architecture dependent optimizations were not initialized
727 or this optimization was not enabled. */
728 if (params == NULL || (opts & arch_dep_mod_by_const) == 0)
731 if (get_irn_opcode(irn) == iro_Mod) {
732 ir_node *c = get_Mod_right(irn);
733 ir_node *block, *left;
740 if (get_irn_op(c) != op_Const)
743 tv = get_Const_tarval(c);
745 /* check for division by zero */
746 if (classify_tarval(tv) == TV_CLASSIFY_NULL)
749 left = get_Mod_left(irn);
750 mode = get_irn_mode(left);
751 block = get_nodes_block(irn);
752 dbg = get_irn_dbg_info(irn);
753 bits = get_mode_size_bits(mode);
757 if (mode_is_signed(mode)) {
758 /* for signed divisions, the algorithm works for a / -2^k by negating the result */
759 ntv = tarval_neg(tv);
768 /* division by 2^k or -2^k:
769 * we use "modulus" here, so x % y == x % -y that's why is no difference between the case 2^k and -2^k
771 if (mode_is_signed(mode)) {
773 ir_node *curr = left;
776 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k - 1);
777 curr = new_rd_Shrs(dbg, current_ir_graph, block, left, k_node, mode);
780 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, bits - k);
781 curr = new_rd_Shr(dbg, current_ir_graph, block, curr, k_node, mode);
783 curr = new_rd_Add(dbg, current_ir_graph, block, left, curr, mode);
785 k_node = new_r_Const_long(current_ir_graph, block, mode, (-1) << k);
786 curr = new_rd_And(dbg, current_ir_graph, block, curr, k_node, mode);
788 res = new_rd_Sub(dbg, current_ir_graph, block, left, curr, mode);
789 } else { /* unsigned case */
792 k_node = new_r_Const_long(current_ir_graph, block, mode, (1 << k) - 1);
793 res = new_rd_And(dbg, current_ir_graph, block, left, k_node, mode);
797 if (allow_Mulh(mode)) {
798 res = replace_div_by_mulh(irn, tv);
800 res = new_rd_Mul(dbg, current_ir_graph, block, res, c, mode);
802 /* res = arch_dep_mul_to_shift(res); */
804 res = new_rd_Sub(dbg, current_ir_graph, block, left, res, mode);
810 hook_arch_dep_replace_division_by_const(irn);
815 /* Replace DivMods with Shifts and Add/Subs and Mulh. */
816 void arch_dep_replace_divmod_by_const(ir_node **div, ir_node **mod, ir_node *irn) {
819 /* If the architecture dependent optimizations were not initialized
820 or this optimization was not enabled. */
821 if (params == NULL ||
822 ((opts & (arch_dep_div_by_const|arch_dep_mod_by_const)) != (arch_dep_div_by_const|arch_dep_mod_by_const)))
825 if (get_irn_opcode(irn) == iro_DivMod) {
826 ir_node *c = get_DivMod_right(irn);
827 ir_node *block, *left;
834 if (get_irn_op(c) != op_Const)
837 tv = get_Const_tarval(c);
839 /* check for division by zero */
840 if (classify_tarval(tv) == TV_CLASSIFY_NULL)
843 left = get_DivMod_left(irn);
844 mode = get_irn_mode(left);
845 block = get_nodes_block(irn);
846 dbg = get_irn_dbg_info(irn);
848 bits = get_mode_size_bits(mode);
852 if (mode_is_signed(mode)) {
853 /* for signed divisions, the algorithm works for a / -2^k by negating the result */
854 ntv = tarval_neg(tv);
864 if (k >= 0) { /* division by 2^k or -2^k */
865 if (mode_is_signed(mode)) {
866 ir_node *k_node, *c_k;
867 ir_node *curr = left;
870 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k - 1);
871 curr = new_rd_Shrs(dbg, current_ir_graph, block, left, k_node, mode);
874 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, bits - k);
875 curr = new_rd_Shr(dbg, current_ir_graph, block, curr, k_node, mode);
877 curr = new_rd_Add(dbg, current_ir_graph, block, left, curr, mode);
879 c_k = new_r_Const_long(current_ir_graph, block, mode_Iu, k);
881 *div = new_rd_Shrs(dbg, current_ir_graph, block, curr, c_k, mode);
883 if (n_flag) { /* negate the div result */
886 k_node = new_r_Const(current_ir_graph, block, mode, get_mode_null(mode));
887 *div = new_rd_Sub(dbg, current_ir_graph, block, k_node, *div, mode);
890 k_node = new_r_Const_long(current_ir_graph, block, mode, (-1) << k);
891 curr = new_rd_And(dbg, current_ir_graph, block, curr, k_node, mode);
893 *mod = new_rd_Sub(dbg, current_ir_graph, block, left, curr, mode);
894 } else { /* unsigned case */
897 k_node = new_r_Const_long(current_ir_graph, block, mode_Iu, k);
898 *div = new_rd_Shr(dbg, current_ir_graph, block, left, k_node, mode);
900 k_node = new_r_Const_long(current_ir_graph, block, mode, (1 << k) - 1);
901 *mod = new_rd_And(dbg, current_ir_graph, block, left, k_node, mode);
905 if (allow_Mulh(mode)) {
908 *div = replace_div_by_mulh(irn, tv);
910 t = new_rd_Mul(dbg, current_ir_graph, block, *div, c, mode);
912 /* t = arch_dep_mul_to_shift(t); */
914 *mod = new_rd_Sub(dbg, current_ir_graph, block, left, t, mode);
920 hook_arch_dep_replace_division_by_const(irn);
924 static const ir_settings_arch_dep_t default_params = {
925 1, /* also use subs */
926 4, /* maximum shifts */
927 31, /* maximum shift amount */
931 32 /* Mulh allowed up to 32 bit */
934 /* A default parameter factory for testing purposes. */
935 const ir_settings_arch_dep_t *arch_dep_default_factory(void) {
936 return &default_params;