2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
31 #include "irgraph_t.h"
37 #include "iroptimize.h"
47 #include "betranshlp.h"
48 #include "beabihelper.h"
49 #include "bearch_sparc_t.h"
51 #include "sparc_nodes_attr.h"
52 #include "sparc_transform.h"
53 #include "sparc_new_nodes.h"
54 #include "gen_sparc_new_nodes.h"
56 #include "gen_sparc_regalloc_if.h"
57 #include "sparc_cconv.h"
61 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
63 typedef struct reg_info_t {
68 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
69 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
70 static calling_convention_t *current_cconv = NULL;
71 static be_stackorder_t *stackorder;
72 static ir_mode *mode_gp;
73 static ir_mode *mode_flags;
74 static ir_mode *mode_fp;
75 static ir_mode *mode_fp2;
76 //static ir_mode *mode_fp4;
77 static pmap *node_to_stack;
78 static reg_info_t start_mem;
79 static reg_info_t start_g0;
80 static reg_info_t start_g7;
81 static reg_info_t start_sp;
82 static reg_info_t start_fp;
83 static ir_node *frame_base;
84 static size_t start_params_offset;
85 static size_t start_callee_saves_offset;
87 static const arch_register_t *const omit_fp_callee_saves[] = {
88 &sparc_registers[REG_L0],
89 &sparc_registers[REG_L1],
90 &sparc_registers[REG_L2],
91 &sparc_registers[REG_L3],
92 &sparc_registers[REG_L4],
93 &sparc_registers[REG_L5],
94 &sparc_registers[REG_L6],
95 &sparc_registers[REG_L7],
96 &sparc_registers[REG_I0],
97 &sparc_registers[REG_I1],
98 &sparc_registers[REG_I2],
99 &sparc_registers[REG_I3],
100 &sparc_registers[REG_I4],
101 &sparc_registers[REG_I5],
104 static inline bool mode_needs_gp_reg(ir_mode *mode)
106 if (mode_is_int(mode) || mode_is_reference(mode)) {
107 /* we should only see 32bit code */
108 assert(get_mode_size_bits(mode) <= 32);
115 * Create an And that will zero out upper bits.
117 * @param dbgi debug info
118 * @param block the basic block
119 * @param op the original node
120 * @param src_bits number of lower bits that will remain
122 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
126 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
127 } else if (src_bits == 16) {
128 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
129 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
132 panic("zero extension only supported for 8 and 16 bits");
137 * Generate code for a sign extension.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * @param src_bits number of lower bits that will remain
144 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
147 int shift_width = 32 - src_bits;
148 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
149 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
154 * returns true if it is assured, that the upper bits of a node are "clean"
155 * which means for a 16 or 8 bit value, that the upper bits in the register
156 * are 0 for unsigned and a copy of the last significant bit for signed
159 static bool upper_bits_clean(ir_node *node, ir_mode *mode)
161 switch ((ir_opcode)get_irn_opcode(node)) {
163 if (!mode_is_signed(mode)) {
164 return upper_bits_clean(get_And_left(node), mode)
165 || upper_bits_clean(get_And_right(node), mode);
170 return upper_bits_clean(get_binop_left(node), mode)
171 && upper_bits_clean(get_binop_right(node), mode);
174 if (mode_is_signed(mode)) {
175 return false; /* TODO */
177 ir_node *right = get_Shr_right(node);
178 if (is_Const(right)) {
179 ir_tarval *tv = get_Const_tarval(right);
180 long val = get_tarval_long(tv);
181 if (val >= 32 - (long)get_mode_size_bits(mode))
184 return upper_bits_clean(get_Shr_left(node), mode);
188 return upper_bits_clean(get_Shrs_left(node), mode);
191 ir_tarval *tv = get_Const_tarval(node);
192 long val = get_tarval_long(tv);
193 if (mode_is_signed(mode)) {
194 long shifted = val >> (get_mode_size_bits(mode)-1);
195 return shifted == 0 || shifted == -1;
197 unsigned long shifted = (unsigned long)val;
198 shifted >>= get_mode_size_bits(mode)-1;
205 ir_mode *dest_mode = get_irn_mode(node);
206 ir_node *op = get_Conv_op(node);
207 ir_mode *src_mode = get_irn_mode(op);
208 unsigned src_bits = get_mode_size_bits(src_mode);
209 unsigned dest_bits = get_mode_size_bits(dest_mode);
210 /* downconvs are a nop */
211 if (src_bits <= dest_bits)
212 return upper_bits_clean(op, mode);
213 if (dest_bits <= get_mode_size_bits(mode)
214 && mode_is_signed(dest_mode) == mode_is_signed(mode))
220 ir_node *pred = get_Proj_pred(node);
221 switch (get_irn_opcode(pred)) {
223 ir_mode *load_mode = get_Load_mode(pred);
224 unsigned load_bits = get_mode_size_bits(load_mode);
225 unsigned bits = get_mode_size_bits(mode);
226 if (load_bits > bits)
228 if (mode_is_signed(mode) != mode_is_signed(load_mode))
243 * Extend a value to 32 bit signed/unsigned depending on its mode.
245 * @param dbgi debug info
246 * @param block the basic block
247 * @param op the original node
248 * @param orig_mode the original mode of op
250 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
253 int bits = get_mode_size_bits(orig_mode);
256 if (mode_is_signed(orig_mode)) {
257 return gen_sign_extension(dbgi, block, op, bits);
259 return gen_zero_extension(dbgi, block, op, bits);
265 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
266 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
267 influence the significant lower bit at
268 all (for cases where mode < 32bit) */
270 ENUM_BITSET(match_flags_t)
272 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
273 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
274 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
275 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
278 * checks if a node's value can be encoded as a immediate
280 static bool is_imm_encodeable(const ir_node *node)
286 value = get_tarval_long(get_Const_tarval(node));
287 return sparc_is_value_imm_encodeable(value);
290 static bool needs_extension(ir_node *op)
292 ir_mode *mode = get_irn_mode(op);
293 if (get_mode_size_bits(mode) >= get_mode_size_bits(mode_gp))
295 return !upper_bits_clean(op, mode);
299 * Check, if a given node is a Down-Conv, ie. a integer Conv
300 * from a mode with a mode with more bits to a mode with lesser bits.
301 * Moreover, we return only true if the node has not more than 1 user.
303 * @param node the node
304 * @return non-zero if node is a Down-Conv
306 static bool is_downconv(const ir_node *node)
314 src_mode = get_irn_mode(get_Conv_op(node));
315 dest_mode = get_irn_mode(node);
317 mode_needs_gp_reg(src_mode) &&
318 mode_needs_gp_reg(dest_mode) &&
319 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
322 static ir_node *skip_downconv(ir_node *node)
324 while (is_downconv(node)) {
325 node = get_Conv_op(node);
331 * helper function for binop operations
333 * @param new_reg register generation function ptr
334 * @param new_imm immediate generation function ptr
336 static ir_node *gen_helper_binop_args(ir_node *node,
337 ir_node *op1, ir_node *op2,
339 new_binop_reg_func new_reg,
340 new_binop_imm_func new_imm)
342 dbg_info *dbgi = get_irn_dbg_info(node);
343 ir_node *block = be_transform_node(get_nodes_block(node));
349 if (flags & MATCH_MODE_NEUTRAL) {
350 op1 = skip_downconv(op1);
351 op2 = skip_downconv(op2);
353 mode1 = get_irn_mode(op1);
354 mode2 = get_irn_mode(op2);
355 /* we shouldn't see 64bit code */
356 assert(get_mode_size_bits(mode1) <= 32);
357 assert(get_mode_size_bits(mode2) <= 32);
359 if (is_imm_encodeable(op2)) {
360 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
361 new_op1 = be_transform_node(op1);
362 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
363 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
365 return new_imm(dbgi, block, new_op1, NULL, immediate);
367 new_op2 = be_transform_node(op2);
368 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op2)) {
369 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
372 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
373 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
374 return new_imm(dbgi, block, new_op2, NULL, immediate);
377 new_op1 = be_transform_node(op1);
378 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
379 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
381 return new_reg(dbgi, block, new_op1, new_op2);
384 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
385 new_binop_reg_func new_reg,
386 new_binop_imm_func new_imm)
388 ir_node *op1 = get_binop_left(node);
389 ir_node *op2 = get_binop_right(node);
390 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
394 * helper function for FP binop operations
396 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
397 new_binop_fp_func new_func_single,
398 new_binop_fp_func new_func_double,
399 new_binop_fp_func new_func_quad)
401 ir_node *block = be_transform_node(get_nodes_block(node));
402 ir_node *op1 = get_binop_left(node);
403 ir_node *new_op1 = be_transform_node(op1);
404 ir_node *op2 = get_binop_right(node);
405 ir_node *new_op2 = be_transform_node(op2);
406 dbg_info *dbgi = get_irn_dbg_info(node);
407 unsigned bits = get_mode_size_bits(mode);
411 return new_func_single(dbgi, block, new_op1, new_op2, mode);
413 return new_func_double(dbgi, block, new_op1, new_op2, mode);
415 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
419 panic("unsupported mode %+F for float op", mode);
422 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
423 new_unop_fp_func new_func_single,
424 new_unop_fp_func new_func_double,
425 new_unop_fp_func new_func_quad)
427 ir_node *block = be_transform_node(get_nodes_block(node));
428 ir_node *op = get_unop_op(node);
429 ir_node *new_op = be_transform_node(op);
430 dbg_info *dbgi = get_irn_dbg_info(node);
431 unsigned bits = get_mode_size_bits(mode);
435 return new_func_single(dbgi, block, new_op, mode);
437 return new_func_double(dbgi, block, new_op, mode);
439 return new_func_quad(dbgi, block, new_op, mode);
443 panic("unsupported mode %+F for float op", mode);
446 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
447 ir_node *op1, ir_node *flags,
448 ir_entity *imm_entity, int32_t imm);
450 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
451 ir_node *op1, ir_node *op2,
454 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
455 new_binopx_reg_func new_binopx_reg,
456 new_binopx_imm_func new_binopx_imm)
458 dbg_info *dbgi = get_irn_dbg_info(node);
459 ir_node *block = be_transform_node(get_nodes_block(node));
460 ir_node *op1 = get_irn_n(node, 0);
461 ir_node *op2 = get_irn_n(node, 1);
462 ir_node *flags = get_irn_n(node, 2);
463 ir_node *new_flags = be_transform_node(flags);
467 /* only support for mode-neutral implemented so far */
468 assert(match_flags & MATCH_MODE_NEUTRAL);
470 if (is_imm_encodeable(op2)) {
471 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
472 new_op1 = be_transform_node(op1);
473 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
475 new_op2 = be_transform_node(op2);
476 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
477 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
478 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
480 new_op1 = be_transform_node(op1);
481 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
485 static ir_node *get_reg(ir_graph *const irg, reg_info_t *const reg)
488 /* this is already the transformed start node */
489 ir_node *const start = get_irg_start(irg);
490 assert(is_sparc_Start(start));
491 arch_register_class_t const *const cls = arch_get_irn_register_req_out(start, reg->offset)->cls;
492 reg->irn = new_r_Proj(start, cls ? cls->mode : mode_M, reg->offset);
497 static ir_node *get_g0(ir_graph *irg)
499 return get_reg(irg, &start_g0);
502 static ir_node *get_g7(ir_graph *irg)
504 return get_reg(irg, &start_g7);
507 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
508 ir_entity *entity, int32_t offset)
510 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
511 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
515 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
518 if (get_entity_owner(entity) == get_tls_type()) {
519 ir_graph *irg = get_irn_irg(block);
520 ir_node *g7 = get_g7(irg);
521 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
522 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
525 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
526 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
531 typedef struct address_t {
539 * Match a load/store address
541 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
544 ir_node *ptr2 = NULL;
546 ir_entity *entity = NULL;
549 ir_node *add_right = get_Add_right(base);
550 if (is_Const(add_right)) {
551 base = get_Add_left(base);
552 offset += get_tarval_long(get_Const_tarval(add_right));
555 /* Note that we don't match sub(x, Const) or chains of adds/subs
556 * because this should all be normalized by now */
558 /* we only use the symconst if we're the only user otherwise we probably
559 * won't save anything but produce multiple sethi+or combinations with
560 * just different offsets */
561 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
562 ir_entity *sc_entity = get_SymConst_entity(base);
563 dbg_info *dbgi = get_irn_dbg_info(ptr);
564 ir_node *block = get_nodes_block(ptr);
565 ir_node *new_block = be_transform_node(block);
567 if (get_entity_owner(sc_entity) == get_tls_type()) {
571 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
573 base = get_g7(get_irn_irg(base));
577 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
579 } else if (use_ptr2 && is_Add(base) && offset == 0) {
580 ptr2 = be_transform_node(get_Add_right(base));
581 base = be_transform_node(get_Add_left(base));
584 if (sparc_is_value_imm_encodeable(offset)) {
585 base = be_transform_node(base);
587 base = be_transform_node(ptr);
593 address->ptr2 = ptr2;
594 address->entity = entity;
595 address->offset = offset;
599 * Creates an sparc Add.
601 * @param node FIRM node
602 * @return the created sparc Add node
604 static ir_node *gen_Add(ir_node *node)
606 ir_mode *mode = get_irn_mode(node);
609 if (mode_is_float(mode)) {
610 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
611 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
614 /* special case: + 0x1000 can be represented as - 0x1000 */
615 right = get_Add_right(node);
616 if (is_Const(right)) {
617 ir_node *left = get_Add_left(node);
620 /* is this simple address arithmetic? then we can let the linker do
621 * the calculation. */
622 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
623 dbg_info *dbgi = get_irn_dbg_info(node);
624 ir_node *block = be_transform_node(get_nodes_block(node));
627 /* the value of use_ptr2 shouldn't matter here */
628 match_address(node, &address, false);
629 assert(is_sparc_SetHi(address.ptr));
630 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
631 address.entity, address.offset);
634 tv = get_Const_tarval(right);
635 val = get_tarval_long(tv);
637 dbg_info *dbgi = get_irn_dbg_info(node);
638 ir_node *block = be_transform_node(get_nodes_block(node));
639 ir_node *op = get_Add_left(node);
640 ir_node *new_op = be_transform_node(op);
641 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
645 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
646 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
649 static ir_node *gen_AddCC_t(ir_node *node)
651 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
652 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
655 static ir_node *gen_Proj_AddCC_t(ir_node *node)
657 long pn = get_Proj_proj(node);
658 ir_node *pred = get_Proj_pred(node);
659 ir_node *new_pred = be_transform_node(pred);
662 case pn_sparc_AddCC_t_res:
663 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
664 case pn_sparc_AddCC_t_flags:
665 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
667 panic("Invalid proj found");
671 static ir_node *gen_AddX_t(ir_node *node)
673 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
674 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
678 * Creates an sparc Sub.
680 * @param node FIRM node
681 * @return the created sparc Sub node
683 static ir_node *gen_Sub(ir_node *node)
685 ir_mode *mode = get_irn_mode(node);
687 if (mode_is_float(mode)) {
688 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
689 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
692 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
693 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
696 static ir_node *gen_SubCC_t(ir_node *node)
698 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
699 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
702 static ir_node *gen_Proj_SubCC_t(ir_node *node)
704 long pn = get_Proj_proj(node);
705 ir_node *pred = get_Proj_pred(node);
706 ir_node *new_pred = be_transform_node(pred);
709 case pn_sparc_SubCC_t_res:
710 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
711 case pn_sparc_SubCC_t_flags:
712 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
714 panic("Invalid proj found");
718 static ir_node *gen_SubX_t(ir_node *node)
720 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
721 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
724 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
725 ir_node *mem, ir_mode *mode, ir_entity *entity,
726 long offset, bool is_frame_entity)
728 unsigned bits = get_mode_size_bits(mode);
729 assert(mode_is_float(mode));
731 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
732 offset, is_frame_entity);
733 } else if (bits == 64) {
734 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
735 offset, is_frame_entity);
738 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
739 offset, is_frame_entity);
743 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
744 ir_node *ptr, ir_node *mem, ir_mode *mode,
745 ir_entity *entity, long offset,
746 bool is_frame_entity)
748 unsigned bits = get_mode_size_bits(mode);
749 assert(mode_is_float(mode));
751 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
752 offset, is_frame_entity);
753 } else if (bits == 64) {
754 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
755 offset, is_frame_entity);
758 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
759 offset, is_frame_entity);
766 * @param node the ir Load node
767 * @return the created sparc Load node
769 static ir_node *gen_Load(ir_node *node)
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_mode *mode = get_Load_mode(node);
773 ir_node *block = be_transform_node(get_nodes_block(node));
774 ir_node *ptr = get_Load_ptr(node);
775 ir_node *mem = get_Load_mem(node);
776 ir_node *new_mem = be_transform_node(mem);
777 ir_node *new_load = NULL;
780 if (get_Load_unaligned(node) == align_non_aligned) {
781 panic("transformation of unaligned Loads not implemented yet");
784 if (mode_is_float(mode)) {
785 match_address(ptr, &address, false);
786 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
787 address.entity, address.offset, false);
789 match_address(ptr, &address, true);
790 if (address.ptr2 != NULL) {
791 assert(address.entity == NULL && address.offset == 0);
792 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
793 address.ptr2, new_mem, mode);
795 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
796 mode, address.entity, address.offset,
800 set_irn_pinned(new_load, get_irn_pinned(node));
806 * Transforms a Store.
808 * @param node the ir Store node
809 * @return the created sparc Store node
811 static ir_node *gen_Store(ir_node *node)
813 ir_node *block = be_transform_node(get_nodes_block(node));
814 ir_node *ptr = get_Store_ptr(node);
815 ir_node *mem = get_Store_mem(node);
816 ir_node *new_mem = be_transform_node(mem);
817 ir_node *val = get_Store_value(node);
818 ir_mode *mode = get_irn_mode(val);
819 dbg_info *dbgi = get_irn_dbg_info(node);
820 ir_node *new_store = NULL;
823 if (get_Store_unaligned(node) == align_non_aligned) {
824 panic("transformation of unaligned Stores not implemented yet");
827 if (mode_is_float(mode)) {
828 ir_node *new_val = be_transform_node(val);
829 /* TODO: variants with reg+reg address mode */
830 match_address(ptr, &address, false);
831 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
832 mode, address.entity, address.offset, false);
835 unsigned dest_bits = get_mode_size_bits(mode);
836 while (is_downconv(node)
837 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
838 val = get_Conv_op(val);
840 new_val = be_transform_node(val);
842 assert(dest_bits <= 32);
843 match_address(ptr, &address, true);
844 if (address.ptr2 != NULL) {
845 assert(address.entity == NULL && address.offset == 0);
846 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
847 address.ptr2, new_mem, mode);
849 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
850 new_mem, mode, address.entity,
851 address.offset, false);
854 set_irn_pinned(new_store, get_irn_pinned(node));
860 * Creates an sparc Mul.
861 * returns the lower 32bits of the 64bit multiply result
863 * @return the created sparc Mul node
865 static ir_node *gen_Mul(ir_node *node)
867 ir_mode *mode = get_irn_mode(node);
868 if (mode_is_float(mode)) {
869 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
870 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
873 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
874 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
878 * Creates an sparc Mulh.
879 * Mulh returns the upper 32bits of a mul instruction
881 * @return the created sparc Mulh node
883 static ir_node *gen_Mulh(ir_node *node)
885 ir_mode *mode = get_irn_mode(node);
888 if (mode_is_float(mode))
889 panic("FP not supported yet");
891 if (mode_is_signed(mode)) {
892 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
893 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
895 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
896 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
900 static ir_node *gen_sign_extension_value(ir_node *node)
902 ir_node *block = get_nodes_block(node);
903 ir_node *new_block = be_transform_node(block);
904 ir_node *new_node = be_transform_node(node);
905 /* TODO: we could do some shortcuts for some value types probably.
906 * (For constants or other cases where we know the sign bit in
908 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
912 * Creates an sparc Div.
914 * @return the created sparc Div node
916 static ir_node *gen_Div(ir_node *node)
918 dbg_info *dbgi = get_irn_dbg_info(node);
919 ir_node *block = get_nodes_block(node);
920 ir_node *new_block = be_transform_node(block);
921 ir_mode *mode = get_Div_resmode(node);
922 ir_node *left = get_Div_left(node);
923 ir_node *left_low = be_transform_node(left);
924 ir_node *right = get_Div_right(node);
927 if (mode_is_float(mode)) {
928 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
929 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
932 if (mode_is_signed(mode)) {
933 ir_node *left_high = gen_sign_extension_value(left);
935 if (is_imm_encodeable(right)) {
936 int32_t immediate = get_tarval_long(get_Const_tarval(right));
937 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
940 ir_node *new_right = be_transform_node(right);
941 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
945 ir_graph *irg = get_irn_irg(node);
946 ir_node *left_high = get_g0(irg);
947 if (is_imm_encodeable(right)) {
948 int32_t immediate = get_tarval_long(get_Const_tarval(right));
949 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
952 ir_node *new_right = be_transform_node(right);
953 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
962 * Transforms a Not node.
964 * @return the created sparc Not node
966 static ir_node *gen_Not(ir_node *node)
968 ir_node *op = get_Not_op(node);
969 ir_graph *irg = get_irn_irg(node);
970 ir_node *zero = get_g0(irg);
971 dbg_info *dbgi = get_irn_dbg_info(node);
972 ir_node *block = be_transform_node(get_nodes_block(node));
973 ir_node *new_op = be_transform_node(op);
975 /* Note: Not(Eor()) is normalize in firm localopts already so
976 * we don't match it for xnor here */
978 /* Not can be represented with xnor 0, n */
979 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
982 static ir_node *gen_helper_bitop(ir_node *node,
983 new_binop_reg_func new_reg,
984 new_binop_imm_func new_imm,
985 new_binop_reg_func new_not_reg,
986 new_binop_imm_func new_not_imm,
989 ir_node *op1 = get_binop_left(node);
990 ir_node *op2 = get_binop_right(node);
992 return gen_helper_binop_args(node, op2, get_Not_op(op1),
994 new_not_reg, new_not_imm);
997 return gen_helper_binop_args(node, op1, get_Not_op(op2),
999 new_not_reg, new_not_imm);
1001 if (is_Const(op2) && get_irn_n_edges(op2) == 1) {
1002 ir_tarval *tv = get_Const_tarval(op2);
1003 long value = get_tarval_long(tv);
1004 if (!sparc_is_value_imm_encodeable(value)) {
1005 long notvalue = ~value;
1006 if ((notvalue & 0x3ff) == 0) {
1007 ir_node *block = get_nodes_block(node);
1008 ir_node *new_block = be_transform_node(block);
1009 dbg_info *dbgi = get_irn_dbg_info(node);
1011 = new_bd_sparc_SetHi(NULL, new_block, NULL, notvalue);
1012 ir_node *new_op1 = be_transform_node(op1);
1014 = new_not_reg(dbgi, new_block, new_op1, new_op2);
1019 return gen_helper_binop_args(node, op1, op2,
1020 flags | MATCH_COMMUTATIVE,
1024 static ir_node *gen_And(ir_node *node)
1026 return gen_helper_bitop(node,
1027 new_bd_sparc_And_reg,
1028 new_bd_sparc_And_imm,
1029 new_bd_sparc_AndN_reg,
1030 new_bd_sparc_AndN_imm,
1031 MATCH_MODE_NEUTRAL);
1034 static ir_node *gen_Or(ir_node *node)
1036 return gen_helper_bitop(node,
1037 new_bd_sparc_Or_reg,
1038 new_bd_sparc_Or_imm,
1039 new_bd_sparc_OrN_reg,
1040 new_bd_sparc_OrN_imm,
1041 MATCH_MODE_NEUTRAL);
1044 static ir_node *gen_Eor(ir_node *node)
1046 return gen_helper_bitop(node,
1047 new_bd_sparc_Xor_reg,
1048 new_bd_sparc_Xor_imm,
1049 new_bd_sparc_XNor_reg,
1050 new_bd_sparc_XNor_imm,
1051 MATCH_MODE_NEUTRAL);
1054 static ir_node *gen_Shl(ir_node *node)
1056 ir_mode *mode = get_irn_mode(node);
1057 if (get_mode_modulo_shift(mode) != 32)
1058 panic("modulo_shift!=32 not supported");
1059 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
1062 static ir_node *gen_Shr(ir_node *node)
1064 ir_mode *mode = get_irn_mode(node);
1065 if (get_mode_modulo_shift(mode) != 32)
1066 panic("modulo_shift!=32 not supported");
1067 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
1070 static ir_node *gen_Shrs(ir_node *node)
1072 ir_mode *mode = get_irn_mode(node);
1073 if (get_mode_modulo_shift(mode) != 32)
1074 panic("modulo_shift!=32 not supported");
1075 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
1079 * Transforms a Minus node.
1081 static ir_node *gen_Minus(ir_node *node)
1083 ir_mode *mode = get_irn_mode(node);
1090 if (mode_is_float(mode)) {
1091 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
1092 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
1094 block = be_transform_node(get_nodes_block(node));
1095 dbgi = get_irn_dbg_info(node);
1096 op = get_Minus_op(node);
1097 new_op = be_transform_node(op);
1098 zero = get_g0(get_irn_irg(node));
1099 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1103 * Create an entity for a given (floating point) tarval
1105 static ir_entity *create_float_const_entity(ir_tarval *tv)
1107 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
1108 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1109 ir_entity *entity = pmap_get(ir_entity, isa->constants, tv);
1110 ir_initializer_t *initializer;
1118 mode = get_tarval_mode(tv);
1119 type = get_type_for_mode(mode);
1120 glob = get_glob_type();
1121 entity = new_entity(glob, id_unique("C%u"), type);
1122 set_entity_visibility(entity, ir_visibility_private);
1123 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1125 initializer = create_initializer_tarval(tv);
1126 set_entity_initializer(entity, initializer);
1128 pmap_insert(isa->constants, tv, entity);
1132 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1134 ir_entity *entity = create_float_const_entity(tv);
1135 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1136 ir_node *mem = get_irg_no_mem(current_ir_graph);
1137 ir_mode *mode = get_tarval_mode(tv);
1139 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1140 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1142 set_irn_pinned(new_op, op_pin_state_floats);
1146 static ir_node *create_int_const(ir_node *block, int32_t value)
1149 ir_graph *irg = get_irn_irg(block);
1151 } else if (sparc_is_value_imm_encodeable(value)) {
1152 ir_graph *irg = get_irn_irg(block);
1153 return new_bd_sparc_Or_imm(NULL, block, get_g0(irg), NULL, value);
1155 ir_node *hi = new_bd_sparc_SetHi(NULL, block, NULL, value);
1156 if ((value & 0x3ff) != 0) {
1157 return new_bd_sparc_Or_imm(NULL, block, hi, NULL, value & 0x3ff);
1164 static ir_node *gen_Const(ir_node *node)
1166 ir_node *block = be_transform_node(get_nodes_block(node));
1167 ir_mode *mode = get_irn_mode(node);
1168 dbg_info *dbgi = get_irn_dbg_info(node);
1169 ir_tarval *tv = get_Const_tarval(node);
1172 if (mode_is_float(mode)) {
1173 return gen_float_const(dbgi, block, tv);
1176 assert(get_mode_size_bits(get_tarval_mode(tv)) <= 32);
1177 val = (int32_t)get_tarval_long(tv);
1178 return create_int_const(block, val);
1181 static ir_node *gen_Switch(ir_node *node)
1183 dbg_info *dbgi = get_irn_dbg_info(node);
1184 ir_node *block = get_nodes_block(node);
1185 ir_node *new_block = be_transform_node(block);
1186 ir_graph *irg = get_irn_irg(block);
1187 ir_node *selector = get_Switch_selector(node);
1188 ir_node *new_selector = be_transform_node(selector);
1189 const ir_switch_table *table = get_Switch_table(node);
1190 unsigned n_outs = get_Switch_n_outs(node);
1192 ir_node *table_address;
1197 table = ir_switch_table_duplicate(irg, table);
1199 /* switch with smaller mode not implemented yet */
1200 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1202 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1203 set_entity_visibility(entity, ir_visibility_private);
1204 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1206 /* construct base address */
1207 table_address = make_address(dbgi, new_block, entity, 0);
1209 idx = new_bd_sparc_Sll_imm(dbgi, new_block, new_selector, NULL, 2);
1210 /* load from jumptable */
1211 load = new_bd_sparc_Ld_reg(dbgi, new_block, table_address, idx,
1212 get_irg_no_mem(current_ir_graph),
1214 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1216 return new_bd_sparc_SwitchJmp(dbgi, new_block, address, n_outs, table, entity);
1219 static ir_node *gen_Cond(ir_node *node)
1221 ir_node *selector = get_Cond_selector(node);
1226 ir_relation relation;
1229 /* note: after lower_mode_b we are guaranteed to have a Cmp input */
1230 block = be_transform_node(get_nodes_block(node));
1231 dbgi = get_irn_dbg_info(node);
1232 cmp_left = get_Cmp_left(selector);
1233 cmp_mode = get_irn_mode(cmp_left);
1234 flag_node = be_transform_node(selector);
1235 relation = get_Cmp_relation(selector);
1236 if (mode_is_float(cmp_mode)) {
1237 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1239 bool is_unsigned = !mode_is_signed(cmp_mode);
1240 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1247 static ir_node *gen_Cmp(ir_node *node)
1249 ir_node *op1 = get_Cmp_left(node);
1250 ir_node *op2 = get_Cmp_right(node);
1251 ir_mode *cmp_mode = get_irn_mode(op1);
1252 assert(get_irn_mode(op2) == cmp_mode);
1254 if (mode_is_float(cmp_mode)) {
1255 ir_node *block = be_transform_node(get_nodes_block(node));
1256 dbg_info *dbgi = get_irn_dbg_info(node);
1257 ir_node *new_op1 = be_transform_node(op1);
1258 ir_node *new_op2 = be_transform_node(op2);
1259 unsigned bits = get_mode_size_bits(cmp_mode);
1261 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1262 } else if (bits == 64) {
1263 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1265 assert(bits == 128);
1266 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1270 /* when we compare a bitop like and,or,... with 0 then we can directly use
1271 * the bitopcc variant.
1272 * Currently we only do this when we're the only user of the node...
1274 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1276 return gen_helper_bitop(op1,
1277 new_bd_sparc_AndCCZero_reg,
1278 new_bd_sparc_AndCCZero_imm,
1279 new_bd_sparc_AndNCCZero_reg,
1280 new_bd_sparc_AndNCCZero_imm,
1282 } else if (is_Or(op1)) {
1283 return gen_helper_bitop(op1,
1284 new_bd_sparc_OrCCZero_reg,
1285 new_bd_sparc_OrCCZero_imm,
1286 new_bd_sparc_OrNCCZero_reg,
1287 new_bd_sparc_OrNCCZero_imm,
1289 } else if (is_Eor(op1)) {
1290 return gen_helper_bitop(op1,
1291 new_bd_sparc_XorCCZero_reg,
1292 new_bd_sparc_XorCCZero_imm,
1293 new_bd_sparc_XNorCCZero_reg,
1294 new_bd_sparc_XNorCCZero_imm,
1296 } else if (is_Add(op1)) {
1297 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1298 new_bd_sparc_AddCCZero_reg,
1299 new_bd_sparc_AddCCZero_imm);
1300 } else if (is_Sub(op1)) {
1301 return gen_helper_binop(op1, MATCH_NONE,
1302 new_bd_sparc_SubCCZero_reg,
1303 new_bd_sparc_SubCCZero_imm);
1304 } else if (is_Mul(op1)) {
1305 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1306 new_bd_sparc_MulCCZero_reg,
1307 new_bd_sparc_MulCCZero_imm);
1311 /* integer compare */
1312 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1313 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1317 * Transforms a SymConst node.
1319 static ir_node *gen_SymConst(ir_node *node)
1321 ir_entity *entity = get_SymConst_entity(node);
1322 dbg_info *dbgi = get_irn_dbg_info(node);
1323 ir_node *block = get_nodes_block(node);
1324 ir_node *new_block = be_transform_node(block);
1325 return make_address(dbgi, new_block, entity, 0);
1328 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1329 ir_mode *src_mode, ir_mode *dst_mode)
1331 unsigned src_bits = get_mode_size_bits(src_mode);
1332 unsigned dst_bits = get_mode_size_bits(dst_mode);
1333 if (src_bits == 32) {
1334 if (dst_bits == 64) {
1335 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1337 assert(dst_bits == 128);
1338 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1340 } else if (src_bits == 64) {
1341 if (dst_bits == 32) {
1342 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1344 assert(dst_bits == 128);
1345 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1348 assert(src_bits == 128);
1349 if (dst_bits == 32) {
1350 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1352 assert(dst_bits == 64);
1353 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1358 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1362 unsigned bits = get_mode_size_bits(src_mode);
1364 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1365 } else if (bits == 64) {
1366 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1368 assert(bits == 128);
1369 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1373 ir_graph *irg = get_irn_irg(block);
1374 ir_node *sp = get_irg_frame(irg);
1375 ir_node *nomem = get_irg_no_mem(irg);
1376 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, mode_fp,
1378 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1380 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1381 set_irn_pinned(stf, op_pin_state_floats);
1382 set_irn_pinned(ld, op_pin_state_floats);
1387 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1390 ir_graph *irg = get_irn_irg(block);
1391 ir_node *sp = get_irg_frame(irg);
1392 ir_node *nomem = get_irg_no_mem(irg);
1393 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1394 mode_gp, NULL, 0, true);
1395 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1397 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1398 unsigned bits = get_mode_size_bits(dst_mode);
1399 set_irn_pinned(st, op_pin_state_floats);
1400 set_irn_pinned(ldf, op_pin_state_floats);
1403 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1404 } else if (bits == 64) {
1405 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1407 assert(bits == 128);
1408 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1412 static ir_node *gen_Conv(ir_node *node)
1414 ir_node *block = be_transform_node(get_nodes_block(node));
1415 ir_node *op = get_Conv_op(node);
1416 ir_mode *src_mode = get_irn_mode(op);
1417 ir_mode *dst_mode = get_irn_mode(node);
1418 dbg_info *dbgi = get_irn_dbg_info(node);
1421 int src_bits = get_mode_size_bits(src_mode);
1422 int dst_bits = get_mode_size_bits(dst_mode);
1424 if (src_mode == mode_b)
1425 panic("ConvB not lowered %+F", node);
1427 if (src_mode == dst_mode)
1428 return be_transform_node(op);
1430 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1431 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1433 new_op = be_transform_node(op);
1434 if (mode_is_float(src_mode)) {
1435 if (mode_is_float(dst_mode)) {
1436 /* float -> float conv */
1437 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1439 /* float -> int conv */
1440 if (!mode_is_signed(dst_mode))
1441 panic("float to unsigned not lowered");
1442 return create_ftoi(dbgi, block, new_op, src_mode);
1445 /* int -> float conv */
1446 if (src_bits < 32) {
1447 new_op = gen_extension(dbgi, block, new_op, src_mode);
1448 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1449 panic("unsigned to float not lowered!");
1451 return create_itof(dbgi, block, new_op, dst_mode);
1453 } else { /* complete in gp registers */
1457 if (src_bits == dst_bits || dst_mode == mode_b) {
1458 /* kill unnecessary conv */
1459 return be_transform_node(op);
1462 if (src_bits < dst_bits) {
1463 min_bits = src_bits;
1464 min_mode = src_mode;
1466 min_bits = dst_bits;
1467 min_mode = dst_mode;
1470 if (upper_bits_clean(op, min_mode)) {
1471 return be_transform_node(op);
1473 new_op = be_transform_node(op);
1475 if (mode_is_signed(min_mode)) {
1476 return gen_sign_extension(dbgi, block, new_op, min_bits);
1478 return gen_zero_extension(dbgi, block, new_op, min_bits);
1483 static ir_node *gen_Unknown(ir_node *node)
1485 /* just produce a 0 */
1486 ir_mode *mode = get_irn_mode(node);
1487 if (mode_is_float(mode)) {
1488 ir_node *block = be_transform_node(get_nodes_block(node));
1489 return gen_float_const(NULL, block, get_mode_null(mode));
1490 } else if (mode_needs_gp_reg(mode)) {
1491 ir_graph *irg = get_irn_irg(node);
1495 panic("Unexpected Unknown mode");
1499 * transform the start node to the prolog code
1501 static ir_node *gen_Start(ir_node *node)
1503 ir_graph *irg = get_irn_irg(node);
1504 ir_entity *entity = get_irg_entity(irg);
1505 ir_type *function_type = get_entity_type(entity);
1506 ir_node *block = get_nodes_block(node);
1507 ir_node *new_block = be_transform_node(block);
1508 dbg_info *dbgi = get_irn_dbg_info(node);
1509 struct obstack *obst = be_get_be_obst(irg);
1510 const arch_register_req_t *req;
1516 /* start building list of start constraints */
1517 assert(obstack_object_size(obst) == 0);
1519 /* calculate number of outputs */
1520 n_outs = 4; /* memory, g0, g7, sp */
1521 if (!current_cconv->omit_fp)
1522 ++n_outs; /* framepointer */
1523 /* function parameters */
1524 n_outs += current_cconv->n_param_regs;
1526 if (current_cconv->omit_fp) {
1527 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1530 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1534 /* first output is memory */
1535 start_mem.offset = o;
1536 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1539 /* the zero register */
1540 start_g0.offset = o;
1541 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1542 arch_register_req_type_ignore);
1543 arch_set_irn_register_req_out(start, o, req);
1544 arch_set_irn_register_out(start, o, &sparc_registers[REG_G0]);
1547 /* g7 is used for TLS data */
1548 start_g7.offset = o;
1549 req = be_create_reg_req(obst, &sparc_registers[REG_G7],
1550 arch_register_req_type_ignore);
1551 arch_set_irn_register_req_out(start, o, req);
1552 arch_set_irn_register_out(start, o, &sparc_registers[REG_G7]);
1555 /* we need an output for the stackpointer */
1556 start_sp.offset = o;
1557 req = be_create_reg_req(obst, sp_reg,
1558 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1559 arch_set_irn_register_req_out(start, o, req);
1560 arch_set_irn_register_out(start, o, sp_reg);
1563 if (!current_cconv->omit_fp) {
1564 start_fp.offset = o;
1565 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1566 arch_set_irn_register_req_out(start, o, req);
1567 arch_set_irn_register_out(start, o, fp_reg);
1571 /* function parameters in registers */
1572 start_params_offset = o;
1573 for (i = 0; i < get_method_n_params(function_type); ++i) {
1574 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1575 const arch_register_t *reg0 = param->reg0;
1576 const arch_register_t *reg1 = param->reg1;
1578 arch_set_irn_register_req_out(start, o, reg0->single_req);
1579 arch_set_irn_register_out(start, o, reg0);
1583 arch_set_irn_register_req_out(start, o, reg1->single_req);
1584 arch_set_irn_register_out(start, o, reg1);
1588 /* we need the values of the callee saves (Note: non omit-fp mode has no
1590 start_callee_saves_offset = o;
1591 if (current_cconv->omit_fp) {
1592 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1594 for (c = 0; c < n_callee_saves; ++c) {
1595 const arch_register_t *reg = omit_fp_callee_saves[c];
1596 arch_set_irn_register_req_out(start, o, reg->single_req);
1597 arch_set_irn_register_out(start, o, reg);
1601 assert(n_outs == o);
1606 static ir_node *get_initial_sp(ir_graph *irg)
1608 return get_reg(irg, &start_sp);
1611 static ir_node *get_initial_fp(ir_graph *irg)
1613 return get_reg(irg, &start_fp);
1616 static ir_node *get_initial_mem(ir_graph *irg)
1618 return get_reg(irg, &start_mem);
1621 static ir_node *get_stack_pointer_for(ir_node *node)
1623 /* get predecessor in stack_order list */
1624 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1627 if (stack_pred == NULL) {
1628 /* first stack user in the current block. We can simply use the
1629 * initial sp_proj for it */
1630 ir_graph *irg = get_irn_irg(node);
1631 return get_initial_sp(irg);
1634 be_transform_node(stack_pred);
1635 stack = pmap_get(ir_node, node_to_stack, stack_pred);
1636 if (stack == NULL) {
1637 return get_stack_pointer_for(stack_pred);
1644 * transform a Return node into epilogue code + return statement
1646 static ir_node *gen_Return(ir_node *node)
1648 ir_node *block = get_nodes_block(node);
1649 ir_graph *irg = get_irn_irg(node);
1650 ir_node *new_block = be_transform_node(block);
1651 dbg_info *dbgi = get_irn_dbg_info(node);
1652 ir_node *mem = get_Return_mem(node);
1653 ir_node *new_mem = be_transform_node(mem);
1654 ir_node *sp = get_stack_pointer_for(node);
1655 size_t n_res = get_Return_n_ress(node);
1656 struct obstack *be_obst = be_get_be_obst(irg);
1659 const arch_register_req_t **reqs;
1664 /* estimate number of return values */
1665 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1666 if (current_cconv->omit_fp)
1667 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1669 in = ALLOCAN(ir_node*, n_ins);
1670 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1674 reqs[p] = arch_no_register_req;
1678 reqs[p] = sp_reg->single_req;
1682 for (i = 0; i < n_res; ++i) {
1683 ir_node *res_value = get_Return_res(node, i);
1684 ir_node *new_res_value = be_transform_node(res_value);
1685 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1686 assert(slot->req1 == NULL);
1687 in[p] = new_res_value;
1688 reqs[p] = slot->req0;
1692 if (current_cconv->omit_fp) {
1693 ir_node *start = get_irg_start(irg);
1694 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1695 for (i = 0; i < n_callee_saves; ++i) {
1696 const arch_register_t *reg = omit_fp_callee_saves[i];
1697 ir_mode *mode = reg->reg_class->mode;
1699 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1701 reqs[p] = reg->single_req;
1707 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1708 arch_set_irn_register_reqs_in(bereturn, reqs);
1713 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1714 ir_node *value0, ir_node *value1)
1716 ir_graph *irg = current_ir_graph;
1717 ir_node *sp = get_irg_frame(irg);
1718 ir_node *nomem = get_irg_no_mem(irg);
1719 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1720 mode_gp, NULL, 0, true);
1724 set_irn_pinned(st, op_pin_state_floats);
1726 if (value1 != NULL) {
1727 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1728 mode_gp, NULL, 4, true);
1729 ir_node *in[2] = { st, st1 };
1730 ir_node *sync = new_r_Sync(block, 2, in);
1731 set_irn_pinned(st1, op_pin_state_floats);
1739 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1740 set_irn_pinned(ldf, op_pin_state_floats);
1742 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1745 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1746 ir_node *value, ir_mode *float_mode,
1749 int bits = get_mode_size_bits(float_mode);
1750 if (is_Const(value)) {
1751 ir_tarval *tv = get_Const_tarval(value);
1752 int32_t val = get_tarval_sub_bits(tv, 0) |
1753 (get_tarval_sub_bits(tv, 1) << 8) |
1754 (get_tarval_sub_bits(tv, 2) << 16) |
1755 (get_tarval_sub_bits(tv, 3) << 24);
1756 ir_node *valc = create_int_const(block, val);
1758 int32_t val2 = get_tarval_sub_bits(tv, 4) |
1759 (get_tarval_sub_bits(tv, 5) << 8) |
1760 (get_tarval_sub_bits(tv, 6) << 16) |
1761 (get_tarval_sub_bits(tv, 7) << 24);
1762 ir_node *valc2 = create_int_const(block, val2);
1771 ir_graph *irg = current_ir_graph;
1772 ir_node *stack = get_irg_frame(irg);
1773 ir_node *nomem = get_irg_no_mem(irg);
1774 ir_node *new_value = be_transform_node(value);
1775 ir_node *stf = create_stf(dbgi, block, new_value, stack, nomem,
1776 float_mode, NULL, 0, true);
1778 set_irn_pinned(stf, op_pin_state_floats);
1780 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1781 set_irn_pinned(ld, op_pin_state_floats);
1782 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1785 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1787 set_irn_pinned(ld, op_pin_state_floats);
1788 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1790 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1791 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1799 static ir_node *gen_Call(ir_node *node)
1801 ir_graph *irg = get_irn_irg(node);
1802 ir_node *callee = get_Call_ptr(node);
1803 ir_node *block = get_nodes_block(node);
1804 ir_node *new_block = be_transform_node(block);
1805 ir_node *mem = get_Call_mem(node);
1806 ir_node *new_mem = be_transform_node(mem);
1807 dbg_info *dbgi = get_irn_dbg_info(node);
1808 ir_type *type = get_Call_type(node);
1809 size_t n_params = get_Call_n_params(node);
1810 size_t n_ress = get_method_n_ress(type);
1811 /* max inputs: memory, callee, register arguments */
1812 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1813 struct obstack *obst = be_get_be_obst(irg);
1814 calling_convention_t *cconv
1815 = sparc_decide_calling_convention(type, NULL);
1816 size_t n_param_regs = cconv->n_param_regs;
1817 /* param-regs + mem + stackpointer + callee */
1818 unsigned max_inputs = 3 + n_param_regs;
1819 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1820 const arch_register_req_t **in_req
1821 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1825 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1826 ir_entity *entity = NULL;
1827 ir_node *new_frame = get_stack_pointer_for(node);
1828 bool aggregate_return
1829 = get_method_calling_convention(type) & cc_compound_ret;
1839 assert(n_params == get_method_n_params(type));
1841 /* construct arguments */
1844 in_req[in_arity] = arch_no_register_req;
1848 /* stack pointer input */
1849 /* construct an IncSP -> we have to always be sure that the stack is
1850 * aligned even if we don't push arguments on it */
1851 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1852 cconv->param_stack_size, 1);
1853 in_req[in_arity] = sp_reg->single_req;
1854 in[in_arity] = incsp;
1858 for (p = 0; p < n_params; ++p) {
1859 ir_node *value = get_Call_param(node, p);
1860 const reg_or_stackslot_t *param = &cconv->parameters[p];
1861 ir_type *param_type = get_method_param_type(type, p);
1862 ir_mode *mode = get_type_mode(param_type);
1863 ir_node *partial_value;
1864 ir_node *new_values[2];
1868 if (mode_is_float(mode) && param->reg0 != NULL) {
1869 unsigned size_bits = get_mode_size_bits(mode);
1870 assert(size_bits <= 64);
1871 bitcast_float_to_int(dbgi, new_block, value, mode, new_values);
1873 ir_node *new_value = be_transform_node(value);
1874 new_values[0] = new_value;
1875 new_values[1] = NULL;
1878 /* put value into registers */
1879 if (param->reg0 != NULL) {
1880 in[in_arity] = new_values[0];
1881 in_req[in_arity] = param->reg0->single_req;
1883 if (new_values[1] == NULL)
1886 if (param->reg1 != NULL) {
1887 assert(new_values[1] != NULL);
1888 in[in_arity] = new_values[1];
1889 in_req[in_arity] = param->reg1->single_req;
1894 /* we need a store if we're here */
1895 if (new_values[1] != NULL) {
1896 partial_value = new_values[1];
1899 partial_value = new_values[0];
1902 /* we need to skip over our save area when constructing the call
1903 * arguments on stack */
1904 offset = param->offset + SPARC_MIN_STACKSIZE;
1906 if (mode_is_float(mode)) {
1907 str = create_stf(dbgi, new_block, partial_value, incsp, new_mem,
1908 mode, NULL, offset, true);
1910 str = new_bd_sparc_St_imm(dbgi, new_block, partial_value, incsp,
1911 new_mem, mode, NULL, offset, true);
1913 set_irn_pinned(str, op_pin_state_floats);
1914 sync_ins[sync_arity++] = str;
1917 /* construct memory input */
1918 if (sync_arity == 0) {
1919 in[mem_pos] = new_mem;
1920 } else if (sync_arity == 1) {
1921 in[mem_pos] = sync_ins[0];
1923 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1926 if (is_SymConst(callee)) {
1927 entity = get_SymConst_entity(callee);
1929 in[in_arity] = be_transform_node(callee);
1930 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1933 assert(in_arity <= (int)max_inputs);
1940 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1942 /* create call node */
1943 if (entity != NULL) {
1944 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1945 entity, 0, aggregate_return);
1947 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1950 arch_set_irn_register_reqs_in(res, in_req);
1952 /* create output register reqs */
1954 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1955 /* add register requirements for the result regs */
1956 for (r = 0; r < n_ress; ++r) {
1957 const reg_or_stackslot_t *result_info = &cconv->results[r];
1958 const arch_register_req_t *req = result_info->req0;
1960 arch_set_irn_register_req_out(res, o++, req);
1962 assert(result_info->req1 == NULL);
1964 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1965 const arch_register_t *reg;
1966 if (!rbitset_is_set(cconv->caller_saves, i))
1968 reg = &sparc_registers[i];
1969 arch_set_irn_register_req_out(res, o++, reg->single_req);
1971 assert(o == out_arity);
1973 /* copy pinned attribute */
1974 set_irn_pinned(res, get_irn_pinned(node));
1976 /* IncSP to destroy the call stackframe */
1977 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1978 /* if we are the last IncSP producer in a block then we have to keep
1980 * Note: This here keeps all producers which is more than necessary */
1981 add_irn_dep(incsp, res);
1984 pmap_insert(node_to_stack, node, incsp);
1986 sparc_free_calling_convention(cconv);
1990 static ir_node *gen_Sel(ir_node *node)
1992 dbg_info *dbgi = get_irn_dbg_info(node);
1993 ir_node *block = get_nodes_block(node);
1994 ir_node *new_block = be_transform_node(block);
1995 ir_node *ptr = get_Sel_ptr(node);
1996 ir_node *new_ptr = be_transform_node(ptr);
1997 ir_entity *entity = get_Sel_entity(node);
1999 /* must be the frame pointer all other sels must have been lowered
2001 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
2003 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
2006 static ir_node *gen_Alloc(ir_node *node)
2008 dbg_info *dbgi = get_irn_dbg_info(node);
2009 ir_node *block = get_nodes_block(node);
2010 ir_node *new_block = be_transform_node(block);
2011 ir_type *type = get_Alloc_type(node);
2012 ir_node *size = get_Alloc_count(node);
2013 ir_node *stack_pred = get_stack_pointer_for(node);
2014 ir_node *mem = get_Alloc_mem(node);
2015 ir_node *new_mem = be_transform_node(mem);
2018 if (get_Alloc_where(node) != stack_alloc)
2019 panic("only stack-alloc supported in sparc backend (at %+F)", node);
2020 /* lowerer should have transformed all allocas to byte size */
2021 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
2022 panic("Found non-byte alloc in sparc backend (at %+F)", node);
2024 if (is_Const(size)) {
2025 ir_tarval *tv = get_Const_tarval(size);
2026 long sizel = get_tarval_long(tv);
2028 assert((sizel & (SPARC_STACK_ALIGNMENT - 1)) == 0 && "Found Alloc with misaligned constant");
2029 subsp = new_bd_sparc_SubSP_imm(dbgi, new_block, stack_pred, new_mem, NULL, sizel);
2031 ir_node *new_size = be_transform_node(size);
2032 subsp = new_bd_sparc_SubSP_reg(dbgi, new_block, stack_pred, new_size, new_mem);
2035 ir_node *stack_proj = new_r_Proj(subsp, mode_gp, pn_sparc_SubSP_stack);
2036 arch_set_irn_register(stack_proj, sp_reg);
2037 /* If we are the last stack producer in a block, we have to keep the
2038 * stack value. This keeps all producers, which is more than necessary. */
2039 keep_alive(stack_proj);
2041 pmap_insert(node_to_stack, node, stack_proj);
2046 static ir_node *gen_Proj_Alloc(ir_node *node)
2048 ir_node *alloc = get_Proj_pred(node);
2049 ir_node *new_alloc = be_transform_node(alloc);
2050 long pn = get_Proj_proj(node);
2052 switch ((pn_Alloc)pn) {
2054 return new_r_Proj(new_alloc, mode_M, pn_sparc_SubSP_M);
2055 case pn_Alloc_res: {
2056 ir_node *addr_proj = new_r_Proj(new_alloc, mode_gp, pn_sparc_SubSP_addr);
2057 arch_set_irn_register(addr_proj, arch_get_irn_register(node));
2060 case pn_Alloc_X_regular:
2061 case pn_Alloc_X_except:
2062 panic("exception output of alloc not supported (at %+F)",
2065 panic("invalid Proj->Alloc");
2068 static ir_node *gen_Free(ir_node *node)
2070 dbg_info *dbgi = get_irn_dbg_info(node);
2071 ir_node *block = get_nodes_block(node);
2072 ir_node *new_block = be_transform_node(block);
2073 ir_type *type = get_Free_type(node);
2074 ir_node *size = get_Free_count(node);
2075 ir_node *mem = get_Free_mem(node);
2076 ir_node *new_mem = be_transform_node(mem);
2077 ir_node *stack_pred = get_stack_pointer_for(node);
2079 if (get_Alloc_where(node) != stack_alloc)
2080 panic("only stack-alloc supported in sparc backend (at %+F)", node);
2081 /* lowerer should have transformed all allocas to byte size */
2082 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
2083 panic("Found non-byte alloc in sparc backend (at %+F)", node);
2085 if (is_Const(size)) {
2086 ir_tarval *tv = get_Const_tarval(size);
2087 long sizel = get_tarval_long(tv);
2088 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
2089 set_irn_dbg_info(addsp, dbgi);
2091 ir_node *new_size = be_transform_node(size);
2092 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
2093 arch_set_irn_register(addsp, sp_reg);
2096 /* if we are the last IncSP producer in a block then we have to keep
2098 * Note: This here keeps all producers which is more than necessary */
2101 pmap_insert(node_to_stack, node, addsp);
2102 /* the "result" is the unmodified sp value */
2106 static const arch_register_req_t float1_req = {
2107 arch_register_req_type_normal,
2108 &sparc_reg_classes[CLASS_sparc_fp],
2114 static const arch_register_req_t float2_req = {
2115 arch_register_req_type_normal | arch_register_req_type_aligned,
2116 &sparc_reg_classes[CLASS_sparc_fp],
2122 static const arch_register_req_t float4_req = {
2123 arch_register_req_type_normal | arch_register_req_type_aligned,
2124 &sparc_reg_classes[CLASS_sparc_fp],
2132 static const arch_register_req_t *get_float_req(ir_mode *mode)
2134 assert(mode_is_float(mode));
2135 switch (get_mode_size_bits(mode)) {
2136 case 32: return &float1_req;
2137 case 64: return &float2_req;
2138 case 128: return &float4_req;
2139 default: panic("invalid float mode");
2144 * Transform some Phi nodes
2146 static ir_node *gen_Phi(ir_node *node)
2148 const arch_register_req_t *req;
2149 ir_node *block = be_transform_node(get_nodes_block(node));
2150 ir_graph *irg = current_ir_graph;
2151 dbg_info *dbgi = get_irn_dbg_info(node);
2152 ir_mode *mode = get_irn_mode(node);
2155 if (mode_needs_gp_reg(mode)) {
2156 /* we shouldn't have any 64bit stuff around anymore */
2157 assert(get_mode_size_bits(mode) <= 32);
2158 /* all integer operations are on 32bit registers now */
2160 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2161 } else if (mode_is_float(mode)) {
2162 req = get_float_req(mode);
2164 req = arch_no_register_req;
2167 /* phi nodes allow loops, so we use the old arguments for now
2168 * and fix this later */
2169 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2170 copy_node_attr(irg, node, phi);
2171 be_duplicate_deps(node, phi);
2172 arch_set_irn_register_req_out(phi, 0, req);
2173 be_enqueue_preds(node);
2178 * Transform a Proj from a Load.
2180 static ir_node *gen_Proj_Load(ir_node *node)
2182 ir_node *load = get_Proj_pred(node);
2183 ir_node *new_load = be_transform_node(load);
2184 dbg_info *dbgi = get_irn_dbg_info(node);
2185 long pn = get_Proj_proj(node);
2187 /* renumber the proj */
2188 switch (get_sparc_irn_opcode(new_load)) {
2190 /* handle all gp loads equal: they have the same proj numbers. */
2191 if (pn == pn_Load_res) {
2192 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2193 } else if (pn == pn_Load_M) {
2194 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2198 if (pn == pn_Load_res) {
2199 const sparc_load_store_attr_t *attr
2200 = get_sparc_load_store_attr_const(new_load);
2201 ir_mode *mode = attr->load_store_mode;
2202 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2203 } else if (pn == pn_Load_M) {
2204 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2210 panic("Unsupported Proj from Load");
2213 static ir_node *gen_Proj_Store(ir_node *node)
2215 ir_node *store = get_Proj_pred(node);
2216 ir_node *new_store = be_transform_node(store);
2217 long pn = get_Proj_proj(node);
2219 /* renumber the proj */
2220 switch (get_sparc_irn_opcode(new_store)) {
2222 if (pn == pn_Store_M) {
2227 if (pn == pn_Store_M) {
2234 panic("Unsupported Proj from Store");
2238 * Transform the Projs from a Cmp.
2240 static ir_node *gen_Proj_Cmp(ir_node *node)
2243 panic("not implemented");
2247 * transform Projs from a Div
2249 static ir_node *gen_Proj_Div(ir_node *node)
2251 ir_node *pred = get_Proj_pred(node);
2252 ir_node *new_pred = be_transform_node(pred);
2253 long pn = get_Proj_proj(node);
2256 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2258 } else if (is_sparc_fdiv(new_pred)) {
2259 res_mode = get_Div_resmode(pred);
2261 panic("Div transformed to something unexpected: %+F",
2264 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2265 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2266 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2267 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2270 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2272 return new_r_Proj(new_pred, mode_M, pn_sparc_SDiv_M);
2276 panic("Unsupported Proj from Div");
2279 static ir_node *get_frame_base(ir_graph *irg)
2281 if (frame_base == NULL) {
2282 if (current_cconv->omit_fp) {
2283 frame_base = get_initial_sp(irg);
2285 frame_base = get_initial_fp(irg);
2291 static ir_node *gen_Proj_Start(ir_node *node)
2293 ir_node *block = get_nodes_block(node);
2294 ir_node *new_block = be_transform_node(block);
2295 long pn = get_Proj_proj(node);
2296 /* make sure prolog is constructed */
2297 be_transform_node(get_Proj_pred(node));
2299 switch ((pn_Start) pn) {
2300 case pn_Start_X_initial_exec:
2301 /* exchange ProjX with a jump */
2302 return new_bd_sparc_Ba(NULL, new_block);
2304 ir_graph *irg = get_irn_irg(node);
2305 return get_initial_mem(irg);
2307 case pn_Start_T_args:
2308 return new_r_Bad(get_irn_irg(block), mode_T);
2309 case pn_Start_P_frame_base:
2310 return get_frame_base(get_irn_irg(block));
2312 panic("Unexpected start proj: %ld\n", pn);
2315 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2317 long pn = get_Proj_proj(node);
2318 ir_node *block = get_nodes_block(node);
2319 ir_graph *irg = get_irn_irg(node);
2320 ir_node *new_block = be_transform_node(block);
2321 ir_node *args = get_Proj_pred(node);
2322 ir_node *start = get_Proj_pred(args);
2323 ir_node *new_start = be_transform_node(start);
2324 const reg_or_stackslot_t *param;
2326 /* Proj->Proj->Start must be a method argument */
2327 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2329 param = ¤t_cconv->parameters[pn];
2331 if (param->reg0 != NULL) {
2332 /* argument transmitted in register */
2333 const arch_register_t *reg = param->reg0;
2334 ir_mode *reg_mode = reg->reg_class->mode;
2335 long new_pn = param->reg_offset + start_params_offset;
2336 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2337 bool is_float = false;
2340 ir_entity *entity = get_irg_entity(irg);
2341 ir_type *method_type = get_entity_type(entity);
2342 if (pn < (long)get_method_n_params(method_type)) {
2343 ir_type *param_type = get_method_param_type(method_type, pn);
2344 ir_mode *mode = get_type_mode(param_type);
2345 is_float = mode_is_float(mode);
2350 const arch_register_t *reg1 = param->reg1;
2351 ir_node *value1 = NULL;
2354 ir_mode *reg1_mode = reg1->reg_class->mode;
2355 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2356 } else if (param->entity != NULL) {
2357 ir_node *fp = get_initial_fp(irg);
2358 ir_node *mem = get_initial_mem(irg);
2359 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2360 mode_gp, param->entity,
2362 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2365 /* convert integer value to float */
2366 value = bitcast_int_to_float(NULL, new_block, value, value1);
2370 /* argument transmitted on stack */
2371 ir_node *mem = get_initial_mem(irg);
2372 ir_mode *mode = get_type_mode(param->type);
2373 ir_node *base = get_frame_base(irg);
2377 if (mode_is_float(mode)) {
2378 load = create_ldf(NULL, new_block, base, mem, mode,
2379 param->entity, 0, true);
2380 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2382 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2383 param->entity, 0, true);
2384 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2386 set_irn_pinned(load, op_pin_state_floats);
2392 static ir_node *gen_Proj_Call(ir_node *node)
2394 long pn = get_Proj_proj(node);
2395 ir_node *call = get_Proj_pred(node);
2396 ir_node *new_call = be_transform_node(call);
2398 switch ((pn_Call) pn) {
2400 return new_r_Proj(new_call, mode_M, 0);
2401 case pn_Call_X_regular:
2402 case pn_Call_X_except:
2403 case pn_Call_T_result:
2406 panic("Unexpected Call proj %ld\n", pn);
2409 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2411 long pn = get_Proj_proj(node);
2412 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2413 ir_node *new_call = be_transform_node(call);
2414 ir_type *function_type = get_Call_type(call);
2415 calling_convention_t *cconv
2416 = sparc_decide_calling_convention(function_type, NULL);
2417 const reg_or_stackslot_t *res = &cconv->results[pn];
2418 ir_mode *mode = get_irn_mode(node);
2419 long new_pn = 1 + res->reg_offset;
2421 assert(res->req0 != NULL && res->req1 == NULL);
2422 if (mode_needs_gp_reg(mode)) {
2425 sparc_free_calling_convention(cconv);
2427 return new_r_Proj(new_call, mode, new_pn);
2431 * Transform a Proj node.
2433 static ir_node *gen_Proj(ir_node *node)
2435 ir_node *pred = get_Proj_pred(node);
2437 switch (get_irn_opcode(pred)) {
2439 return gen_Proj_Alloc(node);
2441 return gen_Proj_Store(node);
2443 return gen_Proj_Load(node);
2445 return gen_Proj_Call(node);
2447 return gen_Proj_Cmp(node);
2450 return be_duplicate_node(node);
2452 return gen_Proj_Div(node);
2454 return gen_Proj_Start(node);
2456 ir_node *pred_pred = get_Proj_pred(pred);
2457 if (is_Call(pred_pred)) {
2458 return gen_Proj_Proj_Call(node);
2459 } else if (is_Start(pred_pred)) {
2460 return gen_Proj_Proj_Start(node);
2465 if (is_sparc_AddCC_t(pred)) {
2466 return gen_Proj_AddCC_t(node);
2467 } else if (is_sparc_SubCC_t(pred)) {
2468 return gen_Proj_SubCC_t(node);
2470 panic("code selection didn't expect Proj after %+F\n", pred);
2477 static ir_node *gen_Jmp(ir_node *node)
2479 ir_node *block = get_nodes_block(node);
2480 ir_node *new_block = be_transform_node(block);
2481 dbg_info *dbgi = get_irn_dbg_info(node);
2483 return new_bd_sparc_Ba(dbgi, new_block);
2487 * configure transformation callbacks
2489 static void sparc_register_transformers(void)
2491 be_start_transform_setup();
2493 be_set_transform_function(op_Add, gen_Add);
2494 be_set_transform_function(op_Alloc, gen_Alloc);
2495 be_set_transform_function(op_And, gen_And);
2496 be_set_transform_function(op_Call, gen_Call);
2497 be_set_transform_function(op_Cmp, gen_Cmp);
2498 be_set_transform_function(op_Cond, gen_Cond);
2499 be_set_transform_function(op_Const, gen_Const);
2500 be_set_transform_function(op_Conv, gen_Conv);
2501 be_set_transform_function(op_Div, gen_Div);
2502 be_set_transform_function(op_Eor, gen_Eor);
2503 be_set_transform_function(op_Free, gen_Free);
2504 be_set_transform_function(op_Jmp, gen_Jmp);
2505 be_set_transform_function(op_Load, gen_Load);
2506 be_set_transform_function(op_Minus, gen_Minus);
2507 be_set_transform_function(op_Mul, gen_Mul);
2508 be_set_transform_function(op_Mulh, gen_Mulh);
2509 be_set_transform_function(op_Not, gen_Not);
2510 be_set_transform_function(op_Or, gen_Or);
2511 be_set_transform_function(op_Phi, gen_Phi);
2512 be_set_transform_function(op_Proj, gen_Proj);
2513 be_set_transform_function(op_Return, gen_Return);
2514 be_set_transform_function(op_Sel, gen_Sel);
2515 be_set_transform_function(op_Shl, gen_Shl);
2516 be_set_transform_function(op_Shr, gen_Shr);
2517 be_set_transform_function(op_Shrs, gen_Shrs);
2518 be_set_transform_function(op_Start, gen_Start);
2519 be_set_transform_function(op_Store, gen_Store);
2520 be_set_transform_function(op_Sub, gen_Sub);
2521 be_set_transform_function(op_Switch, gen_Switch);
2522 be_set_transform_function(op_SymConst, gen_SymConst);
2523 be_set_transform_function(op_Unknown, gen_Unknown);
2525 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2526 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2527 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2528 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2529 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2533 * Transform a Firm graph into a SPARC graph.
2535 void sparc_transform_graph(ir_graph *irg)
2537 ir_entity *entity = get_irg_entity(irg);
2538 ir_type *frame_type;
2540 sparc_register_transformers();
2542 node_to_stack = pmap_create();
2544 mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
2545 mode_fp = sparc_reg_classes[CLASS_sparc_fp].mode;
2548 mode_flags = sparc_reg_classes[CLASS_sparc_flags_class].mode;
2549 assert(sparc_reg_classes[CLASS_sparc_fpflags_class].mode == mode_flags);
2551 start_mem.irn = NULL;
2552 start_g0.irn = NULL;
2553 start_g7.irn = NULL;
2554 start_sp.irn = NULL;
2555 start_fp.irn = NULL;
2558 stackorder = be_collect_stacknodes(irg);
2560 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2561 if (sparc_variadic_fixups(irg, current_cconv)) {
2562 sparc_free_calling_convention(current_cconv);
2564 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2566 sparc_create_stacklayout(irg, current_cconv);
2567 be_add_parameter_entity_stores(irg);
2569 be_transform_graph(irg, NULL);
2571 be_free_stackorder(stackorder);
2572 sparc_free_calling_convention(current_cconv);
2574 frame_type = get_irg_frame_type(irg);
2575 if (get_type_state(frame_type) == layout_undefined)
2576 default_layout_compound_type(frame_type);
2578 pmap_destroy(node_to_stack);
2579 node_to_stack = NULL;
2581 be_add_missing_keeps(irg);
2583 /* do code placement, to optimize the position of constants */
2585 /* backend expects outedges to be always on */
2589 void sparc_init_transform(void)
2591 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");