2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
32 #include "irgraph_t.h"
38 #include "iroptimize.h"
45 #include "../benode.h"
47 #include "../beutil.h"
48 #include "../betranshlp.h"
49 #include "../beabihelper.h"
50 #include "bearch_sparc_t.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_transform.h"
54 #include "sparc_new_nodes.h"
55 #include "gen_sparc_new_nodes.h"
57 #include "gen_sparc_regalloc_if.h"
58 #include "sparc_cconv.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *current_cconv = NULL;
67 static be_stackorder_t *stackorder;
68 static ir_mode *mode_gp;
69 static ir_mode *mode_flags;
70 static ir_mode *mode_fp;
71 static ir_mode *mode_fp2;
72 //static ir_mode *mode_fp4;
73 static pmap *node_to_stack;
74 static size_t start_mem_offset;
75 static ir_node *start_mem;
76 static size_t start_g0_offset;
77 static ir_node *start_g0;
78 static size_t start_sp_offset;
79 static ir_node *start_sp;
80 static size_t start_fp_offset;
81 static ir_node *start_fp;
82 static ir_node *frame_base;
83 static size_t start_params_offset;
84 static size_t start_callee_saves_offset;
86 static const arch_register_t *const caller_saves[] = {
87 &sparc_registers[REG_G1],
88 &sparc_registers[REG_G2],
89 &sparc_registers[REG_G3],
90 &sparc_registers[REG_G4],
91 &sparc_registers[REG_O0],
92 &sparc_registers[REG_O1],
93 &sparc_registers[REG_O2],
94 &sparc_registers[REG_O3],
95 &sparc_registers[REG_O4],
96 &sparc_registers[REG_O5],
98 &sparc_registers[REG_F0],
99 &sparc_registers[REG_F1],
100 &sparc_registers[REG_F2],
101 &sparc_registers[REG_F3],
102 &sparc_registers[REG_F4],
103 &sparc_registers[REG_F5],
104 &sparc_registers[REG_F6],
105 &sparc_registers[REG_F7],
106 &sparc_registers[REG_F8],
107 &sparc_registers[REG_F9],
108 &sparc_registers[REG_F10],
109 &sparc_registers[REG_F11],
110 &sparc_registers[REG_F12],
111 &sparc_registers[REG_F13],
112 &sparc_registers[REG_F14],
113 &sparc_registers[REG_F15],
114 &sparc_registers[REG_F16],
115 &sparc_registers[REG_F17],
116 &sparc_registers[REG_F18],
117 &sparc_registers[REG_F19],
118 &sparc_registers[REG_F20],
119 &sparc_registers[REG_F21],
120 &sparc_registers[REG_F22],
121 &sparc_registers[REG_F23],
122 &sparc_registers[REG_F24],
123 &sparc_registers[REG_F25],
124 &sparc_registers[REG_F26],
125 &sparc_registers[REG_F27],
126 &sparc_registers[REG_F28],
127 &sparc_registers[REG_F29],
128 &sparc_registers[REG_F30],
129 &sparc_registers[REG_F31],
132 static const arch_register_t *const omit_fp_callee_saves[] = {
133 &sparc_registers[REG_L0],
134 &sparc_registers[REG_L1],
135 &sparc_registers[REG_L2],
136 &sparc_registers[REG_L3],
137 &sparc_registers[REG_L4],
138 &sparc_registers[REG_L5],
139 &sparc_registers[REG_L6],
140 &sparc_registers[REG_L7],
141 &sparc_registers[REG_I0],
142 &sparc_registers[REG_I1],
143 &sparc_registers[REG_I2],
144 &sparc_registers[REG_I3],
145 &sparc_registers[REG_I4],
146 &sparc_registers[REG_I5],
149 static inline bool mode_needs_gp_reg(ir_mode *mode)
151 if (mode_is_int(mode) || mode_is_reference(mode)) {
152 /* we should only see 32bit code */
153 assert(get_mode_size_bits(mode) <= 32);
160 * Create an And that will zero out upper bits.
162 * @param dbgi debug info
163 * @param block the basic block
164 * @param op the original node
165 * @param src_bits number of lower bits that will remain
167 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
171 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
172 } else if (src_bits == 16) {
173 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
174 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
177 panic("zero extension only supported for 8 and 16 bits");
182 * Generate code for a sign extension.
184 * @param dbgi debug info
185 * @param block the basic block
186 * @param op the original node
187 * @param src_bits number of lower bits that will remain
189 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
192 int shift_width = 32 - src_bits;
193 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
194 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
199 * returns true if it is assured, that the upper bits of a node are "clean"
200 * which means for a 16 or 8 bit value, that the upper bits in the register
201 * are 0 for unsigned and a copy of the last significant bit for signed
204 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
206 (void) transformed_node;
213 * Extend a value to 32 bit signed/unsigned depending on its mode.
215 * @param dbgi debug info
216 * @param block the basic block
217 * @param op the original node
218 * @param orig_mode the original mode of op
220 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
223 int bits = get_mode_size_bits(orig_mode);
227 if (mode_is_signed(orig_mode)) {
228 return gen_sign_extension(dbgi, block, op, bits);
230 return gen_zero_extension(dbgi, block, op, bits);
236 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
237 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
238 influence the significant lower bit at
239 all (for cases where mode < 32bit) */
241 ENUM_BITSET(match_flags_t)
243 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
244 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
245 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
246 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
249 * checks if a node's value can be encoded as a immediate
251 static bool is_imm_encodeable(const ir_node *node)
257 value = get_tarval_long(get_Const_tarval(node));
258 return sparc_is_value_imm_encodeable(value);
261 static bool needs_extension(ir_mode *mode)
263 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
267 * Check, if a given node is a Down-Conv, ie. a integer Conv
268 * from a mode with a mode with more bits to a mode with lesser bits.
269 * Moreover, we return only true if the node has not more than 1 user.
271 * @param node the node
272 * @return non-zero if node is a Down-Conv
274 static bool is_downconv(const ir_node *node)
282 src_mode = get_irn_mode(get_Conv_op(node));
283 dest_mode = get_irn_mode(node);
285 mode_needs_gp_reg(src_mode) &&
286 mode_needs_gp_reg(dest_mode) &&
287 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
290 static ir_node *sparc_skip_downconv(ir_node *node)
292 while (is_downconv(node)) {
293 node = get_Conv_op(node);
299 * helper function for binop operations
301 * @param new_reg register generation function ptr
302 * @param new_imm immediate generation function ptr
304 static ir_node *gen_helper_binop_args(ir_node *node,
305 ir_node *op1, ir_node *op2,
307 new_binop_reg_func new_reg,
308 new_binop_imm_func new_imm)
310 dbg_info *dbgi = get_irn_dbg_info(node);
311 ir_node *block = be_transform_node(get_nodes_block(node));
317 if (flags & MATCH_MODE_NEUTRAL) {
318 op1 = sparc_skip_downconv(op1);
319 op2 = sparc_skip_downconv(op2);
321 mode1 = get_irn_mode(op1);
322 mode2 = get_irn_mode(op2);
323 /* we shouldn't see 64bit code */
324 assert(get_mode_size_bits(mode1) <= 32);
325 assert(get_mode_size_bits(mode2) <= 32);
327 if (is_imm_encodeable(op2)) {
328 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
329 new_op1 = be_transform_node(op1);
330 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
331 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
333 return new_imm(dbgi, block, new_op1, NULL, immediate);
335 new_op2 = be_transform_node(op2);
336 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
337 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
340 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
341 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
342 return new_imm(dbgi, block, new_op2, NULL, immediate);
345 new_op1 = be_transform_node(op1);
346 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
347 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
349 return new_reg(dbgi, block, new_op1, new_op2);
352 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
353 new_binop_reg_func new_reg,
354 new_binop_imm_func new_imm)
356 ir_node *op1 = get_binop_left(node);
357 ir_node *op2 = get_binop_right(node);
358 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
362 * helper function for FP binop operations
364 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
365 new_binop_fp_func new_func_single,
366 new_binop_fp_func new_func_double,
367 new_binop_fp_func new_func_quad)
369 ir_node *block = be_transform_node(get_nodes_block(node));
370 ir_node *op1 = get_binop_left(node);
371 ir_node *new_op1 = be_transform_node(op1);
372 ir_node *op2 = get_binop_right(node);
373 ir_node *new_op2 = be_transform_node(op2);
374 dbg_info *dbgi = get_irn_dbg_info(node);
375 unsigned bits = get_mode_size_bits(mode);
379 return new_func_single(dbgi, block, new_op1, new_op2, mode);
381 return new_func_double(dbgi, block, new_op1, new_op2, mode);
383 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
387 panic("unsupported mode %+F for float op", mode);
390 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
391 new_unop_fp_func new_func_single,
392 new_unop_fp_func new_func_double,
393 new_unop_fp_func new_func_quad)
395 ir_node *block = be_transform_node(get_nodes_block(node));
396 ir_node *op1 = get_binop_left(node);
397 ir_node *new_op1 = be_transform_node(op1);
398 dbg_info *dbgi = get_irn_dbg_info(node);
399 unsigned bits = get_mode_size_bits(mode);
403 return new_func_single(dbgi, block, new_op1, mode);
405 return new_func_double(dbgi, block, new_op1, mode);
407 return new_func_quad(dbgi, block, new_op1, mode);
411 panic("unsupported mode %+F for float op", mode);
414 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
415 ir_node *op1, ir_node *flags,
416 ir_entity *imm_entity, int32_t imm);
418 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
419 ir_node *op1, ir_node *op2,
422 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
423 new_binopx_reg_func new_binopx_reg,
424 new_binopx_imm_func new_binopx_imm)
426 dbg_info *dbgi = get_irn_dbg_info(node);
427 ir_node *block = be_transform_node(get_nodes_block(node));
428 ir_node *op1 = get_irn_n(node, 0);
429 ir_node *op2 = get_irn_n(node, 1);
430 ir_node *flags = get_irn_n(node, 2);
431 ir_node *new_flags = be_transform_node(flags);
435 /* only support for mode-neutral implemented so far */
436 assert(match_flags & MATCH_MODE_NEUTRAL);
438 if (is_imm_encodeable(op2)) {
439 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
440 new_op1 = be_transform_node(op1);
441 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
443 new_op2 = be_transform_node(op2);
444 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
445 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
446 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
448 new_op1 = be_transform_node(op1);
449 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
453 static ir_node *get_g0(ir_graph *irg)
455 if (start_g0 == NULL) {
456 /* this is already the transformed start node */
457 ir_node *start = get_irg_start(irg);
458 assert(is_sparc_Start(start));
459 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
464 typedef struct address_t {
472 * Match a load/store address
474 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
477 ir_node *ptr2 = NULL;
479 ir_entity *entity = NULL;
482 ir_node *add_right = get_Add_right(base);
483 if (is_Const(add_right)) {
484 base = get_Add_left(base);
485 offset += get_tarval_long(get_Const_tarval(add_right));
488 /* Note that we don't match sub(x, Const) or chains of adds/subs
489 * because this should all be normalized by now */
491 /* we only use the symconst if we're the only user otherwise we probably
492 * won't save anything but produce multiple sethi+or combinations with
493 * just different offsets */
494 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
495 dbg_info *dbgi = get_irn_dbg_info(ptr);
496 ir_node *block = get_nodes_block(ptr);
497 ir_node *new_block = be_transform_node(block);
498 entity = get_SymConst_entity(base);
499 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
500 } else if (use_ptr2 && is_Add(base) && entity == NULL && offset == 0) {
501 ptr2 = be_transform_node(get_Add_right(base));
502 base = be_transform_node(get_Add_left(base));
504 if (sparc_is_value_imm_encodeable(offset)) {
505 base = be_transform_node(base);
507 base = be_transform_node(ptr);
513 address->ptr2 = ptr2;
514 address->entity = entity;
515 address->offset = offset;
519 * Creates an sparc Add.
521 * @param node FIRM node
522 * @return the created sparc Add node
524 static ir_node *gen_Add(ir_node *node)
526 ir_mode *mode = get_irn_mode(node);
529 if (mode_is_float(mode)) {
530 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
531 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
534 /* special case: + 0x1000 can be represented as - 0x1000 */
535 right = get_Add_right(node);
536 if (is_Const(right)) {
537 ir_node *left = get_Add_left(node);
540 /* is this simple address arithmetic? then we can let the linker do
541 * the calculation. */
542 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_node *block = be_transform_node(get_nodes_block(node));
547 /* the value of use_ptr2 shouldn't matter here */
548 match_address(node, &address, false);
549 assert(is_sparc_SetHi(address.ptr));
550 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
551 address.entity, address.offset);
554 tv = get_Const_tarval(right);
555 val = get_tarval_long(tv);
557 dbg_info *dbgi = get_irn_dbg_info(node);
558 ir_node *block = be_transform_node(get_nodes_block(node));
559 ir_node *op = get_Add_left(node);
560 ir_node *new_op = be_transform_node(op);
561 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
565 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
566 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
569 static ir_node *gen_AddCC_t(ir_node *node)
571 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
572 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
575 static ir_node *gen_Proj_AddCC_t(ir_node *node)
577 long pn = get_Proj_proj(node);
578 ir_node *pred = get_Proj_pred(node);
579 ir_node *new_pred = be_transform_node(pred);
582 case pn_sparc_AddCC_t_res:
583 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
584 case pn_sparc_AddCC_t_flags:
585 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
587 panic("Invalid AddCC_t proj found");
591 static ir_node *gen_AddX_t(ir_node *node)
593 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
594 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
598 * Creates an sparc Sub.
600 * @param node FIRM node
601 * @return the created sparc Sub node
603 static ir_node *gen_Sub(ir_node *node)
605 ir_mode *mode = get_irn_mode(node);
607 if (mode_is_float(mode)) {
608 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
609 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
612 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
613 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
616 static ir_node *gen_SubCC_t(ir_node *node)
618 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
619 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
622 static ir_node *gen_Proj_SubCC_t(ir_node *node)
624 long pn = get_Proj_proj(node);
625 ir_node *pred = get_Proj_pred(node);
626 ir_node *new_pred = be_transform_node(pred);
629 case pn_sparc_SubCC_t_res:
630 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
631 case pn_sparc_SubCC_t_flags:
632 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
634 panic("Invalid SubCC_t proj found");
638 static ir_node *gen_SubX_t(ir_node *node)
640 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
641 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
644 static ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
645 ir_node *mem, ir_mode *mode, ir_entity *entity,
646 long offset, bool is_frame_entity)
648 unsigned bits = get_mode_size_bits(mode);
649 assert(mode_is_float(mode));
651 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
652 offset, is_frame_entity);
653 } else if (bits == 64) {
654 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
655 offset, is_frame_entity);
658 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
659 offset, is_frame_entity);
663 static ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
664 ir_node *ptr, ir_node *mem, ir_mode *mode,
665 ir_entity *entity, long offset,
666 bool is_frame_entity)
668 unsigned bits = get_mode_size_bits(mode);
669 assert(mode_is_float(mode));
671 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
672 offset, is_frame_entity);
673 } else if (bits == 64) {
674 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
675 offset, is_frame_entity);
678 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
679 offset, is_frame_entity);
686 * @param node the ir Load node
687 * @return the created sparc Load node
689 static ir_node *gen_Load(ir_node *node)
691 dbg_info *dbgi = get_irn_dbg_info(node);
692 ir_mode *mode = get_Load_mode(node);
693 ir_node *block = be_transform_node(get_nodes_block(node));
694 ir_node *ptr = get_Load_ptr(node);
695 ir_node *mem = get_Load_mem(node);
696 ir_node *new_mem = be_transform_node(mem);
697 ir_node *new_load = NULL;
700 if (get_Load_unaligned(node) == align_non_aligned) {
701 panic("sparc: transformation of unaligned Loads not implemented yet");
704 if (mode_is_float(mode)) {
705 match_address(ptr, &address, false);
706 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
707 address.entity, address.offset, false);
709 match_address(ptr, &address, true);
710 if (address.ptr2 != NULL) {
711 assert(address.entity == NULL && address.offset == 0);
712 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
713 address.ptr2, new_mem, mode);
715 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
716 mode, address.entity, address.offset,
720 set_irn_pinned(new_load, get_irn_pinned(node));
726 * Transforms a Store.
728 * @param node the ir Store node
729 * @return the created sparc Store node
731 static ir_node *gen_Store(ir_node *node)
733 ir_node *block = be_transform_node(get_nodes_block(node));
734 ir_node *ptr = get_Store_ptr(node);
735 ir_node *mem = get_Store_mem(node);
736 ir_node *new_mem = be_transform_node(mem);
737 ir_node *val = get_Store_value(node);
738 ir_node *new_val = be_transform_node(val);
739 ir_mode *mode = get_irn_mode(val);
740 dbg_info *dbgi = get_irn_dbg_info(node);
741 ir_node *new_store = NULL;
744 if (get_Store_unaligned(node) == align_non_aligned) {
745 panic("sparc: transformation of unaligned Stores not implemented yet");
748 if (mode_is_float(mode)) {
749 /* TODO: variants with reg+reg address mode */
750 match_address(ptr, &address, false);
751 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
752 mode, address.entity, address.offset, false);
754 assert(get_mode_size_bits(mode) <= 32);
755 match_address(ptr, &address, true);
756 if (address.ptr2 != NULL) {
757 assert(address.entity == NULL && address.offset == 0);
758 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
759 address.ptr2, new_mem, mode);
761 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
762 new_mem, mode, address.entity,
763 address.offset, false);
766 set_irn_pinned(new_store, get_irn_pinned(node));
772 * Creates an sparc Mul.
773 * returns the lower 32bits of the 64bit multiply result
775 * @return the created sparc Mul node
777 static ir_node *gen_Mul(ir_node *node)
779 ir_mode *mode = get_irn_mode(node);
780 if (mode_is_float(mode)) {
781 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
782 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
785 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
786 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
790 * Creates an sparc Mulh.
791 * Mulh returns the upper 32bits of a mul instruction
793 * @return the created sparc Mulh node
795 static ir_node *gen_Mulh(ir_node *node)
797 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode))
801 panic("FP not supported yet");
803 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Mulh_reg, new_bd_sparc_Mulh_imm);
804 return new_r_Proj(mul, mode_gp, pn_sparc_Mulh_low);
807 static ir_node *gen_sign_extension_value(ir_node *node)
809 ir_node *block = get_nodes_block(node);
810 ir_node *new_block = be_transform_node(block);
811 ir_node *new_node = be_transform_node(node);
812 /* TODO: we could do some shortcuts for some value types probably.
813 * (For constants or other cases where we know the sign bit in
815 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
819 * Creates an sparc Div.
821 * @return the created sparc Div node
823 static ir_node *gen_Div(ir_node *node)
825 dbg_info *dbgi = get_irn_dbg_info(node);
826 ir_node *block = get_nodes_block(node);
827 ir_node *new_block = be_transform_node(block);
828 ir_mode *mode = get_Div_resmode(node);
829 ir_node *left = get_Div_left(node);
830 ir_node *left_low = be_transform_node(left);
831 ir_node *right = get_Div_right(node);
834 if (mode_is_float(mode)) {
835 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
836 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
839 if (mode_is_signed(mode)) {
840 ir_node *left_high = gen_sign_extension_value(left);
842 if (is_imm_encodeable(right)) {
843 int32_t immediate = get_tarval_long(get_Const_tarval(right));
844 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
847 ir_node *new_right = be_transform_node(right);
848 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
852 ir_graph *irg = get_irn_irg(node);
853 ir_node *left_high = get_g0(irg);
854 if (is_imm_encodeable(right)) {
855 int32_t immediate = get_tarval_long(get_Const_tarval(right));
856 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
859 ir_node *new_right = be_transform_node(right);
860 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
869 * Transforms a Not node.
871 * @return the created sparc Not node
873 static ir_node *gen_Not(ir_node *node)
875 ir_node *op = get_Not_op(node);
876 ir_graph *irg = get_irn_irg(node);
877 ir_node *zero = get_g0(irg);
878 dbg_info *dbgi = get_irn_dbg_info(node);
879 ir_node *block = be_transform_node(get_nodes_block(node));
880 ir_node *new_op = be_transform_node(op);
882 /* Note: Not(Eor()) is normalize in firm localopts already so
883 * we don't match it for xnor here */
885 /* Not can be represented with xnor 0, n */
886 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
889 static ir_node *gen_helper_bitop(ir_node *node,
890 new_binop_reg_func new_reg,
891 new_binop_imm_func new_imm,
892 new_binop_reg_func new_not_reg,
893 new_binop_imm_func new_not_imm)
895 ir_node *op1 = get_binop_left(node);
896 ir_node *op2 = get_binop_right(node);
898 return gen_helper_binop_args(node, op2, get_Not_op(op1),
900 new_not_reg, new_not_imm);
903 return gen_helper_binop_args(node, op1, get_Not_op(op2),
905 new_not_reg, new_not_imm);
907 return gen_helper_binop_args(node, op1, op2,
908 MATCH_MODE_NEUTRAL | MATCH_COMMUTATIVE,
912 static ir_node *gen_And(ir_node *node)
914 return gen_helper_bitop(node,
915 new_bd_sparc_And_reg,
916 new_bd_sparc_And_imm,
917 new_bd_sparc_AndN_reg,
918 new_bd_sparc_AndN_imm);
921 static ir_node *gen_Or(ir_node *node)
923 return gen_helper_bitop(node,
926 new_bd_sparc_OrN_reg,
927 new_bd_sparc_OrN_imm);
930 static ir_node *gen_Eor(ir_node *node)
932 return gen_helper_bitop(node,
933 new_bd_sparc_Xor_reg,
934 new_bd_sparc_Xor_imm,
935 new_bd_sparc_XNor_reg,
936 new_bd_sparc_XNor_imm);
939 static ir_node *gen_Shl(ir_node *node)
941 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
944 static ir_node *gen_Shr(ir_node *node)
946 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
949 static ir_node *gen_Shrs(ir_node *node)
951 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
955 * Transforms a Minus node.
957 static ir_node *gen_Minus(ir_node *node)
959 ir_mode *mode = get_irn_mode(node);
966 if (mode_is_float(mode)) {
967 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
968 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
970 block = be_transform_node(get_nodes_block(node));
971 dbgi = get_irn_dbg_info(node);
972 op = get_Minus_op(node);
973 new_op = be_transform_node(op);
974 zero = get_g0(get_irn_irg(node));
975 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
979 * Create an entity for a given (floating point) tarval
981 static ir_entity *create_float_const_entity(ir_tarval *tv)
983 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
984 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
985 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
986 ir_initializer_t *initializer;
994 mode = get_tarval_mode(tv);
995 type = get_type_for_mode(mode);
996 glob = get_glob_type();
997 entity = new_entity(glob, id_unique("C%u"), type);
998 set_entity_visibility(entity, ir_visibility_private);
999 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1001 initializer = create_initializer_tarval(tv);
1002 set_entity_initializer(entity, initializer);
1004 pmap_insert(isa->constants, tv, entity);
1008 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1010 ir_entity *entity = create_float_const_entity(tv);
1011 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1012 ir_node *mem = get_irg_no_mem(current_ir_graph);
1013 ir_mode *mode = get_tarval_mode(tv);
1015 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1016 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1018 set_irn_pinned(new_op, op_pin_state_floats);
1022 static ir_node *gen_Const(ir_node *node)
1024 ir_node *block = be_transform_node(get_nodes_block(node));
1025 ir_mode *mode = get_irn_mode(node);
1026 dbg_info *dbgi = get_irn_dbg_info(node);
1027 ir_tarval *tv = get_Const_tarval(node);
1030 if (mode_is_float(mode)) {
1031 return gen_float_const(dbgi, block, tv);
1034 value = get_tarval_long(tv);
1036 return get_g0(get_irn_irg(node));
1037 } else if (sparc_is_value_imm_encodeable(value)) {
1038 ir_graph *irg = get_irn_irg(node);
1039 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1041 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1042 if ((value & 0x3ff) != 0) {
1043 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1050 static ir_mode *get_cmp_mode(ir_node *b_value)
1054 if (!is_Cmp(b_value))
1055 panic("can't determine cond signednes (no cmp)");
1056 op = get_Cmp_left(b_value);
1057 return get_irn_mode(op);
1060 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
1063 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
1064 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
1066 if (get_entity_owner(entity) == get_tls_type())
1067 panic("thread local storage not supported yet in sparc backend");
1071 static ir_node *gen_SwitchJmp(ir_node *node)
1073 dbg_info *dbgi = get_irn_dbg_info(node);
1074 ir_node *block = be_transform_node(get_nodes_block(node));
1075 ir_node *selector = get_Cond_selector(node);
1076 ir_node *new_selector = be_transform_node(selector);
1077 long default_pn = get_Cond_default_proj(node);
1079 ir_node *table_address;
1084 /* switch with smaller mode not implemented yet */
1085 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1087 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1088 set_entity_visibility(entity, ir_visibility_private);
1089 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1091 /* construct base address */
1092 table_address = make_address(dbgi, block, entity, 0);
1094 idx = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
1095 /* load from jumptable */
1096 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, idx,
1097 get_irg_no_mem(current_ir_graph),
1099 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1101 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
1104 static ir_node *gen_Cond(ir_node *node)
1106 ir_node *selector = get_Cond_selector(node);
1107 ir_mode *mode = get_irn_mode(selector);
1112 ir_relation relation;
1115 // switch/case jumps
1116 if (mode != mode_b) {
1117 return gen_SwitchJmp(node);
1120 // regular if/else jumps
1121 assert(is_Cmp(selector));
1123 cmp_mode = get_cmp_mode(selector);
1125 block = be_transform_node(get_nodes_block(node));
1126 dbgi = get_irn_dbg_info(node);
1127 flag_node = be_transform_node(selector);
1128 relation = get_Cmp_relation(selector);
1129 is_unsigned = !mode_is_signed(cmp_mode);
1130 if (mode_is_float(cmp_mode)) {
1131 assert(!is_unsigned);
1132 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1134 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1141 static ir_node *gen_Cmp(ir_node *node)
1143 ir_node *op1 = get_Cmp_left(node);
1144 ir_node *op2 = get_Cmp_right(node);
1145 ir_mode *cmp_mode = get_irn_mode(op1);
1146 assert(get_irn_mode(op2) == cmp_mode);
1148 if (mode_is_float(cmp_mode)) {
1149 ir_node *block = be_transform_node(get_nodes_block(node));
1150 dbg_info *dbgi = get_irn_dbg_info(node);
1151 ir_node *new_op1 = be_transform_node(op1);
1152 ir_node *new_op2 = be_transform_node(op2);
1153 unsigned bits = get_mode_size_bits(cmp_mode);
1155 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1156 } else if (bits == 64) {
1157 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1159 assert(bits == 128);
1160 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1164 /* when we compare a bitop like and,or,... with 0 then we can directly use
1165 * the bitopcc variant.
1166 * Currently we only do this when we're the only user of the node...
1168 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1170 return gen_helper_bitop(op1,
1171 new_bd_sparc_AndCCZero_reg,
1172 new_bd_sparc_AndCCZero_imm,
1173 new_bd_sparc_AndNCCZero_reg,
1174 new_bd_sparc_AndNCCZero_imm);
1175 } else if (is_Or(op1)) {
1176 return gen_helper_bitop(op1,
1177 new_bd_sparc_OrCCZero_reg,
1178 new_bd_sparc_OrCCZero_imm,
1179 new_bd_sparc_OrNCCZero_reg,
1180 new_bd_sparc_OrNCCZero_imm);
1181 } else if (is_Eor(op1)) {
1182 return gen_helper_bitop(op1,
1183 new_bd_sparc_XorCCZero_reg,
1184 new_bd_sparc_XorCCZero_imm,
1185 new_bd_sparc_XNorCCZero_reg,
1186 new_bd_sparc_XNorCCZero_imm);
1190 /* integer compare */
1191 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1192 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1196 * Transforms a SymConst node.
1198 static ir_node *gen_SymConst(ir_node *node)
1200 ir_entity *entity = get_SymConst_entity(node);
1201 dbg_info *dbgi = get_irn_dbg_info(node);
1202 ir_node *block = get_nodes_block(node);
1203 ir_node *new_block = be_transform_node(block);
1204 return make_address(dbgi, new_block, entity, 0);
1207 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1208 ir_mode *src_mode, ir_mode *dst_mode)
1210 unsigned src_bits = get_mode_size_bits(src_mode);
1211 unsigned dst_bits = get_mode_size_bits(dst_mode);
1212 if (src_bits == 32) {
1213 if (dst_bits == 64) {
1214 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1216 assert(dst_bits == 128);
1217 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1219 } else if (src_bits == 64) {
1220 if (dst_bits == 32) {
1221 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1223 assert(dst_bits == 128);
1224 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1227 assert(src_bits == 128);
1228 if (dst_bits == 32) {
1229 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1231 assert(dst_bits == 64);
1232 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1237 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1241 unsigned bits = get_mode_size_bits(src_mode);
1243 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1244 } else if (bits == 64) {
1245 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1247 assert(bits == 128);
1248 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1252 ir_graph *irg = get_irn_irg(block);
1253 ir_node *sp = get_irg_frame(irg);
1254 ir_node *nomem = get_irg_no_mem(irg);
1255 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1257 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1259 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1260 set_irn_pinned(stf, op_pin_state_floats);
1261 set_irn_pinned(ld, op_pin_state_floats);
1266 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1269 ir_graph *irg = get_irn_irg(block);
1270 ir_node *sp = get_irg_frame(irg);
1271 ir_node *nomem = get_irg_no_mem(irg);
1272 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1273 mode_gp, NULL, 0, true);
1274 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1276 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1277 unsigned bits = get_mode_size_bits(dst_mode);
1278 set_irn_pinned(st, op_pin_state_floats);
1279 set_irn_pinned(ldf, op_pin_state_floats);
1282 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1283 } else if (bits == 64) {
1284 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1286 assert(bits == 128);
1287 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1291 static ir_node *gen_Conv(ir_node *node)
1293 ir_node *block = be_transform_node(get_nodes_block(node));
1294 ir_node *op = get_Conv_op(node);
1295 ir_mode *src_mode = get_irn_mode(op);
1296 ir_mode *dst_mode = get_irn_mode(node);
1297 dbg_info *dbgi = get_irn_dbg_info(node);
1300 int src_bits = get_mode_size_bits(src_mode);
1301 int dst_bits = get_mode_size_bits(dst_mode);
1303 if (src_mode == mode_b)
1304 panic("ConvB not lowered %+F", node);
1306 new_op = be_transform_node(op);
1307 if (src_mode == dst_mode)
1310 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1311 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1313 if (mode_is_float(src_mode)) {
1314 if (mode_is_float(dst_mode)) {
1315 /* float -> float conv */
1316 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1318 /* float -> int conv */
1319 if (!mode_is_signed(dst_mode))
1320 panic("float to unsigned not implemented yet");
1321 return create_ftoi(dbgi, block, new_op, src_mode);
1324 /* int -> float conv */
1325 if (src_bits < 32) {
1326 new_op = gen_extension(dbgi, block, new_op, src_mode);
1327 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1328 panic("unsigned to float not lowered!");
1330 return create_itof(dbgi, block, new_op, dst_mode);
1332 } else if (src_mode == mode_b) {
1333 panic("ConvB not lowered %+F", node);
1334 } else { /* complete in gp registers */
1338 if (src_bits == dst_bits) {
1339 /* kill unnecessary conv */
1343 if (src_bits < dst_bits) {
1344 min_bits = src_bits;
1345 min_mode = src_mode;
1347 min_bits = dst_bits;
1348 min_mode = dst_mode;
1351 if (upper_bits_clean(new_op, min_mode)) {
1355 if (mode_is_signed(min_mode)) {
1356 return gen_sign_extension(dbgi, block, new_op, min_bits);
1358 return gen_zero_extension(dbgi, block, new_op, min_bits);
1363 static ir_node *gen_Unknown(ir_node *node)
1365 /* just produce a 0 */
1366 ir_mode *mode = get_irn_mode(node);
1367 if (mode_is_float(mode)) {
1368 ir_node *block = be_transform_node(get_nodes_block(node));
1369 return gen_float_const(NULL, block, get_mode_null(mode));
1370 } else if (mode_needs_gp_reg(mode)) {
1371 ir_graph *irg = get_irn_irg(node);
1375 panic("Unexpected Unknown mode");
1379 * Produces the type which sits between the stack args and the locals on the
1382 static ir_type *sparc_get_between_type(void)
1384 static ir_type *between_type = NULL;
1385 static ir_type *between_type0 = NULL;
1387 if (current_cconv->omit_fp) {
1388 if (between_type0 == NULL) {
1390 = new_type_class(new_id_from_str("sparc_between_type"));
1391 set_type_size_bytes(between_type0, 0);
1393 return between_type0;
1396 if (between_type == NULL) {
1397 between_type = new_type_class(new_id_from_str("sparc_between_type"));
1398 set_type_size_bytes(between_type, SPARC_MIN_STACKSIZE);
1401 return between_type;
1404 static ir_type *compute_arg_type(ir_graph *irg)
1406 ir_entity *entity = get_irg_entity(irg);
1407 ir_type *mtp = get_entity_type(entity);
1408 size_t n_params = get_method_n_params(mtp);
1409 ir_entity **param_map = ALLOCANZ(ir_entity*, n_params);
1411 ir_type *frame_type = get_irg_frame_type(irg);
1412 size_t n_frame_members = get_compound_n_members(frame_type);
1416 ir_type *res = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1418 /* search for existing value_param entities */
1419 for (f = n_frame_members; f > 0; ) {
1420 ir_entity *member = get_compound_member(frame_type, --f);
1422 const reg_or_stackslot_t *param;
1424 if (!is_parameter_entity(member))
1426 num = get_entity_parameter_number(member);
1427 assert(num < n_params);
1428 if (param_map[num] != NULL)
1429 panic("multiple entities for parameter %u in %+F found", f, irg);
1431 param = ¤t_cconv->parameters[num];
1432 if (param->reg0 != NULL)
1435 param_map[num] = member;
1436 /* move to new arg_type */
1437 set_entity_owner(member, res);
1440 for (i = 0; i < n_params; ++i) {
1441 reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1444 if (param->reg0 != NULL)
1446 entity = param_map[i];
1448 entity = new_parameter_entity(res, i, param->type);
1449 param->entity = entity;
1450 set_entity_offset(entity, param->offset);
1456 static void create_stacklayout(ir_graph *irg)
1458 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1460 /* calling conventions must be decided by now */
1461 assert(current_cconv != NULL);
1463 memset(layout, 0, sizeof(*layout));
1465 layout->frame_type = get_irg_frame_type(irg);
1466 layout->between_type = sparc_get_between_type();
1467 layout->arg_type = compute_arg_type(irg);
1468 layout->initial_offset = 0;
1469 layout->initial_bias = 0;
1470 layout->sp_relative = current_cconv->omit_fp;
1472 assert(N_FRAME_TYPES == 3);
1473 layout->order[0] = layout->frame_type;
1474 layout->order[1] = layout->between_type;
1475 layout->order[2] = layout->arg_type;
1479 * transform the start node to the prolog code
1481 static ir_node *gen_Start(ir_node *node)
1483 ir_graph *irg = get_irn_irg(node);
1484 ir_entity *entity = get_irg_entity(irg);
1485 ir_type *function_type = get_entity_type(entity);
1486 ir_node *block = get_nodes_block(node);
1487 ir_node *new_block = be_transform_node(block);
1488 dbg_info *dbgi = get_irn_dbg_info(node);
1489 struct obstack *obst = be_get_be_obst(irg);
1490 const arch_register_req_t *req;
1496 /* start building list of start constraints */
1497 assert(obstack_object_size(obst) == 0);
1499 /* calculate number of outputs */
1500 n_outs = 3; /* memory, zero, sp */
1501 if (!current_cconv->omit_fp)
1502 ++n_outs; /* framepointer */
1503 /* function parameters */
1504 n_outs += current_cconv->n_param_regs;
1506 if (current_cconv->omit_fp) {
1507 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1510 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1514 /* first output is memory */
1515 start_mem_offset = o;
1516 arch_set_out_register_req(start, o++, arch_no_register_req);
1517 /* the zero register */
1518 start_g0_offset = o;
1519 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1520 arch_register_req_type_ignore);
1521 arch_set_out_register_req(start, o, req);
1522 arch_irn_set_register(start, o, &sparc_registers[REG_G0]);
1525 /* we need an output for the stackpointer */
1526 start_sp_offset = o;
1527 req = be_create_reg_req(obst, sp_reg,
1528 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1529 arch_set_out_register_req(start, o, req);
1530 arch_irn_set_register(start, o, sp_reg);
1533 if (!current_cconv->omit_fp) {
1534 start_fp_offset = o;
1535 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1536 arch_set_out_register_req(start, o, req);
1537 arch_irn_set_register(start, o, fp_reg);
1541 /* function parameters in registers */
1542 start_params_offset = o;
1543 for (i = 0; i < get_method_n_params(function_type); ++i) {
1544 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1545 const arch_register_t *reg0 = param->reg0;
1546 const arch_register_t *reg1 = param->reg1;
1548 arch_set_out_register_req(start, o, reg0->single_req);
1549 arch_irn_set_register(start, o, reg0);
1553 arch_set_out_register_req(start, o, reg1->single_req);
1554 arch_irn_set_register(start, o, reg1);
1558 /* we need the values of the callee saves (Note: non omit-fp mode has no
1560 start_callee_saves_offset = o;
1561 if (current_cconv->omit_fp) {
1562 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1564 for (c = 0; c < n_callee_saves; ++c) {
1565 const arch_register_t *reg = omit_fp_callee_saves[c];
1566 arch_set_out_register_req(start, o, reg->single_req);
1567 arch_irn_set_register(start, o, reg);
1571 assert(n_outs == o);
1576 static ir_node *get_initial_sp(ir_graph *irg)
1578 if (start_sp == NULL) {
1579 ir_node *start = get_irg_start(irg);
1580 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1585 static ir_node *get_initial_fp(ir_graph *irg)
1587 if (start_fp == NULL) {
1588 ir_node *start = get_irg_start(irg);
1589 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1594 static ir_node *get_initial_mem(ir_graph *irg)
1596 if (start_mem == NULL) {
1597 ir_node *start = get_irg_start(irg);
1598 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1603 static ir_node *get_stack_pointer_for(ir_node *node)
1605 /* get predecessor in stack_order list */
1606 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1609 if (stack_pred == NULL) {
1610 /* first stack user in the current block. We can simply use the
1611 * initial sp_proj for it */
1612 ir_graph *irg = get_irn_irg(node);
1613 return get_initial_sp(irg);
1616 be_transform_node(stack_pred);
1617 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1618 if (stack == NULL) {
1619 return get_stack_pointer_for(stack_pred);
1626 * transform a Return node into epilogue code + return statement
1628 static ir_node *gen_Return(ir_node *node)
1630 ir_node *block = get_nodes_block(node);
1631 ir_graph *irg = get_irn_irg(node);
1632 ir_node *new_block = be_transform_node(block);
1633 dbg_info *dbgi = get_irn_dbg_info(node);
1634 ir_node *mem = get_Return_mem(node);
1635 ir_node *new_mem = be_transform_node(mem);
1636 ir_node *sp = get_stack_pointer_for(node);
1637 size_t n_res = get_Return_n_ress(node);
1638 struct obstack *be_obst = be_get_be_obst(irg);
1641 const arch_register_req_t **reqs;
1646 /* estimate number of return values */
1647 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1648 if (current_cconv->omit_fp)
1649 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1651 in = ALLOCAN(ir_node*, n_ins);
1652 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1656 reqs[p] = arch_no_register_req;
1660 reqs[p] = sp_reg->single_req;
1664 for (i = 0; i < n_res; ++i) {
1665 ir_node *res_value = get_Return_res(node, i);
1666 ir_node *new_res_value = be_transform_node(res_value);
1667 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1668 const arch_register_t *reg = slot->reg0;
1669 assert(slot->reg1 == NULL);
1670 in[p] = new_res_value;
1671 reqs[p] = reg->single_req;
1675 if (current_cconv->omit_fp) {
1676 ir_node *start = get_irg_start(irg);
1677 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1678 for (i = 0; i < n_callee_saves; ++i) {
1679 const arch_register_t *reg = omit_fp_callee_saves[i];
1680 ir_mode *mode = reg->reg_class->mode;
1682 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1684 reqs[p] = reg->single_req;
1690 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1691 arch_set_in_register_reqs(bereturn, reqs);
1696 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1697 ir_node *value0, ir_node *value1)
1699 ir_graph *irg = current_ir_graph;
1700 ir_node *sp = get_irg_frame(irg);
1701 ir_node *nomem = get_irg_no_mem(irg);
1702 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1703 mode_gp, NULL, 0, true);
1707 set_irn_pinned(st, op_pin_state_floats);
1709 if (value1 != NULL) {
1710 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1711 mode_gp, NULL, 4, true);
1712 ir_node *in[2] = { st, st1 };
1713 ir_node *sync = new_r_Sync(block, 2, in);
1714 set_irn_pinned(st1, op_pin_state_floats);
1722 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1723 set_irn_pinned(ldf, op_pin_state_floats);
1725 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1728 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1729 ir_node *node, ir_mode *float_mode,
1732 ir_graph *irg = current_ir_graph;
1733 ir_node *stack = get_irg_frame(irg);
1734 ir_node *nomem = get_irg_no_mem(irg);
1735 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1737 int bits = get_mode_size_bits(float_mode);
1739 set_irn_pinned(stf, op_pin_state_floats);
1741 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1742 set_irn_pinned(ld, op_pin_state_floats);
1743 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1746 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1748 set_irn_pinned(ld, op_pin_state_floats);
1749 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1751 arch_irn_add_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1752 arch_irn_add_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1759 static ir_node *gen_Call(ir_node *node)
1761 ir_graph *irg = get_irn_irg(node);
1762 ir_node *callee = get_Call_ptr(node);
1763 ir_node *block = get_nodes_block(node);
1764 ir_node *new_block = be_transform_node(block);
1765 ir_node *mem = get_Call_mem(node);
1766 ir_node *new_mem = be_transform_node(mem);
1767 dbg_info *dbgi = get_irn_dbg_info(node);
1768 ir_type *type = get_Call_type(node);
1769 size_t n_params = get_Call_n_params(node);
1770 /* max inputs: memory, callee, register arguments */
1771 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1772 struct obstack *obst = be_get_be_obst(irg);
1773 calling_convention_t *cconv
1774 = sparc_decide_calling_convention(type, NULL);
1775 size_t n_param_regs = cconv->n_param_regs;
1776 /* param-regs + mem + stackpointer + callee */
1777 unsigned max_inputs = 3 + n_param_regs;
1778 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1779 const arch_register_req_t **in_req
1780 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1784 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1785 ir_entity *entity = NULL;
1786 ir_node *new_frame = get_stack_pointer_for(node);
1795 assert(n_params == get_method_n_params(type));
1797 /* construct arguments */
1800 in_req[in_arity] = arch_no_register_req;
1804 /* stack pointer input */
1805 /* construct an IncSP -> we have to always be sure that the stack is
1806 * aligned even if we don't push arguments on it */
1807 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1808 cconv->param_stack_size, 1);
1809 in_req[in_arity] = sp_reg->single_req;
1810 in[in_arity] = incsp;
1814 for (p = 0; p < n_params; ++p) {
1815 ir_node *value = get_Call_param(node, p);
1816 ir_node *new_value = be_transform_node(value);
1817 const reg_or_stackslot_t *param = &cconv->parameters[p];
1818 ir_type *param_type = get_method_param_type(type, p);
1819 ir_mode *mode = get_type_mode(param_type);
1820 ir_node *new_values[2];
1823 if (mode_is_float(mode) && param->reg0 != NULL) {
1824 unsigned size_bits = get_mode_size_bits(mode);
1825 assert(size_bits <= 64);
1826 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1828 new_values[0] = new_value;
1829 new_values[1] = NULL;
1832 /* put value into registers */
1833 if (param->reg0 != NULL) {
1834 in[in_arity] = new_values[0];
1835 in_req[in_arity] = param->reg0->single_req;
1837 if (new_values[1] == NULL)
1840 if (param->reg1 != NULL) {
1841 assert(new_values[1] != NULL);
1842 in[in_arity] = new_values[1];
1843 in_req[in_arity] = param->reg1->single_req;
1848 /* we need a store if we're here */
1849 if (new_values[1] != NULL) {
1850 new_value = new_values[1];
1854 /* create a parameter frame if necessary */
1855 if (mode_is_float(mode)) {
1856 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1857 mode, NULL, param->offset, true);
1859 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1860 new_mem, mode, NULL, param->offset, true);
1862 set_irn_pinned(str, op_pin_state_floats);
1863 sync_ins[sync_arity++] = str;
1866 /* construct memory input */
1867 if (sync_arity == 0) {
1868 in[mem_pos] = new_mem;
1869 } else if (sync_arity == 1) {
1870 in[mem_pos] = sync_ins[0];
1872 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1875 if (is_SymConst(callee)) {
1876 entity = get_SymConst_entity(callee);
1878 in[in_arity] = be_transform_node(callee);
1879 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1882 assert(in_arity <= (int)max_inputs);
1888 out_arity = 1 + n_caller_saves;
1890 /* create call node */
1891 if (entity != NULL) {
1892 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1895 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity);
1897 arch_set_in_register_reqs(res, in_req);
1899 /* create output register reqs */
1901 arch_set_out_register_req(res, o++, arch_no_register_req);
1902 for (i = 0; i < n_caller_saves; ++i) {
1903 const arch_register_t *reg = caller_saves[i];
1904 arch_set_out_register_req(res, o++, reg->single_req);
1906 assert(o == out_arity);
1908 /* copy pinned attribute */
1909 set_irn_pinned(res, get_irn_pinned(node));
1911 /* IncSP to destroy the call stackframe */
1912 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1913 /* if we are the last IncSP producer in a block then we have to keep
1915 * Note: This here keeps all producers which is more than necessary */
1916 add_irn_dep(incsp, res);
1919 pmap_insert(node_to_stack, node, incsp);
1921 sparc_free_calling_convention(cconv);
1925 static ir_node *gen_Sel(ir_node *node)
1927 dbg_info *dbgi = get_irn_dbg_info(node);
1928 ir_node *block = get_nodes_block(node);
1929 ir_node *new_block = be_transform_node(block);
1930 ir_node *ptr = get_Sel_ptr(node);
1931 ir_node *new_ptr = be_transform_node(ptr);
1932 ir_entity *entity = get_Sel_entity(node);
1934 /* must be the frame pointer all other sels must have been lowered
1936 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1938 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1941 static const arch_register_req_t float1_req = {
1942 arch_register_req_type_normal,
1943 &sparc_reg_classes[CLASS_sparc_fp],
1949 static const arch_register_req_t float2_req = {
1950 arch_register_req_type_normal | arch_register_req_type_aligned,
1951 &sparc_reg_classes[CLASS_sparc_fp],
1957 static const arch_register_req_t float4_req = {
1958 arch_register_req_type_normal | arch_register_req_type_aligned,
1959 &sparc_reg_classes[CLASS_sparc_fp],
1967 static const arch_register_req_t *get_float_req(ir_mode *mode)
1969 unsigned bits = get_mode_size_bits(mode);
1971 assert(mode_is_float(mode));
1974 } else if (bits == 64) {
1977 assert(bits == 128);
1983 * Transform some Phi nodes
1985 static ir_node *gen_Phi(ir_node *node)
1987 const arch_register_req_t *req;
1988 ir_node *block = be_transform_node(get_nodes_block(node));
1989 ir_graph *irg = current_ir_graph;
1990 dbg_info *dbgi = get_irn_dbg_info(node);
1991 ir_mode *mode = get_irn_mode(node);
1994 if (mode_needs_gp_reg(mode)) {
1995 /* we shouldn't have any 64bit stuff around anymore */
1996 assert(get_mode_size_bits(mode) <= 32);
1997 /* all integer operations are on 32bit registers now */
1999 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2000 } else if (mode_is_float(mode)) {
2002 req = get_float_req(mode);
2004 req = arch_no_register_req;
2007 /* phi nodes allow loops, so we use the old arguments for now
2008 * and fix this later */
2009 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2010 copy_node_attr(irg, node, phi);
2011 be_duplicate_deps(node, phi);
2012 arch_set_out_register_req(phi, 0, req);
2013 be_enqueue_preds(node);
2018 * Transform a Proj from a Load.
2020 static ir_node *gen_Proj_Load(ir_node *node)
2022 ir_node *load = get_Proj_pred(node);
2023 ir_node *new_load = be_transform_node(load);
2024 dbg_info *dbgi = get_irn_dbg_info(node);
2025 long pn = get_Proj_proj(node);
2027 /* renumber the proj */
2028 switch (get_sparc_irn_opcode(new_load)) {
2030 /* handle all gp loads equal: they have the same proj numbers. */
2031 if (pn == pn_Load_res) {
2032 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2033 } else if (pn == pn_Load_M) {
2034 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2038 if (pn == pn_Load_res) {
2039 return new_rd_Proj(dbgi, new_load, mode_fp, pn_sparc_Ldf_res);
2040 } else if (pn == pn_Load_M) {
2041 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2047 panic("Unsupported Proj from Load");
2050 static ir_node *gen_Proj_Store(ir_node *node)
2052 ir_node *store = get_Proj_pred(node);
2053 ir_node *new_store = be_transform_node(store);
2054 long pn = get_Proj_proj(node);
2056 /* renumber the proj */
2057 switch (get_sparc_irn_opcode(new_store)) {
2059 if (pn == pn_Store_M) {
2064 if (pn == pn_Store_M) {
2071 panic("Unsupported Proj from Store");
2075 * Transform the Projs from a Cmp.
2077 static ir_node *gen_Proj_Cmp(ir_node *node)
2080 panic("not implemented");
2084 * transform Projs from a Div
2086 static ir_node *gen_Proj_Div(ir_node *node)
2088 ir_node *pred = get_Proj_pred(node);
2089 ir_node *new_pred = be_transform_node(pred);
2090 long pn = get_Proj_proj(node);
2092 assert(is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)
2093 || is_sparc_fdiv(new_pred));
2094 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2095 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2096 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2097 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2100 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_res);
2102 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
2106 panic("Unsupported Proj from Div");
2109 static ir_node *get_frame_base(ir_graph *irg)
2111 if (frame_base == NULL) {
2112 if (current_cconv->omit_fp) {
2113 frame_base = get_initial_sp(irg);
2115 frame_base = get_initial_fp(irg);
2121 static ir_node *gen_Proj_Start(ir_node *node)
2123 ir_node *block = get_nodes_block(node);
2124 ir_node *new_block = be_transform_node(block);
2125 long pn = get_Proj_proj(node);
2126 /* make sure prolog is constructed */
2127 be_transform_node(get_Proj_pred(node));
2129 switch ((pn_Start) pn) {
2130 case pn_Start_X_initial_exec:
2131 /* exchange ProjX with a jump */
2132 return new_bd_sparc_Ba(NULL, new_block);
2134 ir_graph *irg = get_irn_irg(node);
2135 return get_initial_mem(irg);
2137 case pn_Start_T_args:
2138 return new_r_Bad(get_irn_irg(block), mode_T);
2139 case pn_Start_P_frame_base:
2140 return get_frame_base(get_irn_irg(block));
2142 panic("Unexpected start proj: %ld\n", pn);
2145 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2147 long pn = get_Proj_proj(node);
2148 ir_node *block = get_nodes_block(node);
2149 ir_graph *irg = get_irn_irg(node);
2150 ir_node *new_block = be_transform_node(block);
2151 ir_entity *entity = get_irg_entity(irg);
2152 ir_type *method_type = get_entity_type(entity);
2153 ir_type *param_type = get_method_param_type(method_type, pn);
2154 ir_node *args = get_Proj_pred(node);
2155 ir_node *start = get_Proj_pred(args);
2156 ir_node *new_start = be_transform_node(start);
2157 const reg_or_stackslot_t *param;
2159 /* Proj->Proj->Start must be a method argument */
2160 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2162 param = ¤t_cconv->parameters[pn];
2164 if (param->reg0 != NULL) {
2165 /* argument transmitted in register */
2166 ir_mode *mode = get_type_mode(param_type);
2167 const arch_register_t *reg = param->reg0;
2168 ir_mode *reg_mode = reg->reg_class->mode;
2169 long pn = param->reg_offset + start_params_offset;
2170 ir_node *value = new_r_Proj(new_start, reg_mode, pn);
2172 if (mode_is_float(mode)) {
2173 const arch_register_t *reg1 = param->reg1;
2174 ir_node *value1 = NULL;
2177 ir_mode *reg1_mode = reg1->reg_class->mode;
2178 value1 = new_r_Proj(new_start, reg1_mode, pn+1);
2179 } else if (param->entity != NULL) {
2180 ir_node *fp = get_initial_fp(irg);
2181 ir_node *mem = get_initial_mem(irg);
2182 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2183 mode_gp, param->entity,
2185 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2188 /* convert integer value to float */
2189 value = bitcast_int_to_float(NULL, new_block, value, value1);
2193 /* argument transmitted on stack */
2194 ir_node *mem = get_initial_mem(irg);
2195 ir_mode *mode = get_type_mode(param->type);
2196 ir_node *base = get_frame_base(irg);
2200 if (mode_is_float(mode)) {
2201 load = create_ldf(NULL, new_block, base, mem, mode,
2202 param->entity, 0, true);
2203 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2205 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2206 param->entity, 0, true);
2207 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2209 set_irn_pinned(load, op_pin_state_floats);
2215 static ir_node *gen_Proj_Call(ir_node *node)
2217 long pn = get_Proj_proj(node);
2218 ir_node *call = get_Proj_pred(node);
2219 ir_node *new_call = be_transform_node(call);
2221 switch ((pn_Call) pn) {
2223 return new_r_Proj(new_call, mode_M, 0);
2224 case pn_Call_X_regular:
2225 case pn_Call_X_except:
2226 case pn_Call_T_result:
2229 panic("Unexpected Call proj %ld\n", pn);
2233 * Finds number of output value of a mode_T node which is constrained to
2234 * a single specific register.
2236 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
2238 int n_outs = arch_irn_get_n_outs(node);
2241 for (o = 0; o < n_outs; ++o) {
2242 const arch_register_req_t *req = arch_get_out_register_req(node, o);
2243 if (req == reg->single_req)
2249 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2251 long pn = get_Proj_proj(node);
2252 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2253 ir_node *new_call = be_transform_node(call);
2254 ir_type *function_type = get_Call_type(call);
2255 calling_convention_t *cconv
2256 = sparc_decide_calling_convention(function_type, NULL);
2257 const reg_or_stackslot_t *res = &cconv->results[pn];
2258 const arch_register_t *reg = res->reg0;
2262 assert(res->reg0 != NULL && res->reg1 == NULL);
2263 regn = find_out_for_reg(new_call, reg);
2265 panic("Internal error in calling convention for return %+F", node);
2267 mode = res->reg0->reg_class->mode;
2269 sparc_free_calling_convention(cconv);
2271 return new_r_Proj(new_call, mode, regn);
2275 * Transform a Proj node.
2277 static ir_node *gen_Proj(ir_node *node)
2279 ir_node *pred = get_Proj_pred(node);
2281 switch (get_irn_opcode(pred)) {
2283 return gen_Proj_Store(node);
2285 return gen_Proj_Load(node);
2287 return gen_Proj_Call(node);
2289 return gen_Proj_Cmp(node);
2291 return be_duplicate_node(node);
2293 return gen_Proj_Div(node);
2295 return gen_Proj_Start(node);
2297 ir_node *pred_pred = get_Proj_pred(pred);
2298 if (is_Call(pred_pred)) {
2299 return gen_Proj_Proj_Call(node);
2300 } else if (is_Start(pred_pred)) {
2301 return gen_Proj_Proj_Start(node);
2306 if (is_sparc_AddCC_t(pred)) {
2307 return gen_Proj_AddCC_t(node);
2308 } else if (is_sparc_SubCC_t(pred)) {
2309 return gen_Proj_SubCC_t(node);
2311 panic("code selection didn't expect Proj after %+F\n", pred);
2318 static ir_node *gen_Jmp(ir_node *node)
2320 ir_node *block = get_nodes_block(node);
2321 ir_node *new_block = be_transform_node(block);
2322 dbg_info *dbgi = get_irn_dbg_info(node);
2324 return new_bd_sparc_Ba(dbgi, new_block);
2328 * configure transformation callbacks
2330 static void sparc_register_transformers(void)
2332 be_start_transform_setup();
2334 be_set_transform_function(op_Add, gen_Add);
2335 be_set_transform_function(op_And, gen_And);
2336 be_set_transform_function(op_Call, gen_Call);
2337 be_set_transform_function(op_Cmp, gen_Cmp);
2338 be_set_transform_function(op_Cond, gen_Cond);
2339 be_set_transform_function(op_Const, gen_Const);
2340 be_set_transform_function(op_Conv, gen_Conv);
2341 be_set_transform_function(op_Div, gen_Div);
2342 be_set_transform_function(op_Eor, gen_Eor);
2343 be_set_transform_function(op_Jmp, gen_Jmp);
2344 be_set_transform_function(op_Load, gen_Load);
2345 be_set_transform_function(op_Minus, gen_Minus);
2346 be_set_transform_function(op_Mul, gen_Mul);
2347 be_set_transform_function(op_Mulh, gen_Mulh);
2348 be_set_transform_function(op_Not, gen_Not);
2349 be_set_transform_function(op_Or, gen_Or);
2350 be_set_transform_function(op_Phi, gen_Phi);
2351 be_set_transform_function(op_Proj, gen_Proj);
2352 be_set_transform_function(op_Return, gen_Return);
2353 be_set_transform_function(op_Sel, gen_Sel);
2354 be_set_transform_function(op_Shl, gen_Shl);
2355 be_set_transform_function(op_Shr, gen_Shr);
2356 be_set_transform_function(op_Shrs, gen_Shrs);
2357 be_set_transform_function(op_Start, gen_Start);
2358 be_set_transform_function(op_Store, gen_Store);
2359 be_set_transform_function(op_Sub, gen_Sub);
2360 be_set_transform_function(op_SymConst, gen_SymConst);
2361 be_set_transform_function(op_Unknown, gen_Unknown);
2363 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2364 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2365 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2366 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2367 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2371 * Transform a Firm graph into a SPARC graph.
2373 void sparc_transform_graph(ir_graph *irg)
2375 ir_entity *entity = get_irg_entity(irg);
2376 ir_type *frame_type;
2378 sparc_register_transformers();
2380 node_to_stack = pmap_create();
2385 mode_flags = mode_Bu;
2394 stackorder = be_collect_stacknodes(irg);
2396 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2397 create_stacklayout(irg);
2398 be_add_parameter_entity_stores(irg);
2400 be_transform_graph(irg, NULL);
2402 be_free_stackorder(stackorder);
2403 sparc_free_calling_convention(current_cconv);
2405 frame_type = get_irg_frame_type(irg);
2406 if (get_type_state(frame_type) == layout_undefined)
2407 default_layout_compound_type(frame_type);
2409 pmap_destroy(node_to_stack);
2410 node_to_stack = NULL;
2412 be_add_missing_keeps(irg);
2414 /* do code placement, to optimize the position of constants */
2418 void sparc_init_transform(void)
2420 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");