2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
31 #include "irgraph_t.h"
37 #include "iroptimize.h"
44 #include "../benode.h"
46 #include "../beutil.h"
47 #include "../betranshlp.h"
48 #include "../beabihelper.h"
49 #include "bearch_sparc_t.h"
51 #include "sparc_nodes_attr.h"
52 #include "sparc_transform.h"
53 #include "sparc_new_nodes.h"
54 #include "gen_sparc_new_nodes.h"
56 #include "gen_sparc_regalloc_if.h"
57 #include "sparc_cconv.h"
61 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
63 static beabi_helper_env_t *abihelper;
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *cconv = NULL;
67 static ir_mode *mode_gp;
68 static ir_mode *mode_fp;
69 static ir_mode *mode_fp2;
70 //static ir_mode *mode_fp4;
71 static pmap *node_to_stack;
73 static inline int mode_needs_gp_reg(ir_mode *mode)
75 return mode_is_int(mode) || mode_is_reference(mode);
79 * Create an And that will zero out upper bits.
81 * @param dbgi debug info
82 * @param block the basic block
83 * @param op the original node
84 * @param src_bits number of lower bits that will remain
86 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
90 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
91 } else if (src_bits == 16) {
92 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
93 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
96 panic("zero extension only supported for 8 and 16 bits");
101 * Generate code for a sign extension.
103 * @param dbgi debug info
104 * @param block the basic block
105 * @param op the original node
106 * @param src_bits number of lower bits that will remain
108 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
111 int shift_width = 32 - src_bits;
112 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
113 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
118 * returns true if it is assured, that the upper bits of a node are "clean"
119 * which means for a 16 or 8 bit value, that the upper bits in the register
120 * are 0 for unsigned and a copy of the last significant bit for signed
123 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
125 (void) transformed_node;
132 * Extend a value to 32 bit signed/unsigned depending on its mode.
134 * @param dbgi debug info
135 * @param block the basic block
136 * @param op the original node
137 * @param orig_mode the original mode of op
139 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
142 int bits = get_mode_size_bits(orig_mode);
146 if (mode_is_signed(orig_mode)) {
147 return gen_sign_extension(dbgi, block, op, bits);
149 return gen_zero_extension(dbgi, block, op, bits);
155 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
156 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
157 influence the significant lower bit at
158 all (for cases where mode < 32bit) */
160 ENUM_BITSET(match_flags_t)
162 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
163 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
164 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
165 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
168 * checks if a node's value can be encoded as a immediate
170 static bool is_imm_encodeable(const ir_node *node)
176 value = get_tarval_long(get_Const_tarval(node));
177 return sparc_is_value_imm_encodeable(value);
180 static bool needs_extension(ir_mode *mode)
182 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
186 * Check, if a given node is a Down-Conv, ie. a integer Conv
187 * from a mode with a mode with more bits to a mode with lesser bits.
188 * Moreover, we return only true if the node has not more than 1 user.
190 * @param node the node
191 * @return non-zero if node is a Down-Conv
193 static bool is_downconv(const ir_node *node)
201 src_mode = get_irn_mode(get_Conv_op(node));
202 dest_mode = get_irn_mode(node);
204 mode_needs_gp_reg(src_mode) &&
205 mode_needs_gp_reg(dest_mode) &&
206 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
209 static ir_node *sparc_skip_downconv(ir_node *node)
211 while (is_downconv(node)) {
212 node = get_Conv_op(node);
218 * helper function for binop operations
220 * @param new_reg register generation function ptr
221 * @param new_imm immediate generation function ptr
223 static ir_node *gen_helper_binop_args(ir_node *node,
224 ir_node *op1, ir_node *op2,
226 new_binop_reg_func new_reg,
227 new_binop_imm_func new_imm)
229 dbg_info *dbgi = get_irn_dbg_info(node);
230 ir_node *block = be_transform_node(get_nodes_block(node));
236 if (flags & MATCH_MODE_NEUTRAL) {
237 op1 = sparc_skip_downconv(op1);
238 op2 = sparc_skip_downconv(op2);
240 mode1 = get_irn_mode(op1);
241 mode2 = get_irn_mode(op2);
243 if (is_imm_encodeable(op2)) {
244 ir_node *new_op1 = be_transform_node(op1);
245 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
246 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
247 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
249 return new_imm(dbgi, block, new_op1, NULL, immediate);
251 new_op2 = be_transform_node(op2);
252 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
253 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
256 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
257 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
258 return new_imm(dbgi, block, new_op2, NULL, immediate);
261 new_op1 = be_transform_node(op1);
262 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
263 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
265 return new_reg(dbgi, block, new_op1, new_op2);
268 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
269 new_binop_reg_func new_reg,
270 new_binop_imm_func new_imm)
272 ir_node *op1 = get_binop_left(node);
273 ir_node *op2 = get_binop_right(node);
274 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
278 * helper function for FP binop operations
280 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
281 new_binop_fp_func new_func_single,
282 new_binop_fp_func new_func_double,
283 new_binop_fp_func new_func_quad)
285 ir_node *block = be_transform_node(get_nodes_block(node));
286 ir_node *op1 = get_binop_left(node);
287 ir_node *new_op1 = be_transform_node(op1);
288 ir_node *op2 = get_binop_right(node);
289 ir_node *new_op2 = be_transform_node(op2);
290 dbg_info *dbgi = get_irn_dbg_info(node);
291 unsigned bits = get_mode_size_bits(mode);
295 return new_func_single(dbgi, block, new_op1, new_op2, mode);
297 return new_func_double(dbgi, block, new_op1, new_op2, mode);
299 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
303 panic("unsupported mode %+F for float op", mode);
306 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
307 new_unop_fp_func new_func_single,
308 new_unop_fp_func new_func_double,
309 new_unop_fp_func new_func_quad)
311 ir_node *block = be_transform_node(get_nodes_block(node));
312 ir_node *op1 = get_binop_left(node);
313 ir_node *new_op1 = be_transform_node(op1);
314 dbg_info *dbgi = get_irn_dbg_info(node);
315 unsigned bits = get_mode_size_bits(mode);
319 return new_func_single(dbgi, block, new_op1, mode);
321 return new_func_double(dbgi, block, new_op1, mode);
323 return new_func_quad(dbgi, block, new_op1, mode);
327 panic("unsupported mode %+F for float op", mode);
330 static ir_node *get_g0(void)
332 return be_prolog_get_reg_value(abihelper, &sparc_registers[REG_G0]);
335 typedef struct address_t {
343 * Match a load/store address
345 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
348 ir_node *ptr2 = NULL;
350 ir_entity *entity = NULL;
353 ir_node *add_right = get_Add_right(base);
354 if (is_Const(add_right)) {
355 base = get_Add_left(base);
356 offset += get_tarval_long(get_Const_tarval(add_right));
359 /* Note that we don't match sub(x, Const) or chains of adds/subs
360 * because this should all be normalized by now */
362 /* we only use the symconst if we're the only user otherwise we probably
363 * won't save anything but produce multiple sethi+or combinations with
364 * just different offsets */
365 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
366 dbg_info *dbgi = get_irn_dbg_info(ptr);
367 ir_node *block = get_nodes_block(ptr);
368 ir_node *new_block = be_transform_node(block);
369 entity = get_SymConst_entity(base);
370 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
371 } else if (use_ptr2 && is_Add(base) && entity == NULL && offset == 0) {
372 ptr2 = be_transform_node(get_Add_right(base));
373 base = be_transform_node(get_Add_left(base));
375 if (sparc_is_value_imm_encodeable(offset)) {
376 base = be_transform_node(base);
378 base = be_transform_node(ptr);
384 address->ptr2 = ptr2;
385 address->entity = entity;
386 address->offset = offset;
390 * Creates an sparc Add.
392 * @param node FIRM node
393 * @return the created sparc Add node
395 static ir_node *gen_Add(ir_node *node)
397 ir_mode *mode = get_irn_mode(node);
400 if (mode_is_float(mode)) {
401 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
402 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
405 /* special case: + 0x1000 can be represented as - 0x1000 */
406 right = get_Add_right(node);
407 if (is_Const(right)) {
408 ir_node *left = get_Add_left(node);
411 /* is this simple address arithmetic? then we can let the linker do
412 * the calculation. */
413 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
414 dbg_info *dbgi = get_irn_dbg_info(node);
415 ir_node *block = be_transform_node(get_nodes_block(node));
418 /* the value of use_ptr2 shouldn't matter here */
419 match_address(node, &address, false);
420 assert(is_sparc_SetHi(address.ptr));
421 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
422 address.entity, address.offset);
425 tv = get_Const_tarval(right);
426 val = get_tarval_long(tv);
428 dbg_info *dbgi = get_irn_dbg_info(node);
429 ir_node *block = be_transform_node(get_nodes_block(node));
430 ir_node *op = get_Add_left(node);
431 ir_node *new_op = be_transform_node(op);
432 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
436 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
437 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
441 * Creates an sparc Sub.
443 * @param node FIRM node
444 * @return the created sparc Sub node
446 static ir_node *gen_Sub(ir_node *node)
448 ir_mode *mode = get_irn_mode(node);
450 if (mode_is_float(mode)) {
451 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
452 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
455 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
458 static ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
459 ir_node *mem, ir_mode *mode, ir_entity *entity,
460 long offset, bool is_frame_entity)
462 unsigned bits = get_mode_size_bits(mode);
463 assert(mode_is_float(mode));
465 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
466 offset, is_frame_entity);
467 } else if (bits == 64) {
468 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
469 offset, is_frame_entity);
472 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
473 offset, is_frame_entity);
477 static ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
478 ir_node *ptr, ir_node *mem, ir_mode *mode,
479 ir_entity *entity, long offset,
480 bool is_frame_entity)
482 unsigned bits = get_mode_size_bits(mode);
483 assert(mode_is_float(mode));
485 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
486 offset, is_frame_entity);
487 } else if (bits == 64) {
488 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
489 offset, is_frame_entity);
492 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
493 offset, is_frame_entity);
500 * @param node the ir Load node
501 * @return the created sparc Load node
503 static ir_node *gen_Load(ir_node *node)
505 dbg_info *dbgi = get_irn_dbg_info(node);
506 ir_mode *mode = get_Load_mode(node);
507 ir_node *block = be_transform_node(get_nodes_block(node));
508 ir_node *ptr = get_Load_ptr(node);
509 ir_node *mem = get_Load_mem(node);
510 ir_node *new_mem = be_transform_node(mem);
511 ir_node *new_load = NULL;
514 if (mode_is_float(mode)) {
515 match_address(ptr, &address, false);
516 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
517 address.entity, address.offset, false);
519 match_address(ptr, &address, true);
520 if (address.ptr2 != NULL) {
521 assert(address.entity == NULL && address.offset == 0);
522 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
523 address.ptr2, new_mem, mode);
525 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
526 mode, address.entity, address.offset,
530 set_irn_pinned(new_load, get_irn_pinned(node));
536 * Transforms a Store.
538 * @param node the ir Store node
539 * @return the created sparc Store node
541 static ir_node *gen_Store(ir_node *node)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *ptr = get_Store_ptr(node);
545 ir_node *mem = get_Store_mem(node);
546 ir_node *new_mem = be_transform_node(mem);
547 ir_node *val = get_Store_value(node);
548 ir_node *new_val = be_transform_node(val);
549 ir_mode *mode = get_irn_mode(val);
550 dbg_info *dbgi = get_irn_dbg_info(node);
551 ir_node *new_store = NULL;
554 if (mode_is_float(mode)) {
555 /* TODO: variants with reg+reg address mode */
556 match_address(ptr, &address, false);
557 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
558 mode, address.entity, address.offset, false);
560 match_address(ptr, &address, true);
561 if (address.ptr2 != NULL) {
562 assert(address.entity == NULL && address.offset == 0);
563 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
564 address.ptr2, new_mem, mode);
566 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
567 new_mem, mode, address.entity,
568 address.offset, false);
571 set_irn_pinned(new_store, get_irn_pinned(node));
577 * Creates an sparc Mul.
578 * returns the lower 32bits of the 64bit multiply result
580 * @return the created sparc Mul node
582 static ir_node *gen_Mul(ir_node *node)
584 ir_mode *mode = get_irn_mode(node);
585 if (mode_is_float(mode)) {
586 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
587 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
590 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
591 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
595 * Creates an sparc Mulh.
596 * Mulh returns the upper 32bits of a mul instruction
598 * @return the created sparc Mulh node
600 static ir_node *gen_Mulh(ir_node *node)
602 ir_mode *mode = get_irn_mode(node);
605 if (mode_is_float(mode))
606 panic("FP not supported yet");
608 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Mulh_reg, new_bd_sparc_Mulh_imm);
609 return new_r_Proj(mul, mode_gp, pn_sparc_Mulh_low);
612 static ir_node *gen_sign_extension_value(ir_node *node)
614 ir_node *block = get_nodes_block(node);
615 ir_node *new_block = be_transform_node(block);
616 ir_node *new_node = be_transform_node(node);
617 /* TODO: we could do some shortcuts for some value types probably.
618 * (For constants or other cases where we know the sign bit in
620 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
624 * Creates an sparc Div.
626 * @return the created sparc Div node
628 static ir_node *gen_Div(ir_node *node)
630 dbg_info *dbgi = get_irn_dbg_info(node);
631 ir_node *block = get_nodes_block(node);
632 ir_node *new_block = be_transform_node(block);
633 ir_mode *mode = get_Div_resmode(node);
634 ir_node *left = get_Div_left(node);
635 ir_node *left_low = be_transform_node(left);
636 ir_node *right = get_Div_right(node);
639 if (mode_is_float(mode)) {
640 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
641 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
644 if (mode_is_signed(mode)) {
645 ir_node *left_high = gen_sign_extension_value(left);
647 if (is_imm_encodeable(right)) {
648 int32_t immediate = get_tarval_long(get_Const_tarval(right));
649 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
652 ir_node *new_right = be_transform_node(right);
653 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
657 ir_node *left_high = get_g0();
658 if (is_imm_encodeable(right)) {
659 int32_t immediate = get_tarval_long(get_Const_tarval(right));
660 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
663 ir_node *new_right = be_transform_node(right);
664 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
673 static ir_node *gen_Abs(ir_node *node)
675 ir_mode *const mode = get_irn_mode(node);
677 if (mode_is_float(mode)) {
678 return gen_helper_unfpop(node, mode, new_bd_sparc_fabs_s,
679 new_bd_sparc_fabs_d, new_bd_sparc_fabs_q);
681 ir_node *const block = be_transform_node(get_nodes_block(node));
682 dbg_info *const dbgi = get_irn_dbg_info(node);
683 ir_node *const op = get_Abs_op(node);
684 ir_node *const new_op = be_transform_node(op);
685 ir_node *const sra = new_bd_sparc_Sra_imm(dbgi, block, new_op, NULL, 31);
686 ir_node *const xor = new_bd_sparc_Xor_reg(dbgi, block, new_op, sra);
687 ir_node *const sub = new_bd_sparc_Sub_reg(dbgi, block, xor, sra);
694 * Transforms a Not node.
696 * @return the created sparc Not node
698 static ir_node *gen_Not(ir_node *node)
700 ir_node *op = get_Not_op(node);
701 ir_node *zero = get_g0();
702 dbg_info *dbgi = get_irn_dbg_info(node);
703 ir_node *block = be_transform_node(get_nodes_block(node));
704 ir_node *new_op = be_transform_node(op);
706 /* Note: Not(Eor()) is normalize in firm localopts already so
707 * we don't match it for xnor here */
709 /* Not can be represented with xnor 0, n */
710 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
713 static ir_node *gen_helper_bitop(ir_node *node,
714 new_binop_reg_func new_reg,
715 new_binop_imm_func new_imm,
716 new_binop_reg_func new_not_reg,
717 new_binop_imm_func new_not_imm)
719 ir_node *op1 = get_binop_left(node);
720 ir_node *op2 = get_binop_right(node);
722 return gen_helper_binop_args(node, op2, get_Not_op(op1),
724 new_not_reg, new_not_imm);
727 return gen_helper_binop_args(node, op1, get_Not_op(op2),
729 new_not_reg, new_not_imm);
731 return gen_helper_binop_args(node, op1, op2,
732 MATCH_MODE_NEUTRAL | MATCH_COMMUTATIVE,
736 static ir_node *gen_And(ir_node *node)
738 return gen_helper_bitop(node,
739 new_bd_sparc_And_reg,
740 new_bd_sparc_And_imm,
741 new_bd_sparc_AndN_reg,
742 new_bd_sparc_AndN_imm);
745 static ir_node *gen_Or(ir_node *node)
747 return gen_helper_bitop(node,
750 new_bd_sparc_OrN_reg,
751 new_bd_sparc_OrN_imm);
754 static ir_node *gen_Eor(ir_node *node)
756 return gen_helper_bitop(node,
757 new_bd_sparc_Xor_reg,
758 new_bd_sparc_Xor_imm,
759 new_bd_sparc_XNor_reg,
760 new_bd_sparc_XNor_imm);
763 static ir_node *gen_Shl(ir_node *node)
765 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
768 static ir_node *gen_Shr(ir_node *node)
770 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
773 static ir_node *gen_Shrs(ir_node *node)
775 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
779 * Transforms a Minus node.
781 static ir_node *gen_Minus(ir_node *node)
783 ir_mode *mode = get_irn_mode(node);
790 if (mode_is_float(mode)) {
791 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
792 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
794 block = be_transform_node(get_nodes_block(node));
795 dbgi = get_irn_dbg_info(node);
796 op = get_Minus_op(node);
797 new_op = be_transform_node(op);
799 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
803 * Create an entity for a given (floating point) tarval
805 static ir_entity *create_float_const_entity(ir_tarval *tv)
807 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
808 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
809 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
810 ir_initializer_t *initializer;
818 mode = get_tarval_mode(tv);
819 type = get_type_for_mode(mode);
820 glob = get_glob_type();
821 entity = new_entity(glob, id_unique("C%u"), type);
822 set_entity_visibility(entity, ir_visibility_private);
823 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
825 initializer = create_initializer_tarval(tv);
826 set_entity_initializer(entity, initializer);
828 pmap_insert(isa->constants, tv, entity);
832 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
834 ir_entity *entity = create_float_const_entity(tv);
835 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
836 ir_node *mem = new_r_NoMem(current_ir_graph);
837 ir_mode *mode = get_tarval_mode(tv);
839 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
840 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
842 set_irn_pinned(new_op, op_pin_state_floats);
846 static ir_node *gen_Const(ir_node *node)
848 ir_node *block = be_transform_node(get_nodes_block(node));
849 ir_mode *mode = get_irn_mode(node);
850 dbg_info *dbgi = get_irn_dbg_info(node);
851 ir_tarval *tv = get_Const_tarval(node);
854 if (mode_is_float(mode)) {
855 return gen_float_const(dbgi, block, tv);
858 value = get_tarval_long(tv);
861 } else if (sparc_is_value_imm_encodeable(value)) {
862 return new_bd_sparc_Or_imm(dbgi, block, get_g0(), NULL, value);
864 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
865 if ((value & 0x3ff) != 0) {
866 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
873 static ir_mode *get_cmp_mode(ir_node *b_value)
877 if (!is_Cmp(b_value))
878 panic("can't determine cond signednes (no cmp)");
879 op = get_Cmp_left(b_value);
880 return get_irn_mode(op);
883 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
886 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
887 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
891 static ir_node *gen_SwitchJmp(ir_node *node)
893 dbg_info *dbgi = get_irn_dbg_info(node);
894 ir_node *block = be_transform_node(get_nodes_block(node));
895 ir_node *selector = get_Cond_selector(node);
896 ir_node *new_selector = be_transform_node(selector);
897 long default_pn = get_Cond_default_proj(node);
899 ir_node *table_address;
904 /* switch with smaller mode not implemented yet */
905 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
907 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
908 set_entity_visibility(entity, ir_visibility_private);
909 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
911 /* TODO: this code does not construct code to check for access
912 * out-of bounds of the jumptable yet. I think we should put this stuff
913 * into the switch_lowering phase to get some additional optimisations
916 /* construct base address */
917 table_address = make_address(dbgi, block, entity, 0);
919 index = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
920 /* load from jumptable */
921 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, index,
922 new_r_NoMem(current_ir_graph),
924 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
926 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
929 static ir_node *gen_Cond(ir_node *node)
931 ir_node *selector = get_Cond_selector(node);
932 ir_mode *mode = get_irn_mode(selector);
937 ir_relation relation;
941 if (mode != mode_b) {
942 return gen_SwitchJmp(node);
945 // regular if/else jumps
946 assert(is_Cmp(selector));
948 cmp_mode = get_cmp_mode(selector);
950 block = be_transform_node(get_nodes_block(node));
951 dbgi = get_irn_dbg_info(node);
952 flag_node = be_transform_node(selector);
953 relation = get_Cmp_relation(selector);
954 is_unsigned = !mode_is_signed(cmp_mode);
955 if (mode_is_float(cmp_mode)) {
956 assert(!is_unsigned);
957 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
959 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
966 static ir_node *gen_Cmp(ir_node *node)
968 ir_node *op1 = get_Cmp_left(node);
969 ir_node *op2 = get_Cmp_right(node);
970 ir_mode *cmp_mode = get_irn_mode(op1);
971 assert(get_irn_mode(op2) == cmp_mode);
973 if (mode_is_float(cmp_mode)) {
974 ir_node *block = be_transform_node(get_nodes_block(node));
975 dbg_info *dbgi = get_irn_dbg_info(node);
976 ir_node *new_op1 = be_transform_node(op1);
977 ir_node *new_op2 = be_transform_node(op2);
978 unsigned bits = get_mode_size_bits(cmp_mode);
980 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
981 } else if (bits == 64) {
982 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
985 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
989 /* when we compare a bitop like and,or,... with 0 then we can directly use
990 * the bitopcc variant.
991 * Currently we only do this when we're the only user of the node...
993 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
995 return gen_helper_bitop(op1,
996 new_bd_sparc_AndCCZero_reg,
997 new_bd_sparc_AndCCZero_imm,
998 new_bd_sparc_AndNCCZero_reg,
999 new_bd_sparc_AndNCCZero_imm);
1000 } else if (is_Or(op1)) {
1001 return gen_helper_bitop(op1,
1002 new_bd_sparc_OrCCZero_reg,
1003 new_bd_sparc_OrCCZero_imm,
1004 new_bd_sparc_OrNCCZero_reg,
1005 new_bd_sparc_OrNCCZero_imm);
1006 } else if (is_Eor(op1)) {
1007 return gen_helper_bitop(op1,
1008 new_bd_sparc_XorCCZero_reg,
1009 new_bd_sparc_XorCCZero_imm,
1010 new_bd_sparc_XNorCCZero_reg,
1011 new_bd_sparc_XNorCCZero_imm);
1015 /* integer compare */
1016 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1017 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1021 * Transforms a SymConst node.
1023 static ir_node *gen_SymConst(ir_node *node)
1025 ir_entity *entity = get_SymConst_entity(node);
1026 dbg_info *dbgi = get_irn_dbg_info(node);
1027 ir_node *block = get_nodes_block(node);
1028 ir_node *new_block = be_transform_node(block);
1029 return make_address(dbgi, new_block, entity, 0);
1032 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1033 ir_mode *src_mode, ir_mode *dst_mode)
1035 unsigned src_bits = get_mode_size_bits(src_mode);
1036 unsigned dst_bits = get_mode_size_bits(dst_mode);
1037 if (src_bits == 32) {
1038 if (dst_bits == 64) {
1039 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1041 assert(dst_bits == 128);
1042 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1044 } else if (src_bits == 64) {
1045 if (dst_bits == 32) {
1046 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1048 assert(dst_bits == 128);
1049 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1052 assert(src_bits == 128);
1053 if (dst_bits == 32) {
1054 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1056 assert(dst_bits == 64);
1057 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1062 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1066 unsigned bits = get_mode_size_bits(src_mode);
1068 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1069 } else if (bits == 64) {
1070 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1072 assert(bits == 128);
1073 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1077 ir_graph *irg = get_irn_irg(block);
1078 ir_node *sp = get_irg_frame(irg);
1079 ir_node *nomem = new_r_NoMem(irg);
1080 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1082 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1084 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1085 set_irn_pinned(stf, op_pin_state_floats);
1086 set_irn_pinned(ld, op_pin_state_floats);
1091 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1094 ir_graph *irg = get_irn_irg(block);
1095 ir_node *sp = get_irg_frame(irg);
1096 ir_node *nomem = new_r_NoMem(irg);
1097 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1098 mode_gp, NULL, 0, true);
1099 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1101 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1102 unsigned bits = get_mode_size_bits(dst_mode);
1103 set_irn_pinned(st, op_pin_state_floats);
1104 set_irn_pinned(ldf, op_pin_state_floats);
1107 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1108 } else if (bits == 64) {
1109 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1111 assert(bits == 128);
1112 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1116 static ir_node *gen_Conv(ir_node *node)
1118 ir_node *block = be_transform_node(get_nodes_block(node));
1119 ir_node *op = get_Conv_op(node);
1120 ir_mode *src_mode = get_irn_mode(op);
1121 ir_mode *dst_mode = get_irn_mode(node);
1122 dbg_info *dbg = get_irn_dbg_info(node);
1125 int src_bits = get_mode_size_bits(src_mode);
1126 int dst_bits = get_mode_size_bits(dst_mode);
1128 if (src_mode == mode_b)
1129 panic("ConvB not lowered %+F", node);
1131 new_op = be_transform_node(op);
1132 if (src_mode == dst_mode)
1135 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1136 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1138 if (mode_is_float(src_mode)) {
1139 if (mode_is_float(dst_mode)) {
1140 /* float -> float conv */
1141 return create_fftof(dbg, block, new_op, src_mode, dst_mode);
1143 /* float -> int conv */
1144 if (!mode_is_signed(dst_mode))
1145 panic("float to unsigned not implemented yet");
1146 return create_ftoi(dbg, block, new_op, src_mode);
1149 /* int -> float conv */
1150 if (src_bits < 32) {
1151 new_op = gen_extension(dbg, block, new_op, src_mode);
1152 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1153 panic("unsigned to float not lowered!");
1155 return create_itof(dbg, block, new_op, dst_mode);
1157 } else if (src_mode == mode_b) {
1158 panic("ConvB not lowered %+F", node);
1159 } else { /* complete in gp registers */
1163 if (src_bits == dst_bits) {
1164 /* kill unnecessary conv */
1168 if (src_bits < dst_bits) {
1169 min_bits = src_bits;
1170 min_mode = src_mode;
1172 min_bits = dst_bits;
1173 min_mode = dst_mode;
1176 if (upper_bits_clean(new_op, min_mode)) {
1180 if (mode_is_signed(min_mode)) {
1181 return gen_sign_extension(dbg, block, new_op, min_bits);
1183 return gen_zero_extension(dbg, block, new_op, min_bits);
1188 static ir_node *gen_Unknown(ir_node *node)
1190 /* just produce a 0 */
1191 ir_mode *mode = get_irn_mode(node);
1192 if (mode_is_float(mode)) {
1193 ir_node *block = be_transform_node(get_nodes_block(node));
1194 return gen_float_const(NULL, block, get_mode_null(mode));
1195 } else if (mode_needs_gp_reg(mode)) {
1199 panic("Unexpected Unknown mode");
1203 * Produces the type which sits between the stack args and the locals on the
1206 static ir_type *sparc_get_between_type(void)
1208 static ir_type *between_type = NULL;
1209 static ir_type *between_type0 = NULL;
1211 if (cconv->omit_fp) {
1212 if (between_type0 == NULL) {
1214 = new_type_class(new_id_from_str("sparc_between_type"));
1215 set_type_size_bytes(between_type0, 0);
1217 return between_type0;
1220 if (between_type == NULL) {
1221 between_type = new_type_class(new_id_from_str("sparc_between_type"));
1222 set_type_size_bytes(between_type, SPARC_MIN_STACKSIZE);
1225 return between_type;
1228 static void create_stacklayout(ir_graph *irg)
1230 ir_entity *entity = get_irg_entity(irg);
1231 ir_type *function_type = get_entity_type(entity);
1232 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1237 /* calling conventions must be decided by now */
1238 assert(cconv != NULL);
1240 /* construct argument type */
1241 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1242 n_params = get_method_n_params(function_type);
1243 for (p = 0; p < n_params; ++p) {
1244 reg_or_stackslot_t *param = &cconv->parameters[p];
1248 if (param->type == NULL)
1251 snprintf(buf, sizeof(buf), "param_%d", p);
1252 id = new_id_from_str(buf);
1253 param->entity = new_entity(arg_type, id, param->type);
1254 set_entity_offset(param->entity, param->offset);
1257 memset(layout, 0, sizeof(*layout));
1259 layout->frame_type = get_irg_frame_type(irg);
1260 layout->between_type = sparc_get_between_type();
1261 layout->arg_type = arg_type;
1262 layout->initial_offset = 0;
1263 layout->initial_bias = 0;
1264 layout->stack_dir = -1;
1265 layout->sp_relative = cconv->omit_fp;
1267 assert(N_FRAME_TYPES == 3);
1268 layout->order[0] = layout->frame_type;
1269 layout->order[1] = layout->between_type;
1270 layout->order[2] = layout->arg_type;
1274 * transform the start node to the prolog code
1276 static ir_node *gen_Start(ir_node *node)
1278 ir_graph *irg = get_irn_irg(node);
1279 ir_entity *entity = get_irg_entity(irg);
1280 ir_type *function_type = get_entity_type(entity);
1281 ir_node *block = get_nodes_block(node);
1282 ir_node *new_block = be_transform_node(block);
1283 dbg_info *dbgi = get_irn_dbg_info(node);
1289 /* stackpointer is important at function prolog */
1290 be_prolog_add_reg(abihelper, sp_reg,
1291 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1292 be_prolog_add_reg(abihelper, &sparc_registers[REG_G0],
1293 arch_register_req_type_ignore);
1294 /* function parameters in registers */
1295 for (i = 0; i < get_method_n_params(function_type); ++i) {
1296 const reg_or_stackslot_t *param = &cconv->parameters[i];
1297 if (param->reg0 != NULL) {
1298 be_prolog_add_reg(abihelper, param->reg0,
1299 arch_register_req_type_none);
1301 if (param->reg1 != NULL) {
1302 be_prolog_add_reg(abihelper, param->reg1,
1303 arch_register_req_type_none);
1306 /* we need the values of the callee saves (Note: non omit-fp mode has no
1308 if (cconv->omit_fp) {
1309 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1311 for (c = 0; c < n_callee_saves; ++c) {
1312 be_prolog_add_reg(abihelper, omit_fp_callee_saves[c],
1313 arch_register_req_type_none);
1316 be_prolog_add_reg(abihelper, fp_reg, arch_register_req_type_ignore);
1319 start = be_prolog_create_start(abihelper, dbgi, new_block);
1320 mem = be_prolog_get_memory(abihelper);
1321 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1323 if (!cconv->omit_fp) {
1324 ir_node *save = new_bd_sparc_Save_imm(NULL, block, sp, NULL,
1325 -SPARC_MIN_STACKSIZE);
1326 arch_irn_add_flags(save, arch_irn_flags_prolog);
1327 arch_set_irn_register(save, sp_reg);
1332 sp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1333 arch_irn_add_flags(sp, arch_irn_flags_prolog);
1334 be_prolog_set_reg_value(abihelper, sp_reg, sp);
1335 be_prolog_set_memory(abihelper, mem);
1340 static ir_node *get_stack_pointer_for(ir_node *node)
1342 /* get predecessor in stack_order list */
1343 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1344 ir_node *stack_pred_transformed;
1347 if (stack_pred == NULL) {
1348 /* first stack user in the current block. We can simply use the
1349 * initial sp_proj for it */
1350 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1354 stack_pred_transformed = be_transform_node(stack_pred);
1355 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1356 if (stack == NULL) {
1357 return get_stack_pointer_for(stack_pred);
1364 * transform a Return node into epilogue code + return statement
1366 static ir_node *gen_Return(ir_node *node)
1368 ir_node *block = get_nodes_block(node);
1369 ir_node *new_block = be_transform_node(block);
1370 dbg_info *dbgi = get_irn_dbg_info(node);
1371 ir_node *mem = get_Return_mem(node);
1372 ir_node *new_mem = be_transform_node(mem);
1373 ir_node *sp = get_stack_pointer_for(node);
1374 size_t n_res = get_Return_n_ress(node);
1378 be_epilog_begin(abihelper);
1379 be_epilog_set_memory(abihelper, new_mem);
1380 /* connect stack pointer with initial stack pointer. fix_stack phase
1381 will later serialize all stack pointer adjusting nodes */
1382 be_epilog_add_reg(abihelper, sp_reg,
1383 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1387 for (i = 0; i < n_res; ++i) {
1388 ir_node *res_value = get_Return_res(node, i);
1389 ir_node *new_res_value = be_transform_node(res_value);
1390 const reg_or_stackslot_t *slot = &cconv->results[i];
1391 const arch_register_t *reg = slot->reg0;
1392 assert(slot->reg1 == NULL);
1393 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none,
1397 if (cconv->omit_fp) {
1398 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1400 for (i = 0; i < n_callee_saves; ++i) {
1401 const arch_register_t *reg = omit_fp_callee_saves[i];
1403 = be_prolog_get_reg_value(abihelper, reg);
1404 be_epilog_add_reg(abihelper, reg, arch_register_req_type_none,
1409 /* we need a restore instruction */
1410 if (!cconv->omit_fp) {
1411 ir_node *fp = be_prolog_get_reg_value(abihelper, fp_reg);
1412 ir_node *restore = new_bd_sparc_RestoreZero(NULL, block, fp);
1413 arch_irn_add_flags(restore, arch_irn_flags_epilog);
1414 arch_set_irn_register(restore, sp_reg);
1415 be_epilog_set_reg_value(abihelper, sp_reg, restore);
1417 /* epilog code: an incsp */
1418 sp = be_epilog_get_reg_value(abihelper, sp_reg);
1419 sp = be_new_IncSP(sp_reg, new_block, sp,
1420 BE_STACK_FRAME_SIZE_SHRINK, 0);
1421 arch_irn_add_flags(sp, arch_irn_flags_epilog);
1422 be_epilog_set_reg_value(abihelper, sp_reg, sp);
1425 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1426 arch_irn_add_flags(bereturn, arch_irn_flags_epilog);
1431 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1432 ir_node *value0, ir_node *value1)
1434 ir_graph *irg = current_ir_graph;
1435 ir_node *sp = get_irg_frame(irg);
1436 ir_node *nomem = new_r_NoMem(irg);
1437 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1438 mode_gp, NULL, 0, true);
1442 set_irn_pinned(st, op_pin_state_floats);
1444 if (value1 != NULL) {
1445 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1446 mode_gp, NULL, 4, true);
1447 ir_node *in[2] = { st, st1 };
1448 ir_node *sync = new_r_Sync(block, 2, in);
1449 set_irn_pinned(st1, op_pin_state_floats);
1457 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1458 set_irn_pinned(ldf, op_pin_state_floats);
1460 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1463 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1464 ir_node *node, ir_mode *float_mode,
1467 ir_graph *irg = current_ir_graph;
1468 ir_node *stack = get_irg_frame(irg);
1469 ir_node *nomem = new_r_NoMem(irg);
1470 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1472 int bits = get_mode_size_bits(float_mode);
1474 set_irn_pinned(stf, op_pin_state_floats);
1476 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1477 set_irn_pinned(ld, op_pin_state_floats);
1478 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1481 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1483 set_irn_pinned(ld, op_pin_state_floats);
1484 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1486 arch_irn_add_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1487 arch_irn_add_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1494 static ir_node *gen_Call(ir_node *node)
1496 ir_graph *irg = get_irn_irg(node);
1497 ir_node *callee = get_Call_ptr(node);
1498 ir_node *block = get_nodes_block(node);
1499 ir_node *new_block = be_transform_node(block);
1500 ir_node *mem = get_Call_mem(node);
1501 ir_node *new_mem = be_transform_node(mem);
1502 dbg_info *dbgi = get_irn_dbg_info(node);
1503 ir_type *type = get_Call_type(node);
1504 size_t n_params = get_Call_n_params(node);
1505 size_t n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1506 /* max inputs: memory, callee, register arguments */
1507 int max_inputs = 2 + n_param_regs;
1508 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1509 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1510 struct obstack *obst = be_get_be_obst(irg);
1511 const arch_register_req_t **in_req
1512 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1513 calling_convention_t *cconv
1514 = sparc_decide_calling_convention(type, NULL);
1518 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1519 ir_entity *entity = NULL;
1520 ir_node *new_frame = get_stack_pointer_for(node);
1529 assert(n_params == get_method_n_params(type));
1531 /* construct arguments */
1534 in_req[in_arity] = arch_no_register_req;
1538 /* stack pointer input */
1539 /* construct an IncSP -> we have to always be sure that the stack is
1540 * aligned even if we don't push arguments on it */
1541 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1542 cconv->param_stack_size, 1);
1543 in_req[in_arity] = sp_reg->single_req;
1544 in[in_arity] = incsp;
1548 for (p = 0; p < n_params; ++p) {
1549 ir_node *value = get_Call_param(node, p);
1550 ir_node *new_value = be_transform_node(value);
1551 const reg_or_stackslot_t *param = &cconv->parameters[p];
1552 ir_type *param_type = get_method_param_type(type, p);
1553 ir_mode *mode = get_type_mode(param_type);
1554 ir_node *new_values[2];
1557 if (mode_is_float(mode) && param->reg0 != NULL) {
1558 unsigned size_bits = get_mode_size_bits(mode);
1559 assert(size_bits <= 64);
1560 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1562 new_values[0] = new_value;
1563 new_values[1] = NULL;
1566 /* put value into registers */
1567 if (param->reg0 != NULL) {
1568 in[in_arity] = new_values[0];
1569 in_req[in_arity] = param->reg0->single_req;
1571 if (new_values[1] == NULL)
1574 if (param->reg1 != NULL) {
1575 assert(new_values[1] != NULL);
1576 in[in_arity] = new_values[1];
1577 in_req[in_arity] = param->reg1->single_req;
1582 /* we need a store if we're here */
1583 if (new_values[1] != NULL) {
1584 new_value = new_values[1];
1588 /* create a parameter frame if necessary */
1589 if (mode_is_float(mode)) {
1590 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1591 mode, NULL, param->offset, true);
1593 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1594 new_mem, mode, NULL, param->offset, true);
1596 set_irn_pinned(str, op_pin_state_floats);
1597 sync_ins[sync_arity++] = str;
1599 assert(in_arity <= max_inputs);
1601 /* construct memory input */
1602 if (sync_arity == 0) {
1603 in[mem_pos] = new_mem;
1604 } else if (sync_arity == 1) {
1605 in[mem_pos] = sync_ins[0];
1607 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1610 if (is_SymConst(callee)) {
1611 entity = get_SymConst_entity(callee);
1613 in[in_arity] = be_transform_node(callee);
1614 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1622 out_arity = 1 + n_caller_saves;
1624 /* create call node */
1625 if (entity != NULL) {
1626 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1629 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity);
1631 arch_set_in_register_reqs(res, in_req);
1633 /* create output register reqs */
1635 arch_set_out_register_req(res, o++, arch_no_register_req);
1636 for (i = 0; i < n_caller_saves; ++i) {
1637 const arch_register_t *reg = caller_saves[i];
1638 arch_set_out_register_req(res, o++, reg->single_req);
1640 assert(o == out_arity);
1642 /* copy pinned attribute */
1643 set_irn_pinned(res, get_irn_pinned(node));
1645 /* IncSP to destroy the call stackframe */
1646 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1647 /* if we are the last IncSP producer in a block then we have to keep
1649 * Note: This here keeps all producers which is more than necessary */
1650 add_irn_dep(incsp, res);
1653 pmap_insert(node_to_stack, node, incsp);
1655 sparc_free_calling_convention(cconv);
1659 static ir_node *gen_Sel(ir_node *node)
1661 dbg_info *dbgi = get_irn_dbg_info(node);
1662 ir_node *block = get_nodes_block(node);
1663 ir_node *new_block = be_transform_node(block);
1664 ir_node *ptr = get_Sel_ptr(node);
1665 ir_node *new_ptr = be_transform_node(ptr);
1666 ir_entity *entity = get_Sel_entity(node);
1668 /* must be the frame pointer all other sels must have been lowered
1670 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1671 /* we should not have value types from parameters anymore - they should be
1673 assert(get_entity_owner(entity) !=
1674 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1676 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1679 static const arch_register_req_t float1_req = {
1680 arch_register_req_type_normal,
1681 &sparc_reg_classes[CLASS_sparc_fp],
1687 static const arch_register_req_t float2_req = {
1688 arch_register_req_type_normal | arch_register_req_type_aligned,
1689 &sparc_reg_classes[CLASS_sparc_fp],
1695 static const arch_register_req_t float4_req = {
1696 arch_register_req_type_normal | arch_register_req_type_aligned,
1697 &sparc_reg_classes[CLASS_sparc_fp],
1705 static const arch_register_req_t *get_float_req(ir_mode *mode)
1707 unsigned bits = get_mode_size_bits(mode);
1709 assert(mode_is_float(mode));
1712 } else if (bits == 64) {
1715 assert(bits == 128);
1721 * Transform some Phi nodes
1723 static ir_node *gen_Phi(ir_node *node)
1725 const arch_register_req_t *req;
1726 ir_node *block = be_transform_node(get_nodes_block(node));
1727 ir_graph *irg = current_ir_graph;
1728 dbg_info *dbgi = get_irn_dbg_info(node);
1729 ir_mode *mode = get_irn_mode(node);
1732 if (mode_needs_gp_reg(mode)) {
1733 /* we shouldn't have any 64bit stuff around anymore */
1734 assert(get_mode_size_bits(mode) <= 32);
1735 /* all integer operations are on 32bit registers now */
1737 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
1738 } else if (mode_is_float(mode)) {
1740 req = get_float_req(mode);
1742 req = arch_no_register_req;
1745 /* phi nodes allow loops, so we use the old arguments for now
1746 * and fix this later */
1747 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1748 copy_node_attr(irg, node, phi);
1749 be_duplicate_deps(node, phi);
1750 arch_set_out_register_req(phi, 0, req);
1751 be_enqueue_preds(node);
1756 * Transform a Proj from a Load.
1758 static ir_node *gen_Proj_Load(ir_node *node)
1760 ir_node *load = get_Proj_pred(node);
1761 ir_node *new_load = be_transform_node(load);
1762 dbg_info *dbgi = get_irn_dbg_info(node);
1763 long pn = get_Proj_proj(node);
1765 /* renumber the proj */
1766 switch (get_sparc_irn_opcode(new_load)) {
1768 /* handle all gp loads equal: they have the same proj numbers. */
1769 if (pn == pn_Load_res) {
1770 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
1771 } else if (pn == pn_Load_M) {
1772 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1776 if (pn == pn_Load_res) {
1777 return new_rd_Proj(dbgi, new_load, mode_fp, pn_sparc_Ldf_res);
1778 } else if (pn == pn_Load_M) {
1779 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1785 panic("Unsupported Proj from Load");
1788 static ir_node *gen_Proj_Store(ir_node *node)
1790 ir_node *store = get_Proj_pred(node);
1791 ir_node *new_store = be_transform_node(store);
1792 long pn = get_Proj_proj(node);
1794 /* renumber the proj */
1795 switch (get_sparc_irn_opcode(new_store)) {
1797 if (pn == pn_Store_M) {
1802 if (pn == pn_Store_M) {
1809 panic("Unsupported Proj from Store");
1813 * Transform the Projs from a Cmp.
1815 static ir_node *gen_Proj_Cmp(ir_node *node)
1818 panic("not implemented");
1822 * transform Projs from a Div
1824 static ir_node *gen_Proj_Div(ir_node *node)
1826 ir_node *pred = get_Proj_pred(node);
1827 ir_node *new_pred = be_transform_node(pred);
1828 long pn = get_Proj_proj(node);
1830 assert(is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)
1831 || is_sparc_fdiv(new_pred));
1832 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
1833 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
1834 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
1835 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
1838 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_res);
1840 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
1844 panic("Unsupported Proj from Div");
1847 static ir_node *get_frame_base(void)
1849 const arch_register_t *reg = cconv->omit_fp ? sp_reg : fp_reg;
1850 return be_prolog_get_reg_value(abihelper, reg);
1853 static ir_node *gen_Proj_Start(ir_node *node)
1855 ir_node *block = get_nodes_block(node);
1856 ir_node *new_block = be_transform_node(block);
1857 long pn = get_Proj_proj(node);
1858 /* make sure prolog is constructed */
1859 be_transform_node(get_Proj_pred(node));
1861 switch ((pn_Start) pn) {
1862 case pn_Start_X_initial_exec:
1863 /* exchange ProjX with a jump */
1864 return new_bd_sparc_Ba(NULL, new_block);
1866 return be_prolog_get_memory(abihelper);
1867 case pn_Start_T_args:
1868 /* we should never need this explicitely */
1869 return new_r_Bad(get_irn_irg(block));
1870 case pn_Start_P_frame_base:
1871 return get_frame_base();
1872 case pn_Start_P_tls:
1873 return new_r_Bad(current_ir_graph);
1877 panic("Unexpected start proj: %ld\n", pn);
1880 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1882 long pn = get_Proj_proj(node);
1883 ir_node *block = get_nodes_block(node);
1884 ir_node *new_block = be_transform_node(block);
1885 ir_entity *entity = get_irg_entity(current_ir_graph);
1886 ir_type *method_type = get_entity_type(entity);
1887 ir_type *param_type = get_method_param_type(method_type, pn);
1888 const reg_or_stackslot_t *param;
1890 /* Proj->Proj->Start must be a method argument */
1891 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1893 param = &cconv->parameters[pn];
1895 if (param->reg0 != NULL) {
1896 /* argument transmitted in register */
1897 ir_mode *mode = get_type_mode(param_type);
1898 const arch_register_t *reg = param->reg0;
1899 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1901 if (mode_is_float(mode)) {
1902 ir_node *value1 = NULL;
1904 if (param->reg1 != NULL) {
1905 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1906 } else if (param->entity != NULL) {
1907 ir_node *fp = be_prolog_get_reg_value(abihelper, fp_reg);
1908 ir_node *mem = be_prolog_get_memory(abihelper);
1909 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
1910 mode_gp, param->entity,
1912 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1915 /* convert integer value to float */
1916 value = bitcast_int_to_float(NULL, new_block, value, value1);
1920 /* argument transmitted on stack */
1921 ir_node *mem = be_prolog_get_memory(abihelper);
1922 ir_mode *mode = get_type_mode(param->type);
1923 ir_node *base = get_frame_base();
1927 if (mode_is_float(mode)) {
1928 load = create_ldf(NULL, new_block, base, mem, mode,
1929 param->entity, 0, true);
1930 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
1932 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
1933 param->entity, 0, true);
1934 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1936 set_irn_pinned(load, op_pin_state_floats);
1942 static ir_node *gen_Proj_Call(ir_node *node)
1944 long pn = get_Proj_proj(node);
1945 ir_node *call = get_Proj_pred(node);
1946 ir_node *new_call = be_transform_node(call);
1948 switch ((pn_Call) pn) {
1950 return new_r_Proj(new_call, mode_M, 0);
1951 case pn_Call_X_regular:
1952 case pn_Call_X_except:
1953 case pn_Call_T_result:
1954 case pn_Call_P_value_res_base:
1958 panic("Unexpected Call proj %ld\n", pn);
1962 * Finds number of output value of a mode_T node which is constrained to
1963 * a single specific register.
1965 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1967 int n_outs = arch_irn_get_n_outs(node);
1970 for (o = 0; o < n_outs; ++o) {
1971 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1972 if (req == reg->single_req)
1978 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1980 long pn = get_Proj_proj(node);
1981 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1982 ir_node *new_call = be_transform_node(call);
1983 ir_type *function_type = get_Call_type(call);
1984 calling_convention_t *cconv
1985 = sparc_decide_calling_convention(function_type, NULL);
1986 const reg_or_stackslot_t *res = &cconv->results[pn];
1987 const arch_register_t *reg = res->reg0;
1991 assert(res->reg0 != NULL && res->reg1 == NULL);
1992 regn = find_out_for_reg(new_call, reg);
1994 panic("Internal error in calling convention for return %+F", node);
1996 mode = res->reg0->reg_class->mode;
1998 sparc_free_calling_convention(cconv);
2000 return new_r_Proj(new_call, mode, regn);
2004 * Transform a Proj node.
2006 static ir_node *gen_Proj(ir_node *node)
2008 ir_node *pred = get_Proj_pred(node);
2010 switch (get_irn_opcode(pred)) {
2012 return gen_Proj_Store(node);
2014 return gen_Proj_Load(node);
2016 return gen_Proj_Call(node);
2018 return gen_Proj_Cmp(node);
2020 return be_duplicate_node(node);
2022 return gen_Proj_Div(node);
2024 return gen_Proj_Start(node);
2026 ir_node *pred_pred = get_Proj_pred(pred);
2027 if (is_Call(pred_pred)) {
2028 return gen_Proj_Proj_Call(node);
2029 } else if (is_Start(pred_pred)) {
2030 return gen_Proj_Proj_Start(node);
2035 panic("code selection didn't expect Proj after %+F\n", pred);
2042 static ir_node *gen_Jmp(ir_node *node)
2044 ir_node *block = get_nodes_block(node);
2045 ir_node *new_block = be_transform_node(block);
2046 dbg_info *dbgi = get_irn_dbg_info(node);
2048 return new_bd_sparc_Ba(dbgi, new_block);
2052 * configure transformation callbacks
2054 static void sparc_register_transformers(void)
2056 be_start_transform_setup();
2058 be_set_transform_function(op_Add, gen_Add);
2059 be_set_transform_function(op_And, gen_And);
2060 be_set_transform_function(op_Call, gen_Call);
2061 be_set_transform_function(op_Cmp, gen_Cmp);
2062 be_set_transform_function(op_Cond, gen_Cond);
2063 be_set_transform_function(op_Const, gen_Const);
2064 be_set_transform_function(op_Conv, gen_Conv);
2065 be_set_transform_function(op_Div, gen_Div);
2066 be_set_transform_function(op_Eor, gen_Eor);
2067 be_set_transform_function(op_Jmp, gen_Jmp);
2068 be_set_transform_function(op_Load, gen_Load);
2069 be_set_transform_function(op_Minus, gen_Minus);
2070 be_set_transform_function(op_Mul, gen_Mul);
2071 be_set_transform_function(op_Mulh, gen_Mulh);
2072 be_set_transform_function(op_Not, gen_Not);
2073 be_set_transform_function(op_Or, gen_Or);
2074 be_set_transform_function(op_Phi, gen_Phi);
2075 be_set_transform_function(op_Proj, gen_Proj);
2076 be_set_transform_function(op_Return, gen_Return);
2077 be_set_transform_function(op_Sel, gen_Sel);
2078 be_set_transform_function(op_Shl, gen_Shl);
2079 be_set_transform_function(op_Shr, gen_Shr);
2080 be_set_transform_function(op_Shrs, gen_Shrs);
2081 be_set_transform_function(op_Start, gen_Start);
2082 be_set_transform_function(op_Store, gen_Store);
2083 be_set_transform_function(op_Sub, gen_Sub);
2084 be_set_transform_function(op_SymConst, gen_SymConst);
2085 be_set_transform_function(op_Unknown, gen_Unknown);
2087 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2091 * Transform a Firm graph into a SPARC graph.
2093 void sparc_transform_graph(ir_graph *irg)
2095 ir_entity *entity = get_irg_entity(irg);
2096 ir_type *frame_type;
2098 sparc_register_transformers();
2100 node_to_stack = pmap_create();
2107 abihelper = be_abihelper_prepare(irg);
2108 be_collect_stacknodes(abihelper);
2109 cconv = sparc_decide_calling_convention(get_entity_type(entity), irg);
2110 create_stacklayout(irg);
2112 be_transform_graph(irg, NULL);
2114 be_abihelper_finish(abihelper);
2115 sparc_free_calling_convention(cconv);
2117 frame_type = get_irg_frame_type(irg);
2118 if (get_type_state(frame_type) == layout_undefined)
2119 default_layout_compound_type(frame_type);
2121 pmap_destroy(node_to_stack);
2122 node_to_stack = NULL;
2124 be_add_missing_keeps(irg);
2126 /* do code placement, to optimize the position of constants */
2130 void sparc_init_transform(void)
2132 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");