2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
30 #include "irgraph_t.h"
36 #include "iroptimize.h"
42 #include "../benode.h"
44 #include "../beutil.h"
45 #include "../betranshlp.h"
46 #include "../beabihelper.h"
47 #include "bearch_sparc_t.h"
49 #include "sparc_nodes_attr.h"
50 #include "sparc_transform.h"
51 #include "sparc_new_nodes.h"
52 #include "gen_sparc_new_nodes.h"
54 #include "gen_sparc_regalloc_if.h"
55 #include "sparc_cconv.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static beabi_helper_env_t *abihelper;
62 static const arch_register_t *sp_reg = &sparc_gp_regs[REG_SP];
63 static const arch_register_t *fp_reg = &sparc_gp_regs[REG_FRAME_POINTER];
64 static calling_convention_t *cconv = NULL;
65 static ir_mode *mode_gp;
66 static ir_mode *mode_fp;
67 static ir_mode *mode_fp2;
68 //static ir_mode *mode_fp4;
69 static pmap *node_to_stack;
71 static inline int mode_needs_gp_reg(ir_mode *mode)
73 return mode_is_int(mode) || mode_is_reference(mode);
77 * Create an And that will zero out upper bits.
79 * @param dbgi debug info
80 * @param block the basic block
81 * @param op the original node
82 * @param src_bits number of lower bits that will remain
84 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
88 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
89 } else if (src_bits == 16) {
90 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
91 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
94 panic("zero extension only supported for 8 and 16 bits");
99 * Generate code for a sign extension.
101 * @param dbgi debug info
102 * @param block the basic block
103 * @param op the original node
104 * @param src_bits number of lower bits that will remain
106 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
109 int shift_width = 32 - src_bits;
110 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
111 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
116 * returns true if it is assured, that the upper bits of a node are "clean"
117 * which means for a 16 or 8 bit value, that the upper bits in the register
118 * are 0 for unsigned and a copy of the last significant bit for signed
121 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
123 (void) transformed_node;
130 * Extend a value to 32 bit signed/unsigned depending on its mode.
132 * @param dbgi debug info
133 * @param block the basic block
134 * @param op the original node
135 * @param orig_mode the original mode of op
137 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
140 int bits = get_mode_size_bits(orig_mode);
144 if (mode_is_signed(orig_mode)) {
145 return gen_sign_extension(dbgi, block, op, bits);
147 return gen_zero_extension(dbgi, block, op, bits);
153 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
154 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
155 influence the significant lower bit at
156 all (for cases where mode < 32bit) */
159 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
160 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
161 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
162 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
164 static bool is_value_imm_encodeable(int32_t value)
166 return -4096 <= value && value <= 4095;
170 * checks if a node's value can be encoded as a immediate
172 static bool is_imm_encodeable(const ir_node *node)
178 value = get_tarval_long(get_Const_tarval(node));
179 return is_value_imm_encodeable(value);
182 static bool needs_extension(ir_mode *mode)
184 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
188 * Check, if a given node is a Down-Conv, ie. a integer Conv
189 * from a mode with a mode with more bits to a mode with lesser bits.
190 * Moreover, we return only true if the node has not more than 1 user.
192 * @param node the node
193 * @return non-zero if node is a Down-Conv
195 static bool is_downconv(const ir_node *node)
203 src_mode = get_irn_mode(get_Conv_op(node));
204 dest_mode = get_irn_mode(node);
206 mode_needs_gp_reg(src_mode) &&
207 mode_needs_gp_reg(dest_mode) &&
208 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
211 static ir_node *sparc_skip_downconv(ir_node *node)
213 while (is_downconv(node)) {
214 node = get_Conv_op(node);
220 * helper function for binop operations
222 * @param new_reg register generation function ptr
223 * @param new_imm immediate generation function ptr
225 static ir_node *gen_helper_binop_args(ir_node *node,
226 ir_node *op1, ir_node *op2,
228 new_binop_reg_func new_reg,
229 new_binop_imm_func new_imm)
231 dbg_info *dbgi = get_irn_dbg_info(node);
232 ir_node *block = be_transform_node(get_nodes_block(node));
238 if (flags & MATCH_MODE_NEUTRAL) {
239 op1 = sparc_skip_downconv(op1);
240 op2 = sparc_skip_downconv(op2);
242 mode1 = get_irn_mode(op1);
243 mode2 = get_irn_mode(op2);
245 if (is_imm_encodeable(op2)) {
246 ir_node *new_op1 = be_transform_node(op1);
247 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
248 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
249 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
251 return new_imm(dbgi, block, new_op1, NULL, immediate);
253 new_op2 = be_transform_node(op2);
254 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
255 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
258 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
259 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
260 return new_imm(dbgi, block, new_op2, NULL, immediate);
263 new_op1 = be_transform_node(op1);
264 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
265 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
267 return new_reg(dbgi, block, new_op1, new_op2);
270 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
271 new_binop_reg_func new_reg,
272 new_binop_imm_func new_imm)
274 ir_node *op1 = get_binop_left(node);
275 ir_node *op2 = get_binop_right(node);
276 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
280 * helper function for FP binop operations
282 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
283 new_binop_fp_func new_func_single,
284 new_binop_fp_func new_func_double,
285 new_binop_fp_func new_func_quad)
287 ir_node *block = be_transform_node(get_nodes_block(node));
288 ir_node *op1 = get_binop_left(node);
289 ir_node *new_op1 = be_transform_node(op1);
290 ir_node *op2 = get_binop_right(node);
291 ir_node *new_op2 = be_transform_node(op2);
292 dbg_info *dbgi = get_irn_dbg_info(node);
293 unsigned bits = get_mode_size_bits(mode);
297 return new_func_single(dbgi, block, new_op1, new_op2, mode);
299 return new_func_double(dbgi, block, new_op1, new_op2, mode);
301 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
305 panic("unsupported mode %+F for float op", mode);
308 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
309 new_unop_fp_func new_func_single,
310 new_unop_fp_func new_func_double,
311 new_unop_fp_func new_func_quad)
313 ir_node *block = be_transform_node(get_nodes_block(node));
314 ir_node *op1 = get_binop_left(node);
315 ir_node *new_op1 = be_transform_node(op1);
316 dbg_info *dbgi = get_irn_dbg_info(node);
317 unsigned bits = get_mode_size_bits(mode);
321 return new_func_single(dbgi, block, new_op1, mode);
323 return new_func_double(dbgi, block, new_op1, mode);
325 return new_func_quad(dbgi, block, new_op1, mode);
329 panic("unsupported mode %+F for float op", mode);
332 static ir_node *get_g0(void)
334 return be_prolog_get_reg_value(abihelper, &sparc_gp_regs[REG_G0]);
337 typedef struct address_t {
345 * Match a load/store address
347 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
350 ir_node *ptr2 = NULL;
352 ir_entity *entity = NULL;
355 ir_node *add_right = get_Add_right(base);
356 if (is_Const(add_right)) {
357 base = get_Add_left(base);
358 offset += get_tarval_long(get_Const_tarval(add_right));
361 /* Note that we don't match sub(x, Const) or chains of adds/subs
362 * because this should all be normalized by now */
364 /* we only use the symconst if we're the only user otherwise we probably
365 * won't save anything but produce multiple sethi+or combinations with
366 * just different offsets */
367 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
368 dbg_info *dbgi = get_irn_dbg_info(ptr);
369 ir_node *block = get_nodes_block(ptr);
370 ir_node *new_block = be_transform_node(block);
371 entity = get_SymConst_entity(base);
372 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
373 } else if (use_ptr2 && is_Add(base) && entity == NULL && offset == 0) {
374 ptr2 = be_transform_node(get_Add_right(base));
375 base = be_transform_node(get_Add_left(base));
377 if (is_value_imm_encodeable(offset)) {
378 base = be_transform_node(base);
380 base = be_transform_node(ptr);
386 address->ptr2 = ptr2;
387 address->entity = entity;
388 address->offset = offset;
392 * Creates an sparc Add.
394 * @param node FIRM node
395 * @return the created sparc Add node
397 static ir_node *gen_Add(ir_node *node)
399 ir_mode *mode = get_irn_mode(node);
402 if (mode_is_float(mode)) {
403 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
404 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
407 /* special case: + 0x1000 can be represented as - 0x1000 */
408 right = get_Add_right(node);
409 if (is_Const(right)) {
412 ir_node *left = get_Add_left(node);
413 /* is this simple address arithmetic? then we can let the linker do
414 * the calculation. */
415 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
416 dbg_info *dbgi = get_irn_dbg_info(node);
417 ir_node *block = be_transform_node(get_nodes_block(node));
420 /* the value of use_ptr2 shouldn't matter here */
421 match_address(node, &address, false);
422 assert(is_sparc_SetHi(address.ptr));
423 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
424 address.entity, address.offset);
427 tv = get_Const_tarval(right);
428 val = get_tarval_long(tv);
430 dbg_info *dbgi = get_irn_dbg_info(node);
431 ir_node *block = be_transform_node(get_nodes_block(node));
432 ir_node *op = get_Add_left(node);
433 ir_node *new_op = be_transform_node(op);
434 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
438 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
439 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
443 * Creates an sparc Sub.
445 * @param node FIRM node
446 * @return the created sparc Sub node
448 static ir_node *gen_Sub(ir_node *node)
450 ir_mode *mode = get_irn_mode(node);
452 if (mode_is_float(mode)) {
453 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
454 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
457 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
460 static ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
461 ir_node *mem, ir_mode *mode, ir_entity *entity,
462 long offset, bool is_frame_entity)
464 unsigned bits = get_mode_size_bits(mode);
465 assert(mode_is_float(mode));
467 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
468 offset, is_frame_entity);
469 } else if (bits == 64) {
470 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
471 offset, is_frame_entity);
474 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
475 offset, is_frame_entity);
479 static ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
480 ir_node *ptr, ir_node *mem, ir_mode *mode,
481 ir_entity *entity, long offset,
482 bool is_frame_entity)
484 unsigned bits = get_mode_size_bits(mode);
485 assert(mode_is_float(mode));
487 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
488 offset, is_frame_entity);
489 } else if (bits == 64) {
490 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
491 offset, is_frame_entity);
494 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
495 offset, is_frame_entity);
502 * @param node the ir Load node
503 * @return the created sparc Load node
505 static ir_node *gen_Load(ir_node *node)
507 dbg_info *dbgi = get_irn_dbg_info(node);
508 ir_mode *mode = get_Load_mode(node);
509 ir_node *block = be_transform_node(get_nodes_block(node));
510 ir_node *ptr = get_Load_ptr(node);
511 ir_node *mem = get_Load_mem(node);
512 ir_node *new_mem = be_transform_node(mem);
513 ir_node *new_load = NULL;
516 if (mode_is_float(mode)) {
517 match_address(ptr, &address, false);
518 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
519 address.entity, address.offset, false);
521 match_address(ptr, &address, true);
522 if (address.ptr2 != NULL) {
523 assert(address.entity == NULL && address.offset == 0);
524 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
525 address.ptr2, new_mem, mode);
527 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
528 mode, address.entity, address.offset,
532 set_irn_pinned(new_load, get_irn_pinned(node));
538 * Transforms a Store.
540 * @param node the ir Store node
541 * @return the created sparc Store node
543 static ir_node *gen_Store(ir_node *node)
545 ir_node *block = be_transform_node(get_nodes_block(node));
546 ir_node *ptr = get_Store_ptr(node);
547 ir_node *mem = get_Store_mem(node);
548 ir_node *new_mem = be_transform_node(mem);
549 ir_node *val = get_Store_value(node);
550 ir_node *new_val = be_transform_node(val);
551 ir_mode *mode = get_irn_mode(val);
552 dbg_info *dbgi = get_irn_dbg_info(node);
553 ir_node *new_store = NULL;
556 if (mode_is_float(mode)) {
557 /* TODO: variants with reg+reg address mode */
558 match_address(ptr, &address, false);
559 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
560 mode, address.entity, address.offset, false);
562 match_address(ptr, &address, true);
563 if (address.ptr2 != NULL) {
564 assert(address.entity == NULL && address.offset == 0);
565 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
566 address.ptr2, new_mem, mode);
568 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
569 new_mem, mode, address.entity,
570 address.offset, false);
573 set_irn_pinned(new_store, get_irn_pinned(node));
579 * Creates an sparc Mul.
580 * returns the lower 32bits of the 64bit multiply result
582 * @return the created sparc Mul node
584 static ir_node *gen_Mul(ir_node *node)
586 ir_mode *mode = get_irn_mode(node);
587 if (mode_is_float(mode)) {
588 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
589 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
592 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
593 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
597 * Creates an sparc Mulh.
598 * Mulh returns the upper 32bits of a mul instruction
600 * @return the created sparc Mulh node
602 static ir_node *gen_Mulh(ir_node *node)
604 ir_mode *mode = get_irn_mode(node);
607 if (mode_is_float(mode))
608 panic("FP not supported yet");
610 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Mulh_reg, new_bd_sparc_Mulh_imm);
611 return new_r_Proj(mul, mode_gp, pn_sparc_Mulh_low);
614 static ir_node *gen_sign_extension_value(ir_node *node)
616 ir_node *block = get_nodes_block(node);
617 ir_node *new_block = be_transform_node(block);
618 ir_node *new_node = be_transform_node(node);
619 /* TODO: we could do some shortcuts for some value types probably.
620 * (For constants or other cases where we know the sign bit in
622 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
626 * Creates an sparc Div.
628 * @return the created sparc Div node
630 static ir_node *gen_Div(ir_node *node)
632 dbg_info *dbgi = get_irn_dbg_info(node);
633 ir_node *block = get_nodes_block(node);
634 ir_node *new_block = be_transform_node(block);
635 ir_mode *mode = get_Div_resmode(node);
636 ir_node *left = get_Div_left(node);
637 ir_node *left_low = be_transform_node(left);
638 ir_node *right = get_Div_right(node);
641 assert(!mode_is_float(mode));
642 if (mode_is_signed(mode)) {
643 ir_node *left_high = gen_sign_extension_value(left);
645 if (is_imm_encodeable(right)) {
646 int32_t immediate = get_tarval_long(get_Const_tarval(right));
647 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
650 ir_node *new_right = be_transform_node(right);
651 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
655 ir_node *left_high = get_g0();
656 if (is_imm_encodeable(right)) {
657 int32_t immediate = get_tarval_long(get_Const_tarval(right));
658 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
661 ir_node *new_right = be_transform_node(right);
662 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
670 static ir_node *gen_Quot(ir_node *node)
672 ir_mode *mode = get_Quot_resmode(node);
673 assert(mode_is_float(mode));
674 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
675 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
679 static ir_node *gen_Abs(ir_node *node)
681 ir_mode *const mode = get_irn_mode(node);
683 if (mode_is_float(mode)) {
684 return gen_helper_unfpop(node, mode, new_bd_sparc_fabs_s,
685 new_bd_sparc_fabs_d, new_bd_sparc_fabs_q);
687 ir_node *const block = be_transform_node(get_nodes_block(node));
688 dbg_info *const dbgi = get_irn_dbg_info(node);
689 ir_node *const op = get_Abs_op(node);
690 ir_node *const new_op = be_transform_node(op);
691 ir_node *const sra = new_bd_sparc_Sra_imm(dbgi, block, new_op, NULL, 31);
692 ir_node *const xor = new_bd_sparc_Xor_reg(dbgi, block, new_op, sra);
693 ir_node *const sub = new_bd_sparc_Sub_reg(dbgi, block, xor, sra);
700 * Transforms a Not node.
702 * @return the created sparc Not node
704 static ir_node *gen_Not(ir_node *node)
706 ir_node *op = get_Not_op(node);
707 ir_node *zero = get_g0();
708 dbg_info *dbgi = get_irn_dbg_info(node);
709 ir_node *block = be_transform_node(get_nodes_block(node));
710 ir_node *new_op = be_transform_node(op);
712 /* Note: Not(Eor()) is normalize in firm locatopts already so
713 * we don't match it for xnor here */
715 /* Not can be represented with xnor 0, n */
716 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
719 static ir_node *gen_helper_bitop(ir_node *node,
720 new_binop_reg_func new_reg,
721 new_binop_imm_func new_imm,
722 new_binop_reg_func new_not_reg,
723 new_binop_imm_func new_not_imm)
725 ir_node *op1 = get_binop_left(node);
726 ir_node *op2 = get_binop_right(node);
728 return gen_helper_binop_args(node, op2, get_Not_op(op1),
730 new_not_reg, new_not_imm);
733 return gen_helper_binop_args(node, op1, get_Not_op(op2),
735 new_not_reg, new_not_imm);
737 return gen_helper_binop_args(node, op1, op2,
738 MATCH_MODE_NEUTRAL | MATCH_COMMUTATIVE,
742 static ir_node *gen_And(ir_node *node)
744 return gen_helper_bitop(node,
745 new_bd_sparc_And_reg,
746 new_bd_sparc_And_imm,
747 new_bd_sparc_AndN_reg,
748 new_bd_sparc_AndN_imm);
751 static ir_node *gen_Or(ir_node *node)
753 return gen_helper_bitop(node,
756 new_bd_sparc_OrN_reg,
757 new_bd_sparc_OrN_imm);
760 static ir_node *gen_Eor(ir_node *node)
762 return gen_helper_bitop(node,
763 new_bd_sparc_Xor_reg,
764 new_bd_sparc_Xor_imm,
765 new_bd_sparc_XNor_reg,
766 new_bd_sparc_XNor_imm);
769 static ir_node *gen_Shl(ir_node *node)
771 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
774 static ir_node *gen_Shr(ir_node *node)
776 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
779 static ir_node *gen_Shrs(ir_node *node)
781 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
785 * Transforms a Minus node.
787 static ir_node *gen_Minus(ir_node *node)
789 ir_mode *mode = get_irn_mode(node);
796 if (mode_is_float(mode)) {
797 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
798 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
800 block = be_transform_node(get_nodes_block(node));
801 dbgi = get_irn_dbg_info(node);
802 op = get_Minus_op(node);
803 new_op = be_transform_node(op);
805 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
809 * Create an entity for a given (floating point) tarval
811 static ir_entity *create_float_const_entity(tarval *tv)
813 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
814 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
815 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
816 ir_initializer_t *initializer;
824 mode = get_tarval_mode(tv);
825 type = get_type_for_mode(mode);
826 glob = get_glob_type();
827 entity = new_entity(glob, id_unique("C%u"), type);
828 set_entity_visibility(entity, ir_visibility_private);
829 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
831 initializer = create_initializer_tarval(tv);
832 set_entity_initializer(entity, initializer);
834 pmap_insert(isa->constants, tv, entity);
838 static ir_node *gen_Const(ir_node *node)
840 ir_node *block = be_transform_node(get_nodes_block(node));
841 ir_mode *mode = get_irn_mode(node);
842 dbg_info *dbgi = get_irn_dbg_info(node);
846 if (mode_is_float(mode)) {
847 tarval *tv = get_Const_tarval(node);
848 ir_entity *entity = create_float_const_entity(tv);
849 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
850 ir_node *mem = new_NoMem();
852 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
853 ir_node *proj = new_Proj(new_op, mode, pn_sparc_Ldf_res);
856 set_irn_pinned(new_op, op_pin_state_floats);
860 tv = get_Const_tarval(node);
861 value = get_tarval_long(tv);
864 } else if (-4096 <= value && value <= 4095) {
865 return new_bd_sparc_Or_imm(dbgi, block, get_g0(), NULL, value);
867 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
869 if ((value & 0x3ff) != 0) {
870 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
877 static ir_mode *get_cmp_mode(ir_node *b_value)
882 if (!is_Proj(b_value))
883 panic("can't determine cond signednes");
884 pred = get_Proj_pred(b_value);
886 panic("can't determine cond signednes (no cmp)");
887 op = get_Cmp_left(pred);
888 return get_irn_mode(op);
891 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
894 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
895 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
900 static ir_node *gen_SwitchJmp(ir_node *node)
902 dbg_info *dbgi = get_irn_dbg_info(node);
903 ir_node *block = be_transform_node(get_nodes_block(node));
904 ir_node *selector = get_Cond_selector(node);
905 ir_node *new_selector = be_transform_node(selector);
906 long default_pn = get_Cond_default_proj(node);
908 ir_node *table_address;
913 /* switch with smaller mode not implemented yet */
914 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
916 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
917 set_entity_visibility(entity, ir_visibility_private);
918 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
920 /* TODO: this code does not construct code to check for access
921 * out-of bounds of the jumptable yet. I think we should put this stuff
922 * into the switch_lowering phase to get some additional optimisations
925 /* construct base address */
926 table_address = make_address(dbgi, block, entity, 0);
928 index = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
929 /* load from jumptable */
930 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, index, new_NoMem(),
932 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
934 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
937 static ir_node *gen_Cond(ir_node *node)
939 ir_node *selector = get_Cond_selector(node);
940 ir_mode *mode = get_irn_mode(selector);
949 if (mode != mode_b) {
950 return gen_SwitchJmp(node);
953 // regular if/else jumps
954 assert(is_Proj(selector));
955 assert(is_Cmp(get_Proj_pred(selector)));
957 cmp_mode = get_cmp_mode(selector);
959 block = be_transform_node(get_nodes_block(node));
960 dbgi = get_irn_dbg_info(node);
961 flag_node = be_transform_node(get_Proj_pred(selector));
962 pnc = get_Proj_proj(selector);
963 is_unsigned = !mode_is_signed(cmp_mode);
964 if (mode_is_float(cmp_mode)) {
965 assert(!is_unsigned);
966 return new_bd_sparc_fbfcc(dbgi, block, flag_node, pnc);
968 return new_bd_sparc_Bicc(dbgi, block, flag_node, pnc, is_unsigned);
975 static ir_node *gen_Cmp(ir_node *node)
977 ir_node *op1 = get_Cmp_left(node);
978 ir_node *op2 = get_Cmp_right(node);
979 ir_mode *cmp_mode = get_irn_mode(op1);
980 assert(get_irn_mode(op2) == cmp_mode);
982 if (mode_is_float(cmp_mode)) {
983 ir_node *block = be_transform_node(get_nodes_block(node));
984 dbg_info *dbgi = get_irn_dbg_info(node);
985 ir_node *new_op1 = be_transform_node(op1);
986 ir_node *new_op2 = be_transform_node(op2);
987 unsigned bits = get_mode_size_bits(cmp_mode);
989 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
990 } else if (bits == 64) {
991 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
994 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
998 /* when we compare a bitop like and,or,... with 0 then we can directly use
999 * the bitopcc variant.
1000 * Currently we only do this when we're the only user of the node...
1002 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1004 return gen_helper_bitop(op1,
1005 new_bd_sparc_AndCCZero_reg,
1006 new_bd_sparc_AndCCZero_imm,
1007 new_bd_sparc_AndNCCZero_reg,
1008 new_bd_sparc_AndNCCZero_imm);
1009 } else if (is_Or(op1)) {
1010 return gen_helper_bitop(op1,
1011 new_bd_sparc_OrCCZero_reg,
1012 new_bd_sparc_OrCCZero_imm,
1013 new_bd_sparc_OrNCCZero_reg,
1014 new_bd_sparc_OrNCCZero_imm);
1015 } else if (is_Eor(op1)) {
1016 return gen_helper_bitop(op1,
1017 new_bd_sparc_XorCCZero_reg,
1018 new_bd_sparc_XorCCZero_imm,
1019 new_bd_sparc_XNorCCZero_reg,
1020 new_bd_sparc_XNorCCZero_imm);
1024 /* integer compare */
1025 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1026 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1030 * Transforms a SymConst node.
1032 static ir_node *gen_SymConst(ir_node *node)
1034 ir_entity *entity = get_SymConst_entity(node);
1035 dbg_info *dbgi = get_irn_dbg_info(node);
1036 ir_node *block = get_nodes_block(node);
1037 ir_node *new_block = be_transform_node(block);
1038 return make_address(dbgi, new_block, entity, 0);
1041 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1042 ir_mode *src_mode, ir_mode *dst_mode)
1044 unsigned src_bits = get_mode_size_bits(src_mode);
1045 unsigned dst_bits = get_mode_size_bits(dst_mode);
1046 if (src_bits == 32) {
1047 if (dst_bits == 64) {
1048 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1050 assert(dst_bits == 128);
1051 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1053 } else if (src_bits == 64) {
1054 if (dst_bits == 32) {
1055 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1057 assert(dst_bits == 128);
1058 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1061 assert(src_bits == 128);
1062 if (dst_bits == 32) {
1063 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1065 assert(dst_bits == 64);
1066 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1071 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1075 unsigned bits = get_mode_size_bits(src_mode);
1077 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1078 } else if (bits == 64) {
1079 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1081 assert(bits == 128);
1082 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1086 ir_graph *irg = get_irn_irg(block);
1087 ir_node *sp = get_irg_frame(irg);
1088 ir_node *nomem = new_r_NoMem(irg);
1089 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1091 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1093 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1094 set_irn_pinned(stf, op_pin_state_floats);
1095 set_irn_pinned(ld, op_pin_state_floats);
1100 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1103 ir_graph *irg = get_irn_irg(block);
1104 ir_node *sp = get_irg_frame(irg);
1105 ir_node *nomem = new_r_NoMem(irg);
1106 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1107 mode_gp, NULL, 0, true);
1108 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1110 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1111 unsigned bits = get_mode_size_bits(dst_mode);
1112 set_irn_pinned(st, op_pin_state_floats);
1113 set_irn_pinned(ldf, op_pin_state_floats);
1116 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1117 } else if (bits == 64) {
1118 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1120 assert(bits == 128);
1121 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1125 static ir_node *gen_Conv(ir_node *node)
1127 ir_node *block = be_transform_node(get_nodes_block(node));
1128 ir_node *op = get_Conv_op(node);
1129 ir_node *new_op = be_transform_node(op);
1130 ir_mode *src_mode = get_irn_mode(op);
1131 ir_mode *dst_mode = get_irn_mode(node);
1132 dbg_info *dbg = get_irn_dbg_info(node);
1134 int src_bits = get_mode_size_bits(src_mode);
1135 int dst_bits = get_mode_size_bits(dst_mode);
1137 if (src_mode == dst_mode)
1140 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1141 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1143 if (mode_is_float(src_mode)) {
1144 if (mode_is_float(dst_mode)) {
1145 /* float -> float conv */
1146 return create_fftof(dbg, block, new_op, src_mode, dst_mode);
1148 /* float -> int conv */
1149 if (!mode_is_signed(dst_mode))
1150 panic("float to unsigned not implemented yet");
1151 return create_ftoi(dbg, block, new_op, src_mode);
1154 /* int -> float conv */
1155 if (src_bits < 32) {
1156 new_op = gen_extension(dbg, block, new_op, src_mode);
1157 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1158 panic("unsigned to float not lowered!");
1160 return create_itof(dbg, block, new_op, dst_mode);
1162 } else { /* complete in gp registers */
1166 if (src_bits == dst_bits) {
1167 /* kill unnecessary conv */
1171 if (src_bits < dst_bits) {
1172 min_bits = src_bits;
1173 min_mode = src_mode;
1175 min_bits = dst_bits;
1176 min_mode = dst_mode;
1179 if (upper_bits_clean(new_op, min_mode)) {
1183 if (mode_is_signed(min_mode)) {
1184 return gen_sign_extension(dbg, block, new_op, min_bits);
1186 return gen_zero_extension(dbg, block, new_op, min_bits);
1191 static ir_node *gen_Unknown(ir_node *node)
1193 /* just produce a 0 */
1194 ir_mode *mode = get_irn_mode(node);
1195 if (mode_is_float(mode)) {
1196 panic("FP not implemented");
1197 be_dep_on_frame(node);
1199 } else if (mode_needs_gp_reg(mode)) {
1203 panic("Unexpected Unknown mode");
1207 * Produces the type which sits between the stack args and the locals on the
1210 static ir_type *sparc_get_between_type(void)
1212 static ir_type *between_type = NULL;
1214 if (between_type == NULL) {
1215 between_type = new_type_class(new_id_from_str("sparc_between_type"));
1216 set_type_size_bytes(between_type, SPARC_MIN_STACKSIZE);
1219 return between_type;
1222 static void create_stacklayout(ir_graph *irg)
1224 ir_entity *entity = get_irg_entity(irg);
1225 ir_type *function_type = get_entity_type(entity);
1226 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1231 /* calling conventions must be decided by now */
1232 assert(cconv != NULL);
1234 /* construct argument type */
1235 arg_type = new_type_struct(id_mangle_u(get_entity_ident(entity), new_id_from_chars("arg_type", 8)));
1236 n_params = get_method_n_params(function_type);
1237 for (p = 0; p < n_params; ++p) {
1238 reg_or_stackslot_t *param = &cconv->parameters[p];
1242 if (param->type == NULL)
1245 snprintf(buf, sizeof(buf), "param_%d", p);
1246 id = new_id_from_str(buf);
1247 param->entity = new_entity(arg_type, id, param->type);
1248 set_entity_offset(param->entity, param->offset);
1251 memset(layout, 0, sizeof(*layout));
1253 layout->frame_type = get_irg_frame_type(irg);
1254 layout->between_type = sparc_get_between_type();
1255 layout->arg_type = arg_type;
1256 layout->initial_offset = 0;
1257 layout->initial_bias = 0;
1258 layout->stack_dir = -1;
1259 layout->sp_relative = false;
1261 assert(N_FRAME_TYPES == 3);
1262 layout->order[0] = layout->frame_type;
1263 layout->order[1] = layout->between_type;
1264 layout->order[2] = layout->arg_type;
1268 * transform the start node to the prolog code + initial barrier
1270 static ir_node *gen_Start(ir_node *node)
1272 ir_graph *irg = get_irn_irg(node);
1273 ir_entity *entity = get_irg_entity(irg);
1274 ir_type *function_type = get_entity_type(entity);
1275 ir_node *block = get_nodes_block(node);
1276 ir_node *new_block = be_transform_node(block);
1277 dbg_info *dbgi = get_irn_dbg_info(node);
1286 /* stackpointer is important at function prolog */
1287 be_prolog_add_reg(abihelper, sp_reg,
1288 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1289 be_prolog_add_reg(abihelper, &sparc_gp_regs[REG_G0],
1290 arch_register_req_type_ignore);
1291 /* function parameters in registers */
1292 for (i = 0; i < get_method_n_params(function_type); ++i) {
1293 const reg_or_stackslot_t *param = &cconv->parameters[i];
1294 if (param->reg0 != NULL)
1295 be_prolog_add_reg(abihelper, param->reg0, 0);
1296 if (param->reg1 != NULL)
1297 be_prolog_add_reg(abihelper, param->reg1, 0);
1300 start = be_prolog_create_start(abihelper, dbgi, new_block);
1302 mem = be_prolog_get_memory(abihelper);
1303 sp = be_prolog_get_reg_value(abihelper, sp_reg);
1304 save = new_bd_sparc_Save(NULL, block, sp, mem, SPARC_MIN_STACKSIZE);
1305 fp = new_r_Proj(save, mode_gp, pn_sparc_Save_frame);
1306 sp = new_r_Proj(save, mode_gp, pn_sparc_Save_stack);
1307 mem = new_r_Proj(save, mode_M, pn_sparc_Save_mem);
1308 arch_set_irn_register(fp, fp_reg);
1309 arch_set_irn_register(sp, sp_reg);
1311 be_prolog_add_reg(abihelper, fp_reg, arch_register_req_type_ignore);
1312 be_prolog_set_reg_value(abihelper, fp_reg, fp);
1314 sp = be_new_IncSP(sp_reg, new_block, sp, BE_STACK_FRAME_SIZE_EXPAND, 0);
1315 be_prolog_set_reg_value(abihelper, sp_reg, sp);
1316 be_prolog_set_memory(abihelper, mem);
1318 barrier = be_prolog_create_barrier(abihelper, new_block);
1323 static ir_node *get_stack_pointer_for(ir_node *node)
1325 /* get predecessor in stack_order list */
1326 ir_node *stack_pred = be_get_stack_pred(abihelper, node);
1327 ir_node *stack_pred_transformed;
1330 if (stack_pred == NULL) {
1331 /* first stack user in the current block. We can simply use the
1332 * initial sp_proj for it */
1333 ir_node *sp_proj = be_prolog_get_reg_value(abihelper, sp_reg);
1337 stack_pred_transformed = be_transform_node(stack_pred);
1338 stack = pmap_get(node_to_stack, stack_pred);
1339 if (stack == NULL) {
1340 return get_stack_pointer_for(stack_pred);
1347 * transform a Return node into epilogue code + return statement
1349 static ir_node *gen_Return(ir_node *node)
1351 ir_node *block = get_nodes_block(node);
1352 ir_node *new_block = be_transform_node(block);
1353 dbg_info *dbgi = get_irn_dbg_info(node);
1354 ir_node *mem = get_Return_mem(node);
1355 ir_node *new_mem = be_transform_node(mem);
1356 ir_node *sp_proj = get_stack_pointer_for(node);
1357 int n_res = get_Return_n_ress(node);
1362 be_epilog_begin(abihelper);
1363 be_epilog_set_memory(abihelper, new_mem);
1364 /* connect stack pointer with initial stack pointer. fix_stack phase
1365 will later serialize all stack pointer adjusting nodes */
1366 be_epilog_add_reg(abihelper, sp_reg,
1367 arch_register_req_type_produces_sp | arch_register_req_type_ignore,
1371 for (i = 0; i < n_res; ++i) {
1372 ir_node *res_value = get_Return_res(node, i);
1373 ir_node *new_res_value = be_transform_node(res_value);
1374 const reg_or_stackslot_t *slot = &cconv->results[i];
1375 const arch_register_t *reg = slot->reg0;
1376 assert(slot->reg1 == NULL);
1377 be_epilog_add_reg(abihelper, reg, 0, new_res_value);
1380 /* create the barrier before the epilog code */
1381 be_epilog_create_barrier(abihelper, new_block);
1383 /* epilog code: an incsp */
1384 sp_proj = be_epilog_get_reg_value(abihelper, sp_reg);
1385 incsp = be_new_IncSP(sp_reg, new_block, sp_proj,
1386 BE_STACK_FRAME_SIZE_SHRINK, 0);
1387 be_epilog_set_reg_value(abihelper, sp_reg, incsp);
1389 bereturn = be_epilog_create_return(abihelper, dbgi, new_block);
1394 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1395 ir_node *value0, ir_node *value1)
1397 ir_graph *irg = current_ir_graph;
1398 ir_node *sp = get_irg_frame(irg);
1399 ir_node *nomem = new_NoMem();
1400 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1401 mode_gp, NULL, 0, true);
1405 set_irn_pinned(st, op_pin_state_floats);
1407 if (value1 != NULL) {
1408 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1409 mode_gp, NULL, 4, true);
1410 ir_node *in[2] = { st, st1 };
1411 ir_node *sync = new_r_Sync(block, 2, in);
1412 set_irn_pinned(st1, op_pin_state_floats);
1420 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1421 set_irn_pinned(ldf, op_pin_state_floats);
1423 return new_Proj(ldf, mode, pn_sparc_Ldf_res);
1426 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1427 ir_node *node, ir_mode *float_mode,
1430 ir_graph *irg = current_ir_graph;
1431 ir_node *stack = get_irg_frame(irg);
1432 ir_node *nomem = new_NoMem();
1433 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1435 int bits = get_mode_size_bits(float_mode);
1437 set_irn_pinned(stf, op_pin_state_floats);
1439 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1440 set_irn_pinned(ld, op_pin_state_floats);
1441 result[0] = new_Proj(ld, mode_gp, pn_sparc_Ld_res);
1444 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1446 set_irn_pinned(ld, op_pin_state_floats);
1447 result[1] = new_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1449 arch_irn_add_flags(ld, sparc_arch_irn_flag_needs_64bit_spillslot);
1450 arch_irn_add_flags(ld2, sparc_arch_irn_flag_needs_64bit_spillslot);
1457 static ir_node *gen_Call(ir_node *node)
1459 ir_graph *irg = get_irn_irg(node);
1460 ir_node *callee = get_Call_ptr(node);
1461 ir_node *block = get_nodes_block(node);
1462 ir_node *new_block = be_transform_node(block);
1463 ir_node *mem = get_Call_mem(node);
1464 ir_node *new_mem = be_transform_node(mem);
1465 dbg_info *dbgi = get_irn_dbg_info(node);
1466 ir_type *type = get_Call_type(node);
1467 int n_params = get_Call_n_params(node);
1468 int n_param_regs = sizeof(param_regs)/sizeof(param_regs[0]);
1469 /* max inputs: memory, callee, register arguments */
1470 int max_inputs = 2 + n_param_regs;
1471 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1472 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1473 struct obstack *obst = be_get_be_obst(irg);
1474 const arch_register_req_t **in_req
1475 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1476 calling_convention_t *cconv
1477 = sparc_decide_calling_convention(type, true);
1481 = sizeof(caller_saves)/sizeof(caller_saves[0]);
1482 ir_entity *entity = NULL;
1483 ir_node *new_frame = get_stack_pointer_for(node);
1492 assert(n_params == get_method_n_params(type));
1494 /* construct arguments */
1497 in_req[in_arity] = arch_no_register_req;
1501 /* stack pointer input */
1502 /* construct an IncSP -> we have to always be sure that the stack is
1503 * aligned even if we don't push arguments on it */
1504 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1505 cconv->param_stack_size, 1);
1506 in_req[in_arity] = sp_reg->single_req;
1507 in[in_arity] = incsp;
1511 for (p = 0; p < n_params; ++p) {
1512 ir_node *value = get_Call_param(node, p);
1513 ir_node *new_value = be_transform_node(value);
1514 const reg_or_stackslot_t *param = &cconv->parameters[p];
1515 ir_type *param_type = get_method_param_type(type, p);
1516 ir_mode *mode = get_type_mode(param_type);
1517 ir_node *new_values[2];
1520 if (mode_is_float(mode) && param->reg0 != NULL) {
1521 unsigned size_bits = get_mode_size_bits(mode);
1522 assert(size_bits <= 64);
1523 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1525 new_values[0] = new_value;
1526 new_values[1] = NULL;
1529 /* put value into registers */
1530 if (param->reg0 != NULL) {
1531 in[in_arity] = new_values[0];
1532 in_req[in_arity] = param->reg0->single_req;
1534 if (new_values[1] == NULL)
1537 if (param->reg1 != NULL) {
1538 assert(new_values[1] != NULL);
1539 in[in_arity] = new_values[1];
1540 in_req[in_arity] = param->reg1->single_req;
1545 /* we need a store if we're here */
1546 if (new_values[1] != NULL) {
1547 new_value = new_values[1];
1551 /* create a parameter frame if necessary */
1552 if (mode_is_float(mode)) {
1553 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1554 mode, NULL, param->offset, true);
1556 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1557 new_mem, mode, NULL, param->offset, true);
1559 set_irn_pinned(str, op_pin_state_floats);
1560 sync_ins[sync_arity++] = str;
1562 assert(in_arity <= max_inputs);
1564 /* construct memory input */
1565 if (sync_arity == 0) {
1566 in[mem_pos] = new_mem;
1567 } else if (sync_arity == 1) {
1568 in[mem_pos] = sync_ins[0];
1570 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1573 if (is_SymConst(callee)) {
1574 entity = get_SymConst_entity(callee);
1576 in[in_arity] = be_transform_node(callee);
1577 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1585 out_arity = 1 + n_caller_saves;
1587 /* create call node */
1588 if (entity != NULL) {
1589 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1592 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity);
1594 arch_set_in_register_reqs(res, in_req);
1596 /* create output register reqs */
1598 arch_set_out_register_req(res, o++, arch_no_register_req);
1599 for (i = 0; i < n_caller_saves; ++i) {
1600 const arch_register_t *reg = caller_saves[i];
1601 arch_set_out_register_req(res, o++, reg->single_req);
1603 assert(o == out_arity);
1605 /* copy pinned attribute */
1606 set_irn_pinned(res, get_irn_pinned(node));
1608 /* IncSP to destroy the call stackframe */
1609 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1610 /* if we are the last IncSP producer in a block then we have to keep
1612 * Note: This here keeps all producers which is more than necessary */
1613 add_irn_dep(incsp, res);
1616 pmap_insert(node_to_stack, node, incsp);
1618 sparc_free_calling_convention(cconv);
1622 static ir_node *gen_Sel(ir_node *node)
1624 dbg_info *dbgi = get_irn_dbg_info(node);
1625 ir_node *block = get_nodes_block(node);
1626 ir_node *new_block = be_transform_node(block);
1627 ir_node *ptr = get_Sel_ptr(node);
1628 ir_node *new_ptr = be_transform_node(ptr);
1629 ir_entity *entity = get_Sel_entity(node);
1631 /* must be the frame pointer all other sels must have been lowered
1633 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1634 /* we should not have value types from parameters anymore - they should be
1636 assert(get_entity_owner(entity) !=
1637 get_method_value_param_type(get_entity_type(get_irg_entity(get_irn_irg(node)))));
1639 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1642 static const arch_register_req_t float1_req = {
1643 arch_register_req_type_normal,
1644 &sparc_reg_classes[CLASS_sparc_fp],
1650 static const arch_register_req_t float2_req = {
1651 arch_register_req_type_normal | arch_register_req_type_aligned,
1652 &sparc_reg_classes[CLASS_sparc_fp],
1658 static const arch_register_req_t float4_req = {
1659 arch_register_req_type_normal | arch_register_req_type_aligned,
1660 &sparc_reg_classes[CLASS_sparc_fp],
1668 static const arch_register_req_t *get_float_req(ir_mode *mode)
1670 unsigned bits = get_mode_size_bits(mode);
1672 assert(mode_is_float(mode));
1675 } else if (bits == 64) {
1678 assert(bits == 128);
1684 * Transform some Phi nodes
1686 static ir_node *gen_Phi(ir_node *node)
1688 const arch_register_req_t *req;
1689 ir_node *block = be_transform_node(get_nodes_block(node));
1690 ir_graph *irg = current_ir_graph;
1691 dbg_info *dbgi = get_irn_dbg_info(node);
1692 ir_mode *mode = get_irn_mode(node);
1695 if (mode_needs_gp_reg(mode)) {
1696 /* we shouldn't have any 64bit stuff around anymore */
1697 assert(get_mode_size_bits(mode) <= 32);
1698 /* all integer operations are on 32bit registers now */
1700 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
1701 } else if (mode_is_float(mode)) {
1703 req = get_float_req(mode);
1705 req = arch_no_register_req;
1708 /* phi nodes allow loops, so we use the old arguments for now
1709 * and fix this later */
1710 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1711 copy_node_attr(irg, node, phi);
1712 be_duplicate_deps(node, phi);
1713 arch_set_out_register_req(phi, 0, req);
1714 be_enqueue_preds(node);
1719 * Transform a Proj from a Load.
1721 static ir_node *gen_Proj_Load(ir_node *node)
1723 ir_node *load = get_Proj_pred(node);
1724 ir_node *new_load = be_transform_node(load);
1725 dbg_info *dbgi = get_irn_dbg_info(node);
1726 long pn = get_Proj_proj(node);
1728 /* renumber the proj */
1729 switch (get_sparc_irn_opcode(new_load)) {
1731 /* handle all gp loads equal: they have the same proj numbers. */
1732 if (pn == pn_Load_res) {
1733 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
1734 } else if (pn == pn_Load_M) {
1735 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1739 if (pn == pn_Load_res) {
1740 return new_rd_Proj(dbgi, new_load, mode_fp, pn_sparc_Ldf_res);
1741 } else if (pn == pn_Load_M) {
1742 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1748 panic("Unsupported Proj from Load");
1751 static ir_node *gen_Proj_Store(ir_node *node)
1753 ir_node *store = get_Proj_pred(node);
1754 ir_node *new_store = be_transform_node(store);
1755 long pn = get_Proj_proj(node);
1757 /* renumber the proj */
1758 switch (get_sparc_irn_opcode(new_store)) {
1760 if (pn == pn_Store_M) {
1765 if (pn == pn_Store_M) {
1772 panic("Unsupported Proj from Store");
1776 * Transform the Projs from a Cmp.
1778 static ir_node *gen_Proj_Cmp(ir_node *node)
1781 panic("not implemented");
1785 * transform Projs from a Div
1787 static ir_node *gen_Proj_Div(ir_node *node)
1789 ir_node *pred = get_Proj_pred(node);
1790 ir_node *new_pred = be_transform_node(pred);
1791 long pn = get_Proj_proj(node);
1793 assert(is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred));
1794 assert(pn_sparc_SDiv_res == pn_sparc_UDiv_res);
1795 assert(pn_sparc_SDiv_M == pn_sparc_UDiv_M);
1798 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_res);
1800 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
1804 panic("Unsupported Proj from Div");
1807 static ir_node *gen_Proj_Quot(ir_node *node)
1809 ir_node *pred = get_Proj_pred(node);
1810 ir_node *new_pred = be_transform_node(pred);
1811 long pn = get_Proj_proj(node);
1813 assert(is_sparc_fdiv(new_pred));
1816 return new_r_Proj(new_pred, mode_gp, pn_sparc_fdiv_res);
1818 return new_r_Proj(new_pred, mode_gp, pn_sparc_fdiv_M);
1822 panic("Unsupported Proj from Quot");
1825 static ir_node *gen_Proj_Start(ir_node *node)
1827 ir_node *block = get_nodes_block(node);
1828 ir_node *new_block = be_transform_node(block);
1829 ir_node *barrier = be_transform_node(get_Proj_pred(node));
1830 long pn = get_Proj_proj(node);
1832 switch ((pn_Start) pn) {
1833 case pn_Start_X_initial_exec:
1834 /* exchange ProjX with a jump */
1835 return new_bd_sparc_Ba(NULL, new_block);
1837 return new_r_Proj(barrier, mode_M, 0);
1838 case pn_Start_T_args:
1840 case pn_Start_P_frame_base:
1841 return be_prolog_get_reg_value(abihelper, fp_reg);
1842 case pn_Start_P_tls:
1847 panic("Unexpected start proj: %ld\n", pn);
1850 static ir_node *gen_Proj_Proj_Start(ir_node *node)
1852 long pn = get_Proj_proj(node);
1853 ir_node *block = get_nodes_block(node);
1854 ir_node *new_block = be_transform_node(block);
1855 ir_entity *entity = get_irg_entity(current_ir_graph);
1856 ir_type *method_type = get_entity_type(entity);
1857 ir_type *param_type = get_method_param_type(method_type, pn);
1858 const reg_or_stackslot_t *param;
1860 /* Proj->Proj->Start must be a method argument */
1861 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
1863 param = &cconv->parameters[pn];
1865 if (param->reg0 != NULL) {
1866 /* argument transmitted in register */
1867 ir_mode *mode = get_type_mode(param_type);
1868 const arch_register_t *reg = param->reg0;
1869 ir_node *value = be_prolog_get_reg_value(abihelper, reg);
1871 if (mode_is_float(mode)) {
1872 ir_node *value1 = NULL;
1874 if (param->reg1 != NULL) {
1875 value1 = be_prolog_get_reg_value(abihelper, param->reg1);
1876 } else if (param->entity != NULL) {
1877 ir_node *fp = be_prolog_get_reg_value(abihelper, fp_reg);
1878 ir_node *mem = be_prolog_get_memory(abihelper);
1879 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
1880 mode_gp, param->entity,
1882 value1 = new_Proj(ld, mode_gp, pn_sparc_Ld_res);
1885 /* convert integer value to float */
1886 value = bitcast_int_to_float(NULL, new_block, value, value1);
1890 /* argument transmitted on stack */
1891 ir_node *fp = be_prolog_get_reg_value(abihelper, fp_reg);
1892 ir_node *mem = be_prolog_get_memory(abihelper);
1893 ir_mode *mode = get_type_mode(param->type);
1897 if (mode_is_float(mode)) {
1898 load = create_ldf(NULL, new_block, fp, mem, mode,
1899 param->entity, 0, true);
1900 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
1902 load = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem, mode,
1903 param->entity, 0, true);
1904 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1906 set_irn_pinned(load, op_pin_state_floats);
1912 static ir_node *gen_Proj_Call(ir_node *node)
1914 long pn = get_Proj_proj(node);
1915 ir_node *call = get_Proj_pred(node);
1916 ir_node *new_call = be_transform_node(call);
1918 switch ((pn_Call) pn) {
1920 return new_r_Proj(new_call, mode_M, 0);
1921 case pn_Call_X_regular:
1922 case pn_Call_X_except:
1923 case pn_Call_T_result:
1924 case pn_Call_P_value_res_base:
1928 panic("Unexpected Call proj %ld\n", pn);
1932 * Finds number of output value of a mode_T node which is constrained to
1933 * a single specific register.
1935 static int find_out_for_reg(ir_node *node, const arch_register_t *reg)
1937 int n_outs = arch_irn_get_n_outs(node);
1940 for (o = 0; o < n_outs; ++o) {
1941 const arch_register_req_t *req = arch_get_out_register_req(node, o);
1942 if (req == reg->single_req)
1948 static ir_node *gen_Proj_Proj_Call(ir_node *node)
1950 long pn = get_Proj_proj(node);
1951 ir_node *call = get_Proj_pred(get_Proj_pred(node));
1952 ir_node *new_call = be_transform_node(call);
1953 ir_type *function_type = get_Call_type(call);
1954 calling_convention_t *cconv
1955 = sparc_decide_calling_convention(function_type, true);
1956 const reg_or_stackslot_t *res = &cconv->results[pn];
1957 const arch_register_t *reg = res->reg0;
1961 assert(res->reg0 != NULL && res->reg1 == NULL);
1962 regn = find_out_for_reg(new_call, reg);
1964 panic("Internal error in calling convention for return %+F", node);
1966 mode = res->reg0->reg_class->mode;
1968 sparc_free_calling_convention(cconv);
1970 return new_r_Proj(new_call, mode, regn);
1974 * Transform a Proj node.
1976 static ir_node *gen_Proj(ir_node *node)
1978 ir_node *pred = get_Proj_pred(node);
1980 switch (get_irn_opcode(pred)) {
1982 return gen_Proj_Store(node);
1984 return gen_Proj_Load(node);
1986 return gen_Proj_Call(node);
1988 return gen_Proj_Cmp(node);
1990 return be_duplicate_node(node);
1992 return gen_Proj_Div(node);
1994 return gen_Proj_Quot(node);
1996 return gen_Proj_Start(node);
1998 ir_node *pred_pred = get_Proj_pred(pred);
1999 if (is_Call(pred_pred)) {
2000 return gen_Proj_Proj_Call(node);
2001 } else if (is_Start(pred_pred)) {
2002 return gen_Proj_Proj_Start(node);
2007 panic("code selection didn't expect Proj after %+F\n", pred);
2014 static ir_node *gen_Jmp(ir_node *node)
2016 ir_node *block = get_nodes_block(node);
2017 ir_node *new_block = be_transform_node(block);
2018 dbg_info *dbgi = get_irn_dbg_info(node);
2020 return new_bd_sparc_Ba(dbgi, new_block);
2024 * configure transformation callbacks
2026 static void sparc_register_transformers(void)
2028 be_start_transform_setup();
2030 be_set_transform_function(op_Add, gen_Add);
2031 be_set_transform_function(op_And, gen_And);
2032 be_set_transform_function(op_Call, gen_Call);
2033 be_set_transform_function(op_Cmp, gen_Cmp);
2034 be_set_transform_function(op_Cond, gen_Cond);
2035 be_set_transform_function(op_Const, gen_Const);
2036 be_set_transform_function(op_Conv, gen_Conv);
2037 be_set_transform_function(op_Div, gen_Div);
2038 be_set_transform_function(op_Eor, gen_Eor);
2039 be_set_transform_function(op_Jmp, gen_Jmp);
2040 be_set_transform_function(op_Load, gen_Load);
2041 be_set_transform_function(op_Minus, gen_Minus);
2042 be_set_transform_function(op_Mul, gen_Mul);
2043 be_set_transform_function(op_Mulh, gen_Mulh);
2044 be_set_transform_function(op_Not, gen_Not);
2045 be_set_transform_function(op_Or, gen_Or);
2046 be_set_transform_function(op_Phi, gen_Phi);
2047 be_set_transform_function(op_Proj, gen_Proj);
2048 be_set_transform_function(op_Quot, gen_Quot);
2049 be_set_transform_function(op_Return, gen_Return);
2050 be_set_transform_function(op_Sel, gen_Sel);
2051 be_set_transform_function(op_Shl, gen_Shl);
2052 be_set_transform_function(op_Shr, gen_Shr);
2053 be_set_transform_function(op_Shrs, gen_Shrs);
2054 be_set_transform_function(op_Start, gen_Start);
2055 be_set_transform_function(op_Store, gen_Store);
2056 be_set_transform_function(op_Sub, gen_Sub);
2057 be_set_transform_function(op_SymConst, gen_SymConst);
2058 be_set_transform_function(op_Unknown, gen_Unknown);
2060 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2063 /* hack to avoid unused fp proj at start barrier */
2064 static void assure_fp_keep(void)
2066 unsigned n_users = 0;
2067 const ir_edge_t *edge;
2068 ir_node *fp_proj = be_prolog_get_reg_value(abihelper, fp_reg);
2070 foreach_out_edge(fp_proj, edge) {
2071 ir_node *succ = get_edge_src_irn(edge);
2072 if (is_End(succ) || is_Anchor(succ))
2078 ir_node *block = get_nodes_block(fp_proj);
2079 ir_node *in[1] = { fp_proj };
2080 be_new_Keep(block, 1, in);
2085 * Transform a Firm graph into a SPARC graph.
2087 void sparc_transform_graph(ir_graph *irg)
2089 ir_entity *entity = get_irg_entity(irg);
2090 ir_type *frame_type;
2092 sparc_register_transformers();
2094 node_to_stack = pmap_create();
2101 abihelper = be_abihelper_prepare(irg);
2102 be_collect_stacknodes(abihelper);
2103 cconv = sparc_decide_calling_convention(get_entity_type(entity), false);
2104 create_stacklayout(irg);
2106 be_transform_graph(irg, NULL);
2109 be_abihelper_finish(abihelper);
2110 sparc_free_calling_convention(cconv);
2112 frame_type = get_irg_frame_type(irg);
2113 if (get_type_state(frame_type) == layout_undefined)
2114 default_layout_compound_type(frame_type);
2116 pmap_destroy(node_to_stack);
2117 node_to_stack = NULL;
2119 be_add_missing_keeps(irg);
2121 /* do code placement, to optimize the position of constants */
2125 void sparc_init_transform(void)
2127 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");