2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
31 #include "irgraph_t.h"
37 #include "iroptimize.h"
47 #include "betranshlp.h"
48 #include "beabihelper.h"
49 #include "bearch_sparc_t.h"
51 #include "sparc_nodes_attr.h"
52 #include "sparc_transform.h"
53 #include "sparc_new_nodes.h"
54 #include "gen_sparc_new_nodes.h"
56 #include "gen_sparc_regalloc_if.h"
57 #include "sparc_cconv.h"
61 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
63 typedef struct reg_info_t {
68 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
69 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
70 static calling_convention_t *current_cconv = NULL;
71 static be_stackorder_t *stackorder;
72 static ir_mode *mode_gp;
73 static ir_mode *mode_flags;
74 static ir_mode *mode_fp;
75 static ir_mode *mode_fp2;
76 //static ir_mode *mode_fp4;
77 static pmap *node_to_stack;
78 static reg_info_t start_mem;
79 static reg_info_t start_g0;
80 static reg_info_t start_g7;
81 static reg_info_t start_sp;
82 static reg_info_t start_fp;
83 static ir_node *frame_base;
84 static size_t start_params_offset;
85 static size_t start_callee_saves_offset;
87 static const arch_register_t *const omit_fp_callee_saves[] = {
88 &sparc_registers[REG_L0],
89 &sparc_registers[REG_L1],
90 &sparc_registers[REG_L2],
91 &sparc_registers[REG_L3],
92 &sparc_registers[REG_L4],
93 &sparc_registers[REG_L5],
94 &sparc_registers[REG_L6],
95 &sparc_registers[REG_L7],
96 &sparc_registers[REG_I0],
97 &sparc_registers[REG_I1],
98 &sparc_registers[REG_I2],
99 &sparc_registers[REG_I3],
100 &sparc_registers[REG_I4],
101 &sparc_registers[REG_I5],
104 static inline bool mode_needs_gp_reg(ir_mode *mode)
106 if (mode_is_int(mode) || mode_is_reference(mode)) {
107 /* we should only see 32bit code */
108 assert(get_mode_size_bits(mode) <= 32);
115 * Create an And that will zero out upper bits.
117 * @param dbgi debug info
118 * @param block the basic block
119 * @param op the original node
120 * @param src_bits number of lower bits that will remain
122 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
126 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
127 } else if (src_bits == 16) {
128 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
129 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
132 panic("zero extension only supported for 8 and 16 bits");
137 * Generate code for a sign extension.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * @param src_bits number of lower bits that will remain
144 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
147 int shift_width = 32 - src_bits;
148 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
149 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
154 * Extend a value to 32 bit signed/unsigned depending on its mode.
156 * @param dbgi debug info
157 * @param block the basic block
158 * @param op the original node
159 * @param orig_mode the original mode of op
161 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
164 int bits = get_mode_size_bits(orig_mode);
167 if (mode_is_signed(orig_mode)) {
168 return gen_sign_extension(dbgi, block, op, bits);
170 return gen_zero_extension(dbgi, block, op, bits);
176 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
177 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
178 influence the significant lower bit at
179 all (for cases where mode < 32bit) */
181 ENUM_BITSET(match_flags_t)
183 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
184 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
185 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
186 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
189 * checks if a node's value can be encoded as a immediate
191 static bool is_imm_encodeable(const ir_node *node)
197 value = get_tarval_long(get_Const_tarval(node));
198 return sparc_is_value_imm_encodeable(value);
201 static bool needs_extension(ir_node *op)
203 ir_mode *mode = get_irn_mode(op);
204 unsigned gp_bits = get_mode_size_bits(mode_gp);
205 if (get_mode_size_bits(mode) >= gp_bits)
207 return !be_upper_bits_clean(op, mode);
211 * Check, if a given node is a Down-Conv, i.e. a integer Conv
212 * from a mode with a mode with more bits to a mode with lesser bits.
213 * Moreover, we return only true if the node has not more than 1 user.
215 * @param node the node
216 * @return non-zero if node is a Down-Conv
218 static bool is_downconv(const ir_node *node)
226 src_mode = get_irn_mode(get_Conv_op(node));
227 dest_mode = get_irn_mode(node);
229 mode_needs_gp_reg(src_mode) &&
230 mode_needs_gp_reg(dest_mode) &&
231 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
234 static ir_node *skip_downconv(ir_node *node)
236 while (is_downconv(node)) {
237 node = get_Conv_op(node);
243 * helper function for binop operations
245 * @param new_reg register generation function ptr
246 * @param new_imm immediate generation function ptr
248 static ir_node *gen_helper_binop_args(ir_node *node,
249 ir_node *op1, ir_node *op2,
251 new_binop_reg_func new_reg,
252 new_binop_imm_func new_imm)
254 dbg_info *dbgi = get_irn_dbg_info(node);
255 ir_node *block = be_transform_node(get_nodes_block(node));
261 if (flags & MATCH_MODE_NEUTRAL) {
262 op1 = skip_downconv(op1);
263 op2 = skip_downconv(op2);
265 mode1 = get_irn_mode(op1);
266 mode2 = get_irn_mode(op2);
267 /* we shouldn't see 64bit code */
268 assert(get_mode_size_bits(mode1) <= 32);
269 assert(get_mode_size_bits(mode2) <= 32);
271 if (is_imm_encodeable(op2)) {
272 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
273 new_op1 = be_transform_node(op1);
274 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
275 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
277 return new_imm(dbgi, block, new_op1, NULL, immediate);
279 new_op2 = be_transform_node(op2);
280 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op2)) {
281 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
284 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
285 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
286 return new_imm(dbgi, block, new_op2, NULL, immediate);
289 new_op1 = be_transform_node(op1);
290 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
291 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
293 return new_reg(dbgi, block, new_op1, new_op2);
296 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
297 new_binop_reg_func new_reg,
298 new_binop_imm_func new_imm)
300 ir_node *op1 = get_binop_left(node);
301 ir_node *op2 = get_binop_right(node);
302 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
306 * helper function for FP binop operations
308 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
309 new_binop_fp_func new_func_single,
310 new_binop_fp_func new_func_double,
311 new_binop_fp_func new_func_quad)
313 ir_node *block = be_transform_node(get_nodes_block(node));
314 ir_node *op1 = get_binop_left(node);
315 ir_node *new_op1 = be_transform_node(op1);
316 ir_node *op2 = get_binop_right(node);
317 ir_node *new_op2 = be_transform_node(op2);
318 dbg_info *dbgi = get_irn_dbg_info(node);
319 unsigned bits = get_mode_size_bits(mode);
323 return new_func_single(dbgi, block, new_op1, new_op2, mode);
325 return new_func_double(dbgi, block, new_op1, new_op2, mode);
327 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
331 panic("unsupported mode %+F for float op", mode);
334 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
335 new_unop_fp_func new_func_single,
336 new_unop_fp_func new_func_double,
337 new_unop_fp_func new_func_quad)
339 ir_node *block = be_transform_node(get_nodes_block(node));
340 ir_node *op = get_unop_op(node);
341 ir_node *new_op = be_transform_node(op);
342 dbg_info *dbgi = get_irn_dbg_info(node);
343 unsigned bits = get_mode_size_bits(mode);
347 return new_func_single(dbgi, block, new_op, mode);
349 return new_func_double(dbgi, block, new_op, mode);
351 return new_func_quad(dbgi, block, new_op, mode);
355 panic("unsupported mode %+F for float op", mode);
358 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
359 ir_node *op1, ir_node *flags,
360 ir_entity *imm_entity, int32_t imm);
362 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
363 ir_node *op1, ir_node *op2,
366 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
367 new_binopx_reg_func new_binopx_reg,
368 new_binopx_imm_func new_binopx_imm)
370 dbg_info *dbgi = get_irn_dbg_info(node);
371 ir_node *block = be_transform_node(get_nodes_block(node));
372 ir_node *op1 = get_irn_n(node, 0);
373 ir_node *op2 = get_irn_n(node, 1);
374 ir_node *flags = get_irn_n(node, 2);
375 ir_node *new_flags = be_transform_node(flags);
379 /* only support for mode-neutral implemented so far */
380 assert(match_flags & MATCH_MODE_NEUTRAL);
382 if (is_imm_encodeable(op2)) {
383 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
384 new_op1 = be_transform_node(op1);
385 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
387 new_op2 = be_transform_node(op2);
388 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
389 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
390 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
392 new_op1 = be_transform_node(op1);
393 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
397 static ir_node *get_reg(ir_graph *const irg, reg_info_t *const reg)
400 /* this is already the transformed start node */
401 ir_node *const start = get_irg_start(irg);
402 assert(is_sparc_Start(start));
403 arch_register_class_t const *const cls = arch_get_irn_register_req_out(start, reg->offset)->cls;
404 reg->irn = new_r_Proj(start, cls ? cls->mode : mode_M, reg->offset);
409 static ir_node *get_g0(ir_graph *irg)
411 return get_reg(irg, &start_g0);
414 static ir_node *get_g7(ir_graph *irg)
416 return get_reg(irg, &start_g7);
419 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
420 ir_entity *entity, int32_t offset)
422 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
423 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
427 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
430 if (get_entity_owner(entity) == get_tls_type()) {
431 ir_graph *irg = get_irn_irg(block);
432 ir_node *g7 = get_g7(irg);
433 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
434 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
437 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
438 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
443 typedef struct address_t {
451 * Match a load/store address
453 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
456 ir_node *ptr2 = NULL;
458 ir_entity *entity = NULL;
461 ir_node *add_right = get_Add_right(base);
462 if (is_Const(add_right)) {
463 base = get_Add_left(base);
464 offset += get_tarval_long(get_Const_tarval(add_right));
467 /* Note that we don't match sub(x, Const) or chains of adds/subs
468 * because this should all be normalized by now */
470 /* we only use the symconst if we're the only user otherwise we probably
471 * won't save anything but produce multiple sethi+or combinations with
472 * just different offsets */
473 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
474 ir_entity *sc_entity = get_SymConst_entity(base);
475 dbg_info *dbgi = get_irn_dbg_info(ptr);
476 ir_node *block = get_nodes_block(ptr);
477 ir_node *new_block = be_transform_node(block);
479 if (get_entity_owner(sc_entity) == get_tls_type()) {
483 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
485 base = get_g7(get_irn_irg(base));
489 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
491 } else if (use_ptr2 && is_Add(base) && offset == 0) {
492 ptr2 = be_transform_node(get_Add_right(base));
493 base = be_transform_node(get_Add_left(base));
496 if (sparc_is_value_imm_encodeable(offset)) {
497 base = be_transform_node(base);
499 base = be_transform_node(ptr);
505 address->ptr2 = ptr2;
506 address->entity = entity;
507 address->offset = offset;
511 * Creates an sparc Add.
513 * @param node FIRM node
514 * @return the created sparc Add node
516 static ir_node *gen_Add(ir_node *node)
518 ir_mode *mode = get_irn_mode(node);
521 if (mode_is_float(mode)) {
522 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
523 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
526 /* special case: + 0x1000 can be represented as - 0x1000 */
527 right = get_Add_right(node);
528 if (is_Const(right)) {
529 ir_node *left = get_Add_left(node);
532 /* is this simple address arithmetic? then we can let the linker do
533 * the calculation. */
534 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
535 dbg_info *dbgi = get_irn_dbg_info(node);
536 ir_node *block = be_transform_node(get_nodes_block(node));
539 /* the value of use_ptr2 shouldn't matter here */
540 match_address(node, &address, false);
541 assert(is_sparc_SetHi(address.ptr));
542 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
543 address.entity, address.offset);
546 tv = get_Const_tarval(right);
547 val = get_tarval_long(tv);
549 dbg_info *dbgi = get_irn_dbg_info(node);
550 ir_node *block = be_transform_node(get_nodes_block(node));
551 ir_node *op = get_Add_left(node);
552 ir_node *new_op = be_transform_node(op);
553 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
557 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
558 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
561 static ir_node *gen_AddCC_t(ir_node *node)
563 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
564 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
567 static ir_node *gen_Proj_AddCC_t(ir_node *node)
569 long pn = get_Proj_proj(node);
570 ir_node *pred = get_Proj_pred(node);
571 ir_node *new_pred = be_transform_node(pred);
574 case pn_sparc_AddCC_t_res:
575 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
576 case pn_sparc_AddCC_t_flags:
577 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
579 panic("Invalid proj found");
583 static ir_node *gen_AddX_t(ir_node *node)
585 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
586 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
590 * Creates an sparc Sub.
592 * @param node FIRM node
593 * @return the created sparc Sub node
595 static ir_node *gen_Sub(ir_node *node)
597 ir_mode *mode = get_irn_mode(node);
599 if (mode_is_float(mode)) {
600 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
601 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
604 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
605 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
608 static ir_node *gen_SubCC_t(ir_node *node)
610 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
611 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
614 static ir_node *gen_Proj_SubCC_t(ir_node *node)
616 long pn = get_Proj_proj(node);
617 ir_node *pred = get_Proj_pred(node);
618 ir_node *new_pred = be_transform_node(pred);
621 case pn_sparc_SubCC_t_res:
622 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
623 case pn_sparc_SubCC_t_flags:
624 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
626 panic("Invalid proj found");
630 static ir_node *gen_SubX_t(ir_node *node)
632 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
633 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
636 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
637 ir_node *mem, ir_mode *mode, ir_entity *entity,
638 long offset, bool is_frame_entity)
640 unsigned bits = get_mode_size_bits(mode);
641 assert(mode_is_float(mode));
643 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
644 offset, is_frame_entity);
645 } else if (bits == 64) {
646 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
647 offset, is_frame_entity);
650 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
651 offset, is_frame_entity);
655 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
656 ir_node *ptr, ir_node *mem, ir_mode *mode,
657 ir_entity *entity, long offset,
658 bool is_frame_entity)
660 unsigned bits = get_mode_size_bits(mode);
661 assert(mode_is_float(mode));
663 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
664 offset, is_frame_entity);
665 } else if (bits == 64) {
666 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
667 offset, is_frame_entity);
670 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
671 offset, is_frame_entity);
678 * @param node the ir Load node
679 * @return the created sparc Load node
681 static ir_node *gen_Load(ir_node *node)
683 dbg_info *dbgi = get_irn_dbg_info(node);
684 ir_mode *mode = get_Load_mode(node);
685 ir_node *block = be_transform_node(get_nodes_block(node));
686 ir_node *ptr = get_Load_ptr(node);
687 ir_node *mem = get_Load_mem(node);
688 ir_node *new_mem = be_transform_node(mem);
689 ir_node *new_load = NULL;
692 if (get_Load_unaligned(node) == align_non_aligned) {
693 panic("transformation of unaligned Loads not implemented yet");
696 if (mode_is_float(mode)) {
697 match_address(ptr, &address, false);
698 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
699 address.entity, address.offset, false);
701 match_address(ptr, &address, true);
702 if (address.ptr2 != NULL) {
703 assert(address.entity == NULL && address.offset == 0);
704 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
705 address.ptr2, new_mem, mode);
707 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
708 mode, address.entity, address.offset,
712 set_irn_pinned(new_load, get_irn_pinned(node));
718 * Transforms a Store.
720 * @param node the ir Store node
721 * @return the created sparc Store node
723 static ir_node *gen_Store(ir_node *node)
725 ir_node *block = be_transform_node(get_nodes_block(node));
726 ir_node *ptr = get_Store_ptr(node);
727 ir_node *mem = get_Store_mem(node);
728 ir_node *new_mem = be_transform_node(mem);
729 ir_node *val = get_Store_value(node);
730 ir_mode *mode = get_irn_mode(val);
731 dbg_info *dbgi = get_irn_dbg_info(node);
732 ir_node *new_store = NULL;
735 if (get_Store_unaligned(node) == align_non_aligned) {
736 panic("transformation of unaligned Stores not implemented yet");
739 if (mode_is_float(mode)) {
740 ir_node *new_val = be_transform_node(val);
741 /* TODO: variants with reg+reg address mode */
742 match_address(ptr, &address, false);
743 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
744 mode, address.entity, address.offset, false);
747 unsigned dest_bits = get_mode_size_bits(mode);
748 while (is_downconv(node)
749 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
750 val = get_Conv_op(val);
752 new_val = be_transform_node(val);
754 assert(dest_bits <= 32);
755 match_address(ptr, &address, true);
756 if (address.ptr2 != NULL) {
757 assert(address.entity == NULL && address.offset == 0);
758 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
759 address.ptr2, new_mem, mode);
761 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
762 new_mem, mode, address.entity,
763 address.offset, false);
766 set_irn_pinned(new_store, get_irn_pinned(node));
772 * Creates an sparc Mul.
773 * returns the lower 32bits of the 64bit multiply result
775 * @return the created sparc Mul node
777 static ir_node *gen_Mul(ir_node *node)
779 ir_mode *mode = get_irn_mode(node);
780 if (mode_is_float(mode)) {
781 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
782 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
785 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
786 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
790 * Creates an sparc Mulh.
791 * Mulh returns the upper 32bits of a mul instruction
793 * @return the created sparc Mulh node
795 static ir_node *gen_Mulh(ir_node *node)
797 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode))
801 panic("FP not supported yet");
803 if (mode_is_signed(mode)) {
804 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
805 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
807 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
808 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
812 static ir_node *gen_sign_extension_value(ir_node *node)
814 ir_node *block = get_nodes_block(node);
815 ir_node *new_block = be_transform_node(block);
816 ir_node *new_node = be_transform_node(node);
817 /* TODO: we could do some shortcuts for some value types probably.
818 * (For constants or other cases where we know the sign bit in
820 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
824 * Creates an sparc Div.
826 * @return the created sparc Div node
828 static ir_node *gen_Div(ir_node *node)
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *block = get_nodes_block(node);
832 ir_node *new_block = be_transform_node(block);
833 ir_mode *mode = get_Div_resmode(node);
834 ir_node *left = get_Div_left(node);
835 ir_node *left_low = be_transform_node(left);
836 ir_node *right = get_Div_right(node);
839 if (mode_is_float(mode)) {
840 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
841 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
844 if (mode_is_signed(mode)) {
845 ir_node *left_high = gen_sign_extension_value(left);
847 if (is_imm_encodeable(right)) {
848 int32_t immediate = get_tarval_long(get_Const_tarval(right));
849 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
852 ir_node *new_right = be_transform_node(right);
853 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
857 ir_graph *irg = get_irn_irg(node);
858 ir_node *left_high = get_g0(irg);
859 if (is_imm_encodeable(right)) {
860 int32_t immediate = get_tarval_long(get_Const_tarval(right));
861 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
864 ir_node *new_right = be_transform_node(right);
865 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
874 * Transforms a Not node.
876 * @return the created sparc Not node
878 static ir_node *gen_Not(ir_node *node)
880 ir_node *op = get_Not_op(node);
881 ir_graph *irg = get_irn_irg(node);
882 ir_node *zero = get_g0(irg);
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *block = be_transform_node(get_nodes_block(node));
885 ir_node *new_op = be_transform_node(op);
887 /* Note: Not(Eor()) is normalize in firm localopts already so
888 * we don't match it for xnor here */
890 /* Not can be represented with xnor 0, n */
891 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
894 static ir_node *gen_helper_bitop(ir_node *node,
895 new_binop_reg_func new_reg,
896 new_binop_imm_func new_imm,
897 new_binop_reg_func new_not_reg,
898 new_binop_imm_func new_not_imm,
901 ir_node *op1 = get_binop_left(node);
902 ir_node *op2 = get_binop_right(node);
904 return gen_helper_binop_args(node, op2, get_Not_op(op1),
906 new_not_reg, new_not_imm);
909 return gen_helper_binop_args(node, op1, get_Not_op(op2),
911 new_not_reg, new_not_imm);
913 if (is_Const(op2) && get_irn_n_edges(op2) == 1) {
914 ir_tarval *tv = get_Const_tarval(op2);
915 long value = get_tarval_long(tv);
916 if (!sparc_is_value_imm_encodeable(value)) {
917 long notvalue = ~value;
918 if ((notvalue & 0x3ff) == 0) {
919 ir_node *block = get_nodes_block(node);
920 ir_node *new_block = be_transform_node(block);
921 dbg_info *dbgi = get_irn_dbg_info(node);
923 = new_bd_sparc_SetHi(NULL, new_block, NULL, notvalue);
924 ir_node *new_op1 = be_transform_node(op1);
926 = new_not_reg(dbgi, new_block, new_op1, new_op2);
931 return gen_helper_binop_args(node, op1, op2,
932 flags | MATCH_COMMUTATIVE,
936 static ir_node *gen_And(ir_node *node)
938 return gen_helper_bitop(node,
939 new_bd_sparc_And_reg,
940 new_bd_sparc_And_imm,
941 new_bd_sparc_AndN_reg,
942 new_bd_sparc_AndN_imm,
946 static ir_node *gen_Or(ir_node *node)
948 return gen_helper_bitop(node,
951 new_bd_sparc_OrN_reg,
952 new_bd_sparc_OrN_imm,
956 static ir_node *gen_Eor(ir_node *node)
958 return gen_helper_bitop(node,
959 new_bd_sparc_Xor_reg,
960 new_bd_sparc_Xor_imm,
961 new_bd_sparc_XNor_reg,
962 new_bd_sparc_XNor_imm,
966 static ir_node *gen_Shl(ir_node *node)
968 ir_mode *mode = get_irn_mode(node);
969 if (get_mode_modulo_shift(mode) != 32)
970 panic("modulo_shift!=32 not supported");
971 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
974 static ir_node *gen_Shr(ir_node *node)
976 ir_mode *mode = get_irn_mode(node);
977 if (get_mode_modulo_shift(mode) != 32)
978 panic("modulo_shift!=32 not supported");
979 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
982 static ir_node *gen_Shrs(ir_node *node)
984 ir_mode *mode = get_irn_mode(node);
985 if (get_mode_modulo_shift(mode) != 32)
986 panic("modulo_shift!=32 not supported");
987 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
991 * Transforms a Minus node.
993 static ir_node *gen_Minus(ir_node *node)
995 ir_mode *mode = get_irn_mode(node);
1002 if (mode_is_float(mode)) {
1003 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
1004 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
1006 block = be_transform_node(get_nodes_block(node));
1007 dbgi = get_irn_dbg_info(node);
1008 op = get_Minus_op(node);
1009 new_op = be_transform_node(op);
1010 zero = get_g0(get_irn_irg(node));
1011 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1015 * Create an entity for a given (floating point) tarval
1017 static ir_entity *create_float_const_entity(ir_graph *const irg, ir_tarval *const tv)
1019 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1020 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1021 ir_entity *entity = pmap_get(ir_entity, isa->constants, tv);
1022 ir_initializer_t *initializer;
1030 mode = get_tarval_mode(tv);
1031 type = get_type_for_mode(mode);
1032 glob = get_glob_type();
1033 entity = new_entity(glob, id_unique("C%u"), type);
1034 set_entity_visibility(entity, ir_visibility_private);
1035 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1037 initializer = create_initializer_tarval(tv);
1038 set_entity_initializer(entity, initializer);
1040 pmap_insert(isa->constants, tv, entity);
1044 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1046 ir_graph *irg = get_Block_irg(block);
1047 ir_entity *entity = create_float_const_entity(irg, tv);
1048 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1049 ir_node *mem = get_irg_no_mem(irg);
1050 ir_mode *mode = get_tarval_mode(tv);
1052 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1053 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1055 set_irn_pinned(new_op, op_pin_state_floats);
1059 static ir_node *create_int_const(ir_node *block, int32_t value)
1062 ir_graph *irg = get_irn_irg(block);
1064 } else if (sparc_is_value_imm_encodeable(value)) {
1065 ir_graph *irg = get_irn_irg(block);
1066 return new_bd_sparc_Or_imm(NULL, block, get_g0(irg), NULL, value);
1068 ir_node *hi = new_bd_sparc_SetHi(NULL, block, NULL, value);
1069 if ((value & 0x3ff) != 0) {
1070 return new_bd_sparc_Or_imm(NULL, block, hi, NULL, value & 0x3ff);
1077 static ir_node *gen_Const(ir_node *node)
1079 ir_node *block = be_transform_node(get_nodes_block(node));
1080 ir_mode *mode = get_irn_mode(node);
1081 dbg_info *dbgi = get_irn_dbg_info(node);
1082 ir_tarval *tv = get_Const_tarval(node);
1085 if (mode_is_float(mode)) {
1086 return gen_float_const(dbgi, block, tv);
1089 assert(get_mode_size_bits(get_tarval_mode(tv)) <= 32);
1090 val = (int32_t)get_tarval_long(tv);
1091 return create_int_const(block, val);
1094 static ir_node *gen_Switch(ir_node *node)
1096 dbg_info *dbgi = get_irn_dbg_info(node);
1097 ir_node *block = get_nodes_block(node);
1098 ir_node *new_block = be_transform_node(block);
1099 ir_graph *irg = get_irn_irg(block);
1100 ir_node *selector = get_Switch_selector(node);
1101 ir_node *new_selector = be_transform_node(selector);
1102 const ir_switch_table *table = get_Switch_table(node);
1103 unsigned n_outs = get_Switch_n_outs(node);
1105 ir_node *table_address;
1110 table = ir_switch_table_duplicate(irg, table);
1112 /* switch with smaller mode not implemented yet */
1113 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1115 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1116 set_entity_visibility(entity, ir_visibility_private);
1117 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1119 /* construct base address */
1120 table_address = make_address(dbgi, new_block, entity, 0);
1122 idx = new_bd_sparc_Sll_imm(dbgi, new_block, new_selector, NULL, 2);
1123 /* load from jumptable */
1124 load = new_bd_sparc_Ld_reg(dbgi, new_block, table_address, idx,
1125 get_irg_no_mem(irg),
1127 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1129 return new_bd_sparc_SwitchJmp(dbgi, new_block, address, n_outs, table, entity);
1132 static ir_node *gen_Cond(ir_node *node)
1134 ir_node *selector = get_Cond_selector(node);
1139 ir_relation relation;
1142 /* note: after lower_mode_b we are guaranteed to have a Cmp input */
1143 block = be_transform_node(get_nodes_block(node));
1144 dbgi = get_irn_dbg_info(node);
1145 cmp_left = get_Cmp_left(selector);
1146 cmp_mode = get_irn_mode(cmp_left);
1147 flag_node = be_transform_node(selector);
1148 relation = get_Cmp_relation(selector);
1149 if (mode_is_float(cmp_mode)) {
1150 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1152 bool is_unsigned = !mode_is_signed(cmp_mode);
1153 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1160 static ir_node *gen_Cmp(ir_node *node)
1162 ir_node *op1 = get_Cmp_left(node);
1163 ir_node *op2 = get_Cmp_right(node);
1164 ir_mode *cmp_mode = get_irn_mode(op1);
1165 assert(get_irn_mode(op2) == cmp_mode);
1167 if (mode_is_float(cmp_mode)) {
1168 ir_node *block = be_transform_node(get_nodes_block(node));
1169 dbg_info *dbgi = get_irn_dbg_info(node);
1170 ir_node *new_op1 = be_transform_node(op1);
1171 ir_node *new_op2 = be_transform_node(op2);
1172 unsigned bits = get_mode_size_bits(cmp_mode);
1174 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1175 } else if (bits == 64) {
1176 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1178 assert(bits == 128);
1179 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1183 /* when we compare a bitop like and,or,... with 0 then we can directly use
1184 * the bitopcc variant.
1185 * Currently we only do this when we're the only user of the node...
1187 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1189 return gen_helper_bitop(op1,
1190 new_bd_sparc_AndCCZero_reg,
1191 new_bd_sparc_AndCCZero_imm,
1192 new_bd_sparc_AndNCCZero_reg,
1193 new_bd_sparc_AndNCCZero_imm,
1195 } else if (is_Or(op1)) {
1196 return gen_helper_bitop(op1,
1197 new_bd_sparc_OrCCZero_reg,
1198 new_bd_sparc_OrCCZero_imm,
1199 new_bd_sparc_OrNCCZero_reg,
1200 new_bd_sparc_OrNCCZero_imm,
1202 } else if (is_Eor(op1)) {
1203 return gen_helper_bitop(op1,
1204 new_bd_sparc_XorCCZero_reg,
1205 new_bd_sparc_XorCCZero_imm,
1206 new_bd_sparc_XNorCCZero_reg,
1207 new_bd_sparc_XNorCCZero_imm,
1209 } else if (is_Add(op1)) {
1210 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1211 new_bd_sparc_AddCCZero_reg,
1212 new_bd_sparc_AddCCZero_imm);
1213 } else if (is_Sub(op1)) {
1214 return gen_helper_binop(op1, MATCH_NONE,
1215 new_bd_sparc_SubCCZero_reg,
1216 new_bd_sparc_SubCCZero_imm);
1217 } else if (is_Mul(op1)) {
1218 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1219 new_bd_sparc_MulCCZero_reg,
1220 new_bd_sparc_MulCCZero_imm);
1224 /* integer compare */
1225 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1226 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1230 * Transforms a SymConst node.
1232 static ir_node *gen_SymConst(ir_node *node)
1234 ir_entity *entity = get_SymConst_entity(node);
1235 dbg_info *dbgi = get_irn_dbg_info(node);
1236 ir_node *block = get_nodes_block(node);
1237 ir_node *new_block = be_transform_node(block);
1238 return make_address(dbgi, new_block, entity, 0);
1241 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1242 ir_mode *src_mode, ir_mode *dst_mode)
1244 unsigned src_bits = get_mode_size_bits(src_mode);
1245 unsigned dst_bits = get_mode_size_bits(dst_mode);
1246 if (src_bits == 32) {
1247 if (dst_bits == 64) {
1248 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1250 assert(dst_bits == 128);
1251 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1253 } else if (src_bits == 64) {
1254 if (dst_bits == 32) {
1255 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1257 assert(dst_bits == 128);
1258 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1261 assert(src_bits == 128);
1262 if (dst_bits == 32) {
1263 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1265 assert(dst_bits == 64);
1266 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1271 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1275 unsigned bits = get_mode_size_bits(src_mode);
1277 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1278 } else if (bits == 64) {
1279 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1281 assert(bits == 128);
1282 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1286 ir_graph *irg = get_irn_irg(block);
1287 ir_node *sp = get_irg_frame(irg);
1288 ir_node *nomem = get_irg_no_mem(irg);
1289 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, mode_fp,
1291 arch_add_irn_flags(stf, arch_irn_flags_spill);
1292 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1294 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1295 set_irn_pinned(stf, op_pin_state_floats);
1296 set_irn_pinned(ld, op_pin_state_floats);
1301 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1304 ir_graph *irg = get_irn_irg(block);
1305 ir_node *sp = get_irg_frame(irg);
1306 ir_node *nomem = get_irg_no_mem(irg);
1307 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1308 mode_gp, NULL, 0, true);
1309 arch_add_irn_flags(st, arch_irn_flags_spill);
1310 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1312 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1313 unsigned bits = get_mode_size_bits(dst_mode);
1314 set_irn_pinned(st, op_pin_state_floats);
1315 set_irn_pinned(ldf, op_pin_state_floats);
1318 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1319 } else if (bits == 64) {
1320 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1322 assert(bits == 128);
1323 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1327 static ir_node *gen_Conv(ir_node *node)
1329 ir_node *block = be_transform_node(get_nodes_block(node));
1330 ir_node *op = get_Conv_op(node);
1331 ir_mode *src_mode = get_irn_mode(op);
1332 ir_mode *dst_mode = get_irn_mode(node);
1333 dbg_info *dbgi = get_irn_dbg_info(node);
1336 int src_bits = get_mode_size_bits(src_mode);
1337 int dst_bits = get_mode_size_bits(dst_mode);
1339 if (src_mode == mode_b)
1340 panic("ConvB not lowered %+F", node);
1342 if (src_mode == dst_mode)
1343 return be_transform_node(op);
1345 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1346 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1348 new_op = be_transform_node(op);
1349 if (mode_is_float(src_mode)) {
1350 if (mode_is_float(dst_mode)) {
1351 /* float -> float conv */
1352 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1354 /* float -> int conv */
1355 if (!mode_is_signed(dst_mode))
1356 panic("float to unsigned not lowered");
1357 return create_ftoi(dbgi, block, new_op, src_mode);
1360 /* int -> float conv */
1361 if (src_bits < 32) {
1362 new_op = gen_extension(dbgi, block, new_op, src_mode);
1363 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1364 panic("unsigned to float not lowered!");
1366 return create_itof(dbgi, block, new_op, dst_mode);
1368 } else { /* complete in gp registers */
1369 if (src_bits >= dst_bits || dst_mode == mode_b) {
1370 /* kill unnecessary conv */
1371 return be_transform_node(op);
1374 if (be_upper_bits_clean(op, src_mode)) {
1375 return be_transform_node(op);
1377 new_op = be_transform_node(op);
1379 if (mode_is_signed(src_mode)) {
1380 return gen_sign_extension(dbgi, block, new_op, src_bits);
1382 return gen_zero_extension(dbgi, block, new_op, src_bits);
1387 static ir_node *gen_Unknown(ir_node *node)
1389 /* just produce a 0 */
1390 ir_mode *mode = get_irn_mode(node);
1391 if (mode_is_float(mode)) {
1392 ir_node *block = be_transform_node(get_nodes_block(node));
1393 return gen_float_const(NULL, block, get_mode_null(mode));
1394 } else if (mode_needs_gp_reg(mode)) {
1395 ir_graph *irg = get_irn_irg(node);
1399 panic("Unexpected Unknown mode");
1402 static void make_start_out(reg_info_t *const info, struct obstack *const obst, ir_node *const start, size_t const offset, arch_register_t const *const reg, arch_register_req_type_t const flags)
1404 info->offset = offset;
1406 arch_register_req_t const *const req = be_create_reg_req(obst, reg, arch_register_req_type_ignore | flags);
1407 arch_set_irn_register_req_out(start, offset, req);
1408 arch_set_irn_register_out(start, offset, reg);
1412 * transform the start node to the prolog code
1414 static ir_node *gen_Start(ir_node *node)
1416 ir_graph *irg = get_irn_irg(node);
1417 ir_entity *entity = get_irg_entity(irg);
1418 ir_type *function_type = get_entity_type(entity);
1419 ir_node *block = get_nodes_block(node);
1420 ir_node *new_block = be_transform_node(block);
1421 dbg_info *dbgi = get_irn_dbg_info(node);
1422 struct obstack *obst = be_get_be_obst(irg);
1427 /* start building list of start constraints */
1429 /* calculate number of outputs */
1430 n_outs = 4; /* memory, g0, g7, sp */
1431 if (!current_cconv->omit_fp)
1432 ++n_outs; /* framepointer */
1433 /* function parameters */
1434 n_outs += current_cconv->n_param_regs;
1436 if (current_cconv->omit_fp) {
1437 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1440 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1444 /* first output is memory */
1445 start_mem.offset = o;
1446 start_mem.irn = NULL;
1447 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1450 /* the zero register */
1451 make_start_out(&start_g0, obst, start, o++, &sparc_registers[REG_G0], arch_register_req_type_none);
1453 /* g7 is used for TLS data */
1454 make_start_out(&start_g7, obst, start, o++, &sparc_registers[REG_G7], arch_register_req_type_none);
1456 /* we need an output for the stackpointer */
1457 make_start_out(&start_sp, obst, start, o++, sp_reg, arch_register_req_type_produces_sp);
1459 if (!current_cconv->omit_fp) {
1460 make_start_out(&start_fp, obst, start, o++, fp_reg, arch_register_req_type_none);
1463 /* function parameters in registers */
1464 start_params_offset = o;
1465 for (i = 0; i < get_method_n_params(function_type); ++i) {
1466 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1467 const arch_register_t *reg0 = param->reg0;
1468 const arch_register_t *reg1 = param->reg1;
1470 arch_set_irn_register_req_out(start, o, reg0->single_req);
1471 arch_set_irn_register_out(start, o, reg0);
1475 arch_set_irn_register_req_out(start, o, reg1->single_req);
1476 arch_set_irn_register_out(start, o, reg1);
1480 /* we need the values of the callee saves (Note: non omit-fp mode has no
1482 start_callee_saves_offset = o;
1483 if (current_cconv->omit_fp) {
1484 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1486 for (c = 0; c < n_callee_saves; ++c) {
1487 const arch_register_t *reg = omit_fp_callee_saves[c];
1488 arch_set_irn_register_req_out(start, o, reg->single_req);
1489 arch_set_irn_register_out(start, o, reg);
1493 assert(n_outs == o);
1498 static ir_node *get_initial_sp(ir_graph *irg)
1500 return get_reg(irg, &start_sp);
1503 static ir_node *get_initial_fp(ir_graph *irg)
1505 return get_reg(irg, &start_fp);
1508 static ir_node *get_initial_mem(ir_graph *irg)
1510 return get_reg(irg, &start_mem);
1513 static ir_node *get_stack_pointer_for(ir_node *node)
1515 /* get predecessor in stack_order list */
1516 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1519 if (stack_pred == NULL) {
1520 /* first stack user in the current block. We can simply use the
1521 * initial sp_proj for it */
1522 ir_graph *irg = get_irn_irg(node);
1523 return get_initial_sp(irg);
1526 be_transform_node(stack_pred);
1527 stack = pmap_get(ir_node, node_to_stack, stack_pred);
1528 if (stack == NULL) {
1529 return get_stack_pointer_for(stack_pred);
1536 * transform a Return node into epilogue code + return statement
1538 static ir_node *gen_Return(ir_node *node)
1540 ir_node *block = get_nodes_block(node);
1541 ir_graph *irg = get_irn_irg(node);
1542 ir_node *new_block = be_transform_node(block);
1543 dbg_info *dbgi = get_irn_dbg_info(node);
1544 ir_node *mem = get_Return_mem(node);
1545 ir_node *new_mem = be_transform_node(mem);
1546 ir_node *sp = get_stack_pointer_for(node);
1547 size_t n_res = get_Return_n_ress(node);
1548 struct obstack *be_obst = be_get_be_obst(irg);
1551 const arch_register_req_t **reqs;
1556 /* estimate number of return values */
1557 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1558 if (current_cconv->omit_fp)
1559 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1561 in = ALLOCAN(ir_node*, n_ins);
1562 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1566 reqs[p] = arch_no_register_req;
1570 reqs[p] = sp_reg->single_req;
1574 for (i = 0; i < n_res; ++i) {
1575 ir_node *res_value = get_Return_res(node, i);
1576 ir_node *new_res_value = be_transform_node(res_value);
1577 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1578 assert(slot->req1 == NULL);
1579 in[p] = new_res_value;
1580 reqs[p] = slot->req0;
1584 if (current_cconv->omit_fp) {
1585 ir_node *start = get_irg_start(irg);
1586 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1587 for (i = 0; i < n_callee_saves; ++i) {
1588 const arch_register_t *reg = omit_fp_callee_saves[i];
1589 ir_mode *mode = reg->reg_class->mode;
1591 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1593 reqs[p] = reg->single_req;
1599 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1600 arch_set_irn_register_reqs_in(bereturn, reqs);
1605 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1606 ir_node *value0, ir_node *value1)
1608 ir_graph *irg = get_Block_irg(block);
1609 ir_node *sp = get_irg_frame(irg);
1610 ir_node *nomem = get_irg_no_mem(irg);
1611 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1612 mode_gp, NULL, 0, true);
1616 arch_add_irn_flags(st, arch_irn_flags_spill);
1617 set_irn_pinned(st, op_pin_state_floats);
1619 if (value1 != NULL) {
1620 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1621 mode_gp, NULL, 4, true);
1622 arch_add_irn_flags(st1, arch_irn_flags_spill);
1623 ir_node *in[2] = { st, st1 };
1624 ir_node *sync = new_r_Sync(block, 2, in);
1625 set_irn_pinned(st1, op_pin_state_floats);
1633 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1634 set_irn_pinned(ldf, op_pin_state_floats);
1636 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1639 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1640 ir_node *value, ir_mode *float_mode,
1643 int bits = get_mode_size_bits(float_mode);
1644 if (is_Const(value)) {
1645 ir_tarval *tv = get_Const_tarval(value);
1646 int32_t val = get_tarval_sub_bits(tv, 0) |
1647 (get_tarval_sub_bits(tv, 1) << 8) |
1648 (get_tarval_sub_bits(tv, 2) << 16) |
1649 (get_tarval_sub_bits(tv, 3) << 24);
1650 ir_node *valc = create_int_const(block, val);
1652 int32_t val2 = get_tarval_sub_bits(tv, 4) |
1653 (get_tarval_sub_bits(tv, 5) << 8) |
1654 (get_tarval_sub_bits(tv, 6) << 16) |
1655 (get_tarval_sub_bits(tv, 7) << 24);
1656 ir_node *valc2 = create_int_const(block, val2);
1665 ir_graph *irg = get_Block_irg(block);
1666 ir_node *stack = get_irg_frame(irg);
1667 ir_node *nomem = get_irg_no_mem(irg);
1668 ir_node *new_value = be_transform_node(value);
1669 ir_node *stf = create_stf(dbgi, block, new_value, stack, nomem,
1670 float_mode, NULL, 0, true);
1672 arch_add_irn_flags(stf, arch_irn_flags_spill);
1673 set_irn_pinned(stf, op_pin_state_floats);
1675 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1676 set_irn_pinned(ld, op_pin_state_floats);
1677 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1680 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1682 set_irn_pinned(ld, op_pin_state_floats);
1683 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1685 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1686 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1694 static ir_node *gen_Call(ir_node *node)
1696 ir_graph *irg = get_irn_irg(node);
1697 ir_node *callee = get_Call_ptr(node);
1698 ir_node *block = get_nodes_block(node);
1699 ir_node *new_block = be_transform_node(block);
1700 ir_node *mem = get_Call_mem(node);
1701 ir_node *new_mem = be_transform_node(mem);
1702 dbg_info *dbgi = get_irn_dbg_info(node);
1703 ir_type *type = get_Call_type(node);
1704 size_t n_params = get_Call_n_params(node);
1705 size_t n_ress = get_method_n_ress(type);
1706 /* max inputs: memory, callee, register arguments */
1707 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1708 struct obstack *obst = be_get_be_obst(irg);
1709 calling_convention_t *cconv
1710 = sparc_decide_calling_convention(type, NULL);
1711 size_t n_param_regs = cconv->n_param_regs;
1712 /* param-regs + mem + stackpointer + callee */
1713 unsigned max_inputs = 3 + n_param_regs;
1714 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1715 const arch_register_req_t **in_req
1716 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1720 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1721 ir_entity *entity = NULL;
1722 ir_node *new_frame = get_stack_pointer_for(node);
1723 bool aggregate_return
1724 = get_method_calling_convention(type) & cc_compound_ret;
1734 assert(n_params == get_method_n_params(type));
1736 /* construct arguments */
1739 in_req[in_arity] = arch_no_register_req;
1743 /* stack pointer input */
1744 /* construct an IncSP -> we have to always be sure that the stack is
1745 * aligned even if we don't push arguments on it */
1746 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1747 cconv->param_stack_size, 1);
1748 in_req[in_arity] = sp_reg->single_req;
1749 in[in_arity] = incsp;
1753 for (p = 0; p < n_params; ++p) {
1754 ir_node *value = get_Call_param(node, p);
1755 const reg_or_stackslot_t *param = &cconv->parameters[p];
1756 ir_type *param_type = get_method_param_type(type, p);
1757 ir_mode *mode = get_type_mode(param_type);
1758 ir_node *partial_value;
1759 ir_node *new_values[2];
1763 if (mode_is_float(mode) && param->reg0 != NULL) {
1764 unsigned size_bits = get_mode_size_bits(mode);
1765 assert(size_bits <= 64);
1766 bitcast_float_to_int(dbgi, new_block, value, mode, new_values);
1768 ir_node *new_value = be_transform_node(value);
1769 new_values[0] = new_value;
1770 new_values[1] = NULL;
1773 /* put value into registers */
1774 if (param->reg0 != NULL) {
1775 in[in_arity] = new_values[0];
1776 in_req[in_arity] = param->reg0->single_req;
1778 if (new_values[1] == NULL)
1781 if (param->reg1 != NULL) {
1782 assert(new_values[1] != NULL);
1783 in[in_arity] = new_values[1];
1784 in_req[in_arity] = param->reg1->single_req;
1789 /* we need a store if we're here */
1790 if (new_values[1] != NULL) {
1791 partial_value = new_values[1];
1794 partial_value = new_values[0];
1797 /* we need to skip over our save area when constructing the call
1798 * arguments on stack */
1799 offset = param->offset + SPARC_MIN_STACKSIZE;
1801 if (mode_is_float(mode)) {
1802 str = create_stf(dbgi, new_block, partial_value, incsp, new_mem,
1803 mode, NULL, offset, true);
1805 str = new_bd_sparc_St_imm(dbgi, new_block, partial_value, incsp,
1806 new_mem, mode, NULL, offset, true);
1808 set_irn_pinned(str, op_pin_state_floats);
1809 sync_ins[sync_arity++] = str;
1812 /* construct memory input */
1813 if (sync_arity == 0) {
1814 in[mem_pos] = new_mem;
1815 } else if (sync_arity == 1) {
1816 in[mem_pos] = sync_ins[0];
1818 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1821 if (is_SymConst(callee)) {
1822 entity = get_SymConst_entity(callee);
1824 in[in_arity] = be_transform_node(callee);
1825 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1828 assert(in_arity <= (int)max_inputs);
1835 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1837 /* create call node */
1838 if (entity != NULL) {
1839 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1840 entity, 0, aggregate_return);
1842 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1845 arch_set_irn_register_reqs_in(res, in_req);
1847 /* create output register reqs */
1849 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1850 /* add register requirements for the result regs */
1851 for (r = 0; r < n_ress; ++r) {
1852 const reg_or_stackslot_t *result_info = &cconv->results[r];
1853 const arch_register_req_t *req = result_info->req0;
1855 arch_set_irn_register_req_out(res, o++, req);
1857 assert(result_info->req1 == NULL);
1859 const unsigned *allocatable_regs = be_birg_from_irg(irg)->allocatable_regs;
1860 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1861 const arch_register_t *reg;
1862 if (!rbitset_is_set(cconv->caller_saves, i))
1864 reg = &sparc_registers[i];
1865 arch_set_irn_register_req_out(res, o, reg->single_req);
1866 if (!rbitset_is_set(allocatable_regs, reg->global_index))
1867 arch_set_irn_register_out(res, o, reg);
1870 assert(o == out_arity);
1872 /* copy pinned attribute */
1873 set_irn_pinned(res, get_irn_pinned(node));
1875 /* IncSP to destroy the call stackframe */
1876 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1877 /* if we are the last IncSP producer in a block then we have to keep
1879 * Note: This here keeps all producers which is more than necessary */
1880 add_irn_dep(incsp, res);
1883 pmap_insert(node_to_stack, node, incsp);
1885 sparc_free_calling_convention(cconv);
1889 static ir_node *gen_Sel(ir_node *node)
1891 dbg_info *dbgi = get_irn_dbg_info(node);
1892 ir_node *block = get_nodes_block(node);
1893 ir_node *new_block = be_transform_node(block);
1894 ir_node *ptr = get_Sel_ptr(node);
1895 ir_node *new_ptr = be_transform_node(ptr);
1896 ir_entity *entity = get_Sel_entity(node);
1898 /* must be the frame pointer all other sels must have been lowered
1900 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1902 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1905 static ir_node *gen_Alloc(ir_node *node)
1907 dbg_info *dbgi = get_irn_dbg_info(node);
1908 ir_node *block = get_nodes_block(node);
1909 ir_node *new_block = be_transform_node(block);
1910 ir_type *type = get_Alloc_type(node);
1911 ir_node *size = get_Alloc_count(node);
1912 ir_node *stack_pred = get_stack_pointer_for(node);
1913 ir_node *mem = get_Alloc_mem(node);
1914 ir_node *new_mem = be_transform_node(mem);
1917 if (get_Alloc_where(node) != stack_alloc)
1918 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1919 /* lowerer should have transformed all allocas to byte size */
1920 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
1921 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1923 if (is_Const(size)) {
1924 ir_tarval *tv = get_Const_tarval(size);
1925 long sizel = get_tarval_long(tv);
1927 assert((sizel & (SPARC_STACK_ALIGNMENT - 1)) == 0 && "Found Alloc with misaligned constant");
1928 subsp = new_bd_sparc_SubSP_imm(dbgi, new_block, stack_pred, new_mem, NULL, sizel);
1930 ir_node *new_size = be_transform_node(size);
1931 subsp = new_bd_sparc_SubSP_reg(dbgi, new_block, stack_pred, new_size, new_mem);
1934 ir_node *stack_proj = new_r_Proj(subsp, mode_gp, pn_sparc_SubSP_stack);
1935 arch_set_irn_register(stack_proj, sp_reg);
1936 /* If we are the last stack producer in a block, we have to keep the
1937 * stack value. This keeps all producers, which is more than necessary. */
1938 keep_alive(stack_proj);
1940 pmap_insert(node_to_stack, node, stack_proj);
1945 static ir_node *gen_Proj_Alloc(ir_node *node)
1947 ir_node *alloc = get_Proj_pred(node);
1948 ir_node *new_alloc = be_transform_node(alloc);
1949 long pn = get_Proj_proj(node);
1951 switch ((pn_Alloc)pn) {
1952 case pn_Alloc_M: return new_r_Proj(new_alloc, mode_M, pn_sparc_SubSP_M);
1953 case pn_Alloc_res: return new_r_Proj(new_alloc, mode_gp, pn_sparc_SubSP_addr);
1955 case pn_Alloc_X_regular:
1956 case pn_Alloc_X_except:
1957 panic("exception output of alloc not supported (at %+F)",
1960 panic("invalid Proj->Alloc");
1963 static ir_node *gen_Free(ir_node *node)
1965 dbg_info *dbgi = get_irn_dbg_info(node);
1966 ir_node *block = get_nodes_block(node);
1967 ir_node *new_block = be_transform_node(block);
1968 ir_type *type = get_Free_type(node);
1969 ir_node *size = get_Free_count(node);
1970 ir_node *mem = get_Free_mem(node);
1971 ir_node *new_mem = be_transform_node(mem);
1972 ir_node *stack_pred = get_stack_pointer_for(node);
1974 if (get_Alloc_where(node) != stack_alloc)
1975 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1976 /* lowerer should have transformed all allocas to byte size */
1977 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
1978 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1980 if (is_Const(size)) {
1981 ir_tarval *tv = get_Const_tarval(size);
1982 long sizel = get_tarval_long(tv);
1983 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
1984 set_irn_dbg_info(addsp, dbgi);
1986 ir_node *new_size = be_transform_node(size);
1987 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
1988 arch_set_irn_register(addsp, sp_reg);
1991 /* if we are the last IncSP producer in a block then we have to keep
1993 * Note: This here keeps all producers which is more than necessary */
1996 pmap_insert(node_to_stack, node, addsp);
1997 /* the "result" is the unmodified sp value */
2001 static const arch_register_req_t float1_req = {
2002 arch_register_req_type_normal,
2003 &sparc_reg_classes[CLASS_sparc_fp],
2009 static const arch_register_req_t float2_req = {
2010 arch_register_req_type_normal | arch_register_req_type_aligned,
2011 &sparc_reg_classes[CLASS_sparc_fp],
2017 static const arch_register_req_t float4_req = {
2018 arch_register_req_type_normal | arch_register_req_type_aligned,
2019 &sparc_reg_classes[CLASS_sparc_fp],
2027 static const arch_register_req_t *get_float_req(ir_mode *mode)
2029 assert(mode_is_float(mode));
2030 switch (get_mode_size_bits(mode)) {
2031 case 32: return &float1_req;
2032 case 64: return &float2_req;
2033 case 128: return &float4_req;
2034 default: panic("invalid float mode");
2038 static ir_node *gen_Phi(ir_node *node)
2040 ir_mode *mode = get_irn_mode(node);
2041 const arch_register_req_t *req;
2042 if (mode_needs_gp_reg(mode)) {
2043 /* we shouldn't have any 64bit stuff around anymore */
2044 assert(get_mode_size_bits(mode) <= 32);
2045 /* all integer operations are on 32bit registers now */
2047 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2048 } else if (mode_is_float(mode)) {
2049 req = get_float_req(mode);
2051 req = arch_no_register_req;
2054 return be_transform_phi(node, req);
2058 * Transform a Proj from a Load.
2060 static ir_node *gen_Proj_Load(ir_node *node)
2062 ir_node *load = get_Proj_pred(node);
2063 ir_node *new_load = be_transform_node(load);
2064 dbg_info *dbgi = get_irn_dbg_info(node);
2065 long pn = get_Proj_proj(node);
2067 /* renumber the proj */
2068 switch (get_sparc_irn_opcode(new_load)) {
2070 /* handle all gp loads equal: they have the same proj numbers. */
2071 if (pn == pn_Load_res) {
2072 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2073 } else if (pn == pn_Load_M) {
2074 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2078 if (pn == pn_Load_res) {
2079 const sparc_load_store_attr_t *attr
2080 = get_sparc_load_store_attr_const(new_load);
2081 ir_mode *mode = attr->load_store_mode;
2082 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2083 } else if (pn == pn_Load_M) {
2084 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2090 panic("Unsupported Proj from Load");
2093 static ir_node *gen_Proj_Store(ir_node *node)
2095 ir_node *store = get_Proj_pred(node);
2096 ir_node *new_store = be_transform_node(store);
2097 long pn = get_Proj_proj(node);
2099 /* renumber the proj */
2100 switch (get_sparc_irn_opcode(new_store)) {
2102 if (pn == pn_Store_M) {
2107 if (pn == pn_Store_M) {
2114 panic("Unsupported Proj from Store");
2118 * transform Projs from a Div
2120 static ir_node *gen_Proj_Div(ir_node *node)
2122 ir_node *pred = get_Proj_pred(node);
2123 ir_node *new_pred = be_transform_node(pred);
2124 long pn = get_Proj_proj(node);
2127 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2129 } else if (is_sparc_fdiv(new_pred)) {
2130 res_mode = get_Div_resmode(pred);
2132 panic("Div transformed to something unexpected: %+F",
2135 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2136 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2137 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2138 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2141 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2143 return new_r_Proj(new_pred, mode_M, pn_sparc_SDiv_M);
2147 panic("Unsupported Proj from Div");
2150 static ir_node *get_frame_base(ir_graph *irg)
2152 if (frame_base == NULL) {
2153 if (current_cconv->omit_fp) {
2154 frame_base = get_initial_sp(irg);
2156 frame_base = get_initial_fp(irg);
2162 static ir_node *gen_Proj_Start(ir_node *node)
2164 ir_node *block = get_nodes_block(node);
2165 ir_node *new_block = be_transform_node(block);
2166 long pn = get_Proj_proj(node);
2167 /* make sure prolog is constructed */
2168 be_transform_node(get_Proj_pred(node));
2170 switch ((pn_Start) pn) {
2171 case pn_Start_X_initial_exec:
2172 /* exchange ProjX with a jump */
2173 return new_bd_sparc_Ba(NULL, new_block);
2175 ir_graph *irg = get_irn_irg(node);
2176 return get_initial_mem(irg);
2178 case pn_Start_T_args:
2179 return new_r_Bad(get_irn_irg(block), mode_T);
2180 case pn_Start_P_frame_base:
2181 return get_frame_base(get_irn_irg(block));
2183 panic("Unexpected start proj: %ld\n", pn);
2186 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2188 long pn = get_Proj_proj(node);
2189 ir_node *block = get_nodes_block(node);
2190 ir_graph *irg = get_irn_irg(node);
2191 ir_node *new_block = be_transform_node(block);
2192 ir_node *args = get_Proj_pred(node);
2193 ir_node *start = get_Proj_pred(args);
2194 ir_node *new_start = be_transform_node(start);
2195 const reg_or_stackslot_t *param;
2197 /* Proj->Proj->Start must be a method argument */
2198 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2200 param = ¤t_cconv->parameters[pn];
2202 if (param->reg0 != NULL) {
2203 /* argument transmitted in register */
2204 const arch_register_t *reg = param->reg0;
2205 ir_mode *reg_mode = reg->reg_class->mode;
2206 long new_pn = param->reg_offset + start_params_offset;
2207 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2208 bool is_float = false;
2211 ir_entity *entity = get_irg_entity(irg);
2212 ir_type *method_type = get_entity_type(entity);
2213 if (pn < (long)get_method_n_params(method_type)) {
2214 ir_type *param_type = get_method_param_type(method_type, pn);
2215 ir_mode *mode = get_type_mode(param_type);
2216 is_float = mode_is_float(mode);
2221 const arch_register_t *reg1 = param->reg1;
2222 ir_node *value1 = NULL;
2225 ir_mode *reg1_mode = reg1->reg_class->mode;
2226 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2227 } else if (param->entity != NULL) {
2228 ir_node *fp = get_initial_fp(irg);
2229 ir_node *mem = get_initial_mem(irg);
2230 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2231 mode_gp, param->entity,
2233 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2236 /* convert integer value to float */
2237 value = bitcast_int_to_float(NULL, new_block, value, value1);
2241 /* argument transmitted on stack */
2242 ir_node *mem = get_initial_mem(irg);
2243 ir_mode *mode = get_type_mode(param->type);
2244 ir_node *base = get_frame_base(irg);
2248 if (mode_is_float(mode)) {
2249 load = create_ldf(NULL, new_block, base, mem, mode,
2250 param->entity, 0, true);
2251 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2253 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2254 param->entity, 0, true);
2255 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2257 set_irn_pinned(load, op_pin_state_floats);
2263 static ir_node *gen_Proj_Call(ir_node *node)
2265 long pn = get_Proj_proj(node);
2266 ir_node *call = get_Proj_pred(node);
2267 ir_node *new_call = be_transform_node(call);
2269 switch ((pn_Call) pn) {
2271 return new_r_Proj(new_call, mode_M, 0);
2272 case pn_Call_X_regular:
2273 case pn_Call_X_except:
2274 case pn_Call_T_result:
2277 panic("Unexpected Call proj %ld\n", pn);
2280 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2282 long pn = get_Proj_proj(node);
2283 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2284 ir_node *new_call = be_transform_node(call);
2285 ir_type *function_type = get_Call_type(call);
2286 calling_convention_t *cconv
2287 = sparc_decide_calling_convention(function_type, NULL);
2288 const reg_or_stackslot_t *res = &cconv->results[pn];
2289 ir_mode *mode = get_irn_mode(node);
2290 long new_pn = 1 + res->reg_offset;
2292 assert(res->req0 != NULL && res->req1 == NULL);
2293 if (mode_needs_gp_reg(mode)) {
2296 sparc_free_calling_convention(cconv);
2298 return new_r_Proj(new_call, mode, new_pn);
2302 * Transform a Proj node.
2304 static ir_node *gen_Proj(ir_node *node)
2306 ir_node *pred = get_Proj_pred(node);
2308 switch (get_irn_opcode(pred)) {
2310 return gen_Proj_Alloc(node);
2312 return gen_Proj_Store(node);
2314 return gen_Proj_Load(node);
2316 return gen_Proj_Call(node);
2319 return be_duplicate_node(node);
2321 return gen_Proj_Div(node);
2323 return gen_Proj_Start(node);
2325 ir_node *pred_pred = get_Proj_pred(pred);
2326 if (is_Call(pred_pred)) {
2327 return gen_Proj_Proj_Call(node);
2328 } else if (is_Start(pred_pred)) {
2329 return gen_Proj_Proj_Start(node);
2334 if (is_sparc_AddCC_t(pred)) {
2335 return gen_Proj_AddCC_t(node);
2336 } else if (is_sparc_SubCC_t(pred)) {
2337 return gen_Proj_SubCC_t(node);
2339 panic("code selection didn't expect Proj after %+F\n", pred);
2346 static ir_node *gen_Jmp(ir_node *node)
2348 ir_node *block = get_nodes_block(node);
2349 ir_node *new_block = be_transform_node(block);
2350 dbg_info *dbgi = get_irn_dbg_info(node);
2352 return new_bd_sparc_Ba(dbgi, new_block);
2356 * configure transformation callbacks
2358 static void sparc_register_transformers(void)
2360 be_start_transform_setup();
2362 be_set_transform_function(op_Add, gen_Add);
2363 be_set_transform_function(op_Alloc, gen_Alloc);
2364 be_set_transform_function(op_And, gen_And);
2365 be_set_transform_function(op_Call, gen_Call);
2366 be_set_transform_function(op_Cmp, gen_Cmp);
2367 be_set_transform_function(op_Cond, gen_Cond);
2368 be_set_transform_function(op_Const, gen_Const);
2369 be_set_transform_function(op_Conv, gen_Conv);
2370 be_set_transform_function(op_Div, gen_Div);
2371 be_set_transform_function(op_Eor, gen_Eor);
2372 be_set_transform_function(op_Free, gen_Free);
2373 be_set_transform_function(op_Jmp, gen_Jmp);
2374 be_set_transform_function(op_Load, gen_Load);
2375 be_set_transform_function(op_Minus, gen_Minus);
2376 be_set_transform_function(op_Mul, gen_Mul);
2377 be_set_transform_function(op_Mulh, gen_Mulh);
2378 be_set_transform_function(op_Not, gen_Not);
2379 be_set_transform_function(op_Or, gen_Or);
2380 be_set_transform_function(op_Phi, gen_Phi);
2381 be_set_transform_function(op_Proj, gen_Proj);
2382 be_set_transform_function(op_Return, gen_Return);
2383 be_set_transform_function(op_Sel, gen_Sel);
2384 be_set_transform_function(op_Shl, gen_Shl);
2385 be_set_transform_function(op_Shr, gen_Shr);
2386 be_set_transform_function(op_Shrs, gen_Shrs);
2387 be_set_transform_function(op_Start, gen_Start);
2388 be_set_transform_function(op_Store, gen_Store);
2389 be_set_transform_function(op_Sub, gen_Sub);
2390 be_set_transform_function(op_Switch, gen_Switch);
2391 be_set_transform_function(op_SymConst, gen_SymConst);
2392 be_set_transform_function(op_Unknown, gen_Unknown);
2394 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2395 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2396 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2397 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2398 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2402 * Transform a Firm graph into a SPARC graph.
2404 void sparc_transform_graph(ir_graph *irg)
2406 ir_entity *entity = get_irg_entity(irg);
2407 ir_type *frame_type;
2409 sparc_register_transformers();
2411 node_to_stack = pmap_create();
2413 mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
2414 mode_fp = sparc_reg_classes[CLASS_sparc_fp].mode;
2417 mode_flags = sparc_reg_classes[CLASS_sparc_flags_class].mode;
2418 assert(sparc_reg_classes[CLASS_sparc_fpflags_class].mode == mode_flags);
2422 stackorder = be_collect_stacknodes(irg);
2424 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2425 if (sparc_variadic_fixups(irg, current_cconv)) {
2426 sparc_free_calling_convention(current_cconv);
2428 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2430 sparc_create_stacklayout(irg, current_cconv);
2431 be_add_parameter_entity_stores(irg);
2433 be_transform_graph(irg, NULL);
2435 be_free_stackorder(stackorder);
2436 sparc_free_calling_convention(current_cconv);
2438 frame_type = get_irg_frame_type(irg);
2439 if (get_type_state(frame_type) == layout_undefined)
2440 default_layout_compound_type(frame_type);
2442 pmap_destroy(node_to_stack);
2443 node_to_stack = NULL;
2445 be_add_missing_keeps(irg);
2447 /* do code placement, to optimize the position of constants */
2449 /* backend expects outedges to be always on */
2453 void sparc_init_transform(void)
2455 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");