2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
32 #include "irgraph_t.h"
38 #include "iroptimize.h"
48 #include "betranshlp.h"
49 #include "beabihelper.h"
50 #include "bearch_sparc_t.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_transform.h"
54 #include "sparc_new_nodes.h"
55 #include "gen_sparc_new_nodes.h"
57 #include "gen_sparc_regalloc_if.h"
58 #include "sparc_cconv.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *current_cconv = NULL;
67 static be_stackorder_t *stackorder;
68 static ir_mode *mode_gp;
69 static ir_mode *mode_flags;
70 static ir_mode *mode_fp;
71 static ir_mode *mode_fp2;
72 //static ir_mode *mode_fp4;
73 static pmap *node_to_stack;
74 static size_t start_mem_offset;
75 static ir_node *start_mem;
76 static size_t start_g0_offset;
77 static ir_node *start_g0;
78 static size_t start_g7_offset;
79 static ir_node *start_g7;
80 static size_t start_sp_offset;
81 static ir_node *start_sp;
82 static size_t start_fp_offset;
83 static ir_node *start_fp;
84 static ir_node *frame_base;
85 static size_t start_params_offset;
86 static size_t start_callee_saves_offset;
88 static const arch_register_t *const omit_fp_callee_saves[] = {
89 &sparc_registers[REG_L0],
90 &sparc_registers[REG_L1],
91 &sparc_registers[REG_L2],
92 &sparc_registers[REG_L3],
93 &sparc_registers[REG_L4],
94 &sparc_registers[REG_L5],
95 &sparc_registers[REG_L6],
96 &sparc_registers[REG_L7],
97 &sparc_registers[REG_I0],
98 &sparc_registers[REG_I1],
99 &sparc_registers[REG_I2],
100 &sparc_registers[REG_I3],
101 &sparc_registers[REG_I4],
102 &sparc_registers[REG_I5],
105 static inline bool mode_needs_gp_reg(ir_mode *mode)
107 if (mode_is_int(mode) || mode_is_reference(mode)) {
108 /* we should only see 32bit code */
109 assert(get_mode_size_bits(mode) <= 32);
116 * Create an And that will zero out upper bits.
118 * @param dbgi debug info
119 * @param block the basic block
120 * @param op the original node
121 * @param src_bits number of lower bits that will remain
123 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
127 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
128 } else if (src_bits == 16) {
129 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
130 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
133 panic("zero extension only supported for 8 and 16 bits");
138 * Generate code for a sign extension.
140 * @param dbgi debug info
141 * @param block the basic block
142 * @param op the original node
143 * @param src_bits number of lower bits that will remain
145 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
148 int shift_width = 32 - src_bits;
149 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
150 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
155 * returns true if it is assured, that the upper bits of a node are "clean"
156 * which means for a 16 or 8 bit value, that the upper bits in the register
157 * are 0 for unsigned and a copy of the last significant bit for signed
160 static bool upper_bits_clean(ir_node *node, ir_mode *mode)
162 switch ((ir_opcode)get_irn_opcode(node)) {
164 if (!mode_is_signed(mode)) {
165 return upper_bits_clean(get_And_left(node), mode)
166 || upper_bits_clean(get_And_right(node), mode);
171 return upper_bits_clean(get_binop_left(node), mode)
172 && upper_bits_clean(get_binop_right(node), mode);
175 if (mode_is_signed(mode)) {
176 return false; /* TODO */
178 ir_node *right = get_Shr_right(node);
179 if (is_Const(right)) {
180 ir_tarval *tv = get_Const_tarval(right);
181 long val = get_tarval_long(tv);
182 if (val >= 32 - (long)get_mode_size_bits(mode))
185 return upper_bits_clean(get_Shr_left(node), mode);
189 return upper_bits_clean(get_Shrs_left(node), mode);
192 ir_tarval *tv = get_Const_tarval(node);
193 long val = get_tarval_long(tv);
194 if (mode_is_signed(mode)) {
195 long shifted = val >> (get_mode_size_bits(mode)-1);
196 return shifted == 0 || shifted == -1;
198 unsigned long shifted = (unsigned long)val;
199 shifted >>= get_mode_size_bits(mode)-1;
206 ir_mode *dest_mode = get_irn_mode(node);
207 ir_node *op = get_Conv_op(node);
208 ir_mode *src_mode = get_irn_mode(op);
209 unsigned src_bits = get_mode_size_bits(src_mode);
210 unsigned dest_bits = get_mode_size_bits(dest_mode);
211 /* downconvs are a nop */
212 if (src_bits <= dest_bits)
213 return upper_bits_clean(op, mode);
214 if (dest_bits <= get_mode_size_bits(mode)
215 && mode_is_signed(dest_mode) == mode_is_signed(mode))
221 ir_node *pred = get_Proj_pred(node);
222 switch (get_irn_opcode(pred)) {
224 ir_mode *load_mode = get_Load_mode(pred);
225 unsigned load_bits = get_mode_size_bits(load_mode);
226 unsigned bits = get_mode_size_bits(mode);
227 if (load_bits > bits)
229 if (mode_is_signed(mode) != mode_is_signed(load_mode))
244 * Extend a value to 32 bit signed/unsigned depending on its mode.
246 * @param dbgi debug info
247 * @param block the basic block
248 * @param op the original node
249 * @param orig_mode the original mode of op
251 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
254 int bits = get_mode_size_bits(orig_mode);
257 if (mode_is_signed(orig_mode)) {
258 return gen_sign_extension(dbgi, block, op, bits);
260 return gen_zero_extension(dbgi, block, op, bits);
266 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
267 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
268 influence the significant lower bit at
269 all (for cases where mode < 32bit) */
271 ENUM_BITSET(match_flags_t)
273 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
274 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
275 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
276 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
279 * checks if a node's value can be encoded as a immediate
281 static bool is_imm_encodeable(const ir_node *node)
287 value = get_tarval_long(get_Const_tarval(node));
288 return sparc_is_value_imm_encodeable(value);
291 static bool needs_extension(ir_node *op)
293 ir_mode *mode = get_irn_mode(op);
294 if (get_mode_size_bits(mode) >= get_mode_size_bits(mode_gp))
296 return !upper_bits_clean(op, mode);
300 * Check, if a given node is a Down-Conv, ie. a integer Conv
301 * from a mode with a mode with more bits to a mode with lesser bits.
302 * Moreover, we return only true if the node has not more than 1 user.
304 * @param node the node
305 * @return non-zero if node is a Down-Conv
307 static bool is_downconv(const ir_node *node)
315 src_mode = get_irn_mode(get_Conv_op(node));
316 dest_mode = get_irn_mode(node);
318 mode_needs_gp_reg(src_mode) &&
319 mode_needs_gp_reg(dest_mode) &&
320 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
323 static ir_node *skip_downconv(ir_node *node)
325 while (is_downconv(node)) {
326 node = get_Conv_op(node);
332 * helper function for binop operations
334 * @param new_reg register generation function ptr
335 * @param new_imm immediate generation function ptr
337 static ir_node *gen_helper_binop_args(ir_node *node,
338 ir_node *op1, ir_node *op2,
340 new_binop_reg_func new_reg,
341 new_binop_imm_func new_imm)
343 dbg_info *dbgi = get_irn_dbg_info(node);
344 ir_node *block = be_transform_node(get_nodes_block(node));
350 if (flags & MATCH_MODE_NEUTRAL) {
351 op1 = skip_downconv(op1);
352 op2 = skip_downconv(op2);
354 mode1 = get_irn_mode(op1);
355 mode2 = get_irn_mode(op2);
356 /* we shouldn't see 64bit code */
357 assert(get_mode_size_bits(mode1) <= 32);
358 assert(get_mode_size_bits(mode2) <= 32);
360 if (is_imm_encodeable(op2)) {
361 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
362 new_op1 = be_transform_node(op1);
363 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
364 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
366 return new_imm(dbgi, block, new_op1, NULL, immediate);
368 new_op2 = be_transform_node(op2);
369 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op2)) {
370 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
373 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
374 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
375 return new_imm(dbgi, block, new_op2, NULL, immediate);
378 new_op1 = be_transform_node(op1);
379 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
380 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
382 return new_reg(dbgi, block, new_op1, new_op2);
385 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
386 new_binop_reg_func new_reg,
387 new_binop_imm_func new_imm)
389 ir_node *op1 = get_binop_left(node);
390 ir_node *op2 = get_binop_right(node);
391 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
395 * helper function for FP binop operations
397 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
398 new_binop_fp_func new_func_single,
399 new_binop_fp_func new_func_double,
400 new_binop_fp_func new_func_quad)
402 ir_node *block = be_transform_node(get_nodes_block(node));
403 ir_node *op1 = get_binop_left(node);
404 ir_node *new_op1 = be_transform_node(op1);
405 ir_node *op2 = get_binop_right(node);
406 ir_node *new_op2 = be_transform_node(op2);
407 dbg_info *dbgi = get_irn_dbg_info(node);
408 unsigned bits = get_mode_size_bits(mode);
412 return new_func_single(dbgi, block, new_op1, new_op2, mode);
414 return new_func_double(dbgi, block, new_op1, new_op2, mode);
416 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
420 panic("unsupported mode %+F for float op", mode);
423 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
424 new_unop_fp_func new_func_single,
425 new_unop_fp_func new_func_double,
426 new_unop_fp_func new_func_quad)
428 ir_node *block = be_transform_node(get_nodes_block(node));
429 ir_node *op = get_unop_op(node);
430 ir_node *new_op = be_transform_node(op);
431 dbg_info *dbgi = get_irn_dbg_info(node);
432 unsigned bits = get_mode_size_bits(mode);
436 return new_func_single(dbgi, block, new_op, mode);
438 return new_func_double(dbgi, block, new_op, mode);
440 return new_func_quad(dbgi, block, new_op, mode);
444 panic("unsupported mode %+F for float op", mode);
447 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
448 ir_node *op1, ir_node *flags,
449 ir_entity *imm_entity, int32_t imm);
451 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
452 ir_node *op1, ir_node *op2,
455 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
456 new_binopx_reg_func new_binopx_reg,
457 new_binopx_imm_func new_binopx_imm)
459 dbg_info *dbgi = get_irn_dbg_info(node);
460 ir_node *block = be_transform_node(get_nodes_block(node));
461 ir_node *op1 = get_irn_n(node, 0);
462 ir_node *op2 = get_irn_n(node, 1);
463 ir_node *flags = get_irn_n(node, 2);
464 ir_node *new_flags = be_transform_node(flags);
468 /* only support for mode-neutral implemented so far */
469 assert(match_flags & MATCH_MODE_NEUTRAL);
471 if (is_imm_encodeable(op2)) {
472 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
473 new_op1 = be_transform_node(op1);
474 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
476 new_op2 = be_transform_node(op2);
477 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
478 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
479 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
481 new_op1 = be_transform_node(op1);
482 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
486 static ir_node *get_g0(ir_graph *irg)
488 if (start_g0 == NULL) {
489 /* this is already the transformed start node */
490 ir_node *start = get_irg_start(irg);
491 assert(is_sparc_Start(start));
492 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
497 static ir_node *get_g7(ir_graph *irg)
499 if (start_g7 == NULL) {
500 ir_node *start = get_irg_start(irg);
501 assert(is_sparc_Start(start));
502 start_g7 = new_r_Proj(start, mode_gp, start_g7_offset);
507 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
508 ir_entity *entity, int32_t offset)
510 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
511 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
515 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
518 if (get_entity_owner(entity) == get_tls_type()) {
519 ir_graph *irg = get_irn_irg(block);
520 ir_node *g7 = get_g7(irg);
521 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
522 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
525 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
526 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
531 typedef struct address_t {
539 * Match a load/store address
541 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
544 ir_node *ptr2 = NULL;
546 ir_entity *entity = NULL;
549 ir_node *add_right = get_Add_right(base);
550 if (is_Const(add_right)) {
551 base = get_Add_left(base);
552 offset += get_tarval_long(get_Const_tarval(add_right));
555 /* Note that we don't match sub(x, Const) or chains of adds/subs
556 * because this should all be normalized by now */
558 /* we only use the symconst if we're the only user otherwise we probably
559 * won't save anything but produce multiple sethi+or combinations with
560 * just different offsets */
561 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
562 ir_entity *sc_entity = get_SymConst_entity(base);
563 dbg_info *dbgi = get_irn_dbg_info(ptr);
564 ir_node *block = get_nodes_block(ptr);
565 ir_node *new_block = be_transform_node(block);
567 if (get_entity_owner(sc_entity) == get_tls_type()) {
571 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
573 base = get_g7(get_irn_irg(base));
577 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
579 } else if (use_ptr2 && is_Add(base) && offset == 0) {
580 ptr2 = be_transform_node(get_Add_right(base));
581 base = be_transform_node(get_Add_left(base));
584 if (sparc_is_value_imm_encodeable(offset)) {
585 base = be_transform_node(base);
587 base = be_transform_node(ptr);
593 address->ptr2 = ptr2;
594 address->entity = entity;
595 address->offset = offset;
599 * Creates an sparc Add.
601 * @param node FIRM node
602 * @return the created sparc Add node
604 static ir_node *gen_Add(ir_node *node)
606 ir_mode *mode = get_irn_mode(node);
609 if (mode_is_float(mode)) {
610 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
611 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
614 /* special case: + 0x1000 can be represented as - 0x1000 */
615 right = get_Add_right(node);
616 if (is_Const(right)) {
617 ir_node *left = get_Add_left(node);
620 /* is this simple address arithmetic? then we can let the linker do
621 * the calculation. */
622 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
623 dbg_info *dbgi = get_irn_dbg_info(node);
624 ir_node *block = be_transform_node(get_nodes_block(node));
627 /* the value of use_ptr2 shouldn't matter here */
628 match_address(node, &address, false);
629 assert(is_sparc_SetHi(address.ptr));
630 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
631 address.entity, address.offset);
634 tv = get_Const_tarval(right);
635 val = get_tarval_long(tv);
637 dbg_info *dbgi = get_irn_dbg_info(node);
638 ir_node *block = be_transform_node(get_nodes_block(node));
639 ir_node *op = get_Add_left(node);
640 ir_node *new_op = be_transform_node(op);
641 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
645 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
646 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
649 static ir_node *gen_AddCC_t(ir_node *node)
651 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
652 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
655 static ir_node *gen_Proj_AddCC_t(ir_node *node)
657 long pn = get_Proj_proj(node);
658 ir_node *pred = get_Proj_pred(node);
659 ir_node *new_pred = be_transform_node(pred);
662 case pn_sparc_AddCC_t_res:
663 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
664 case pn_sparc_AddCC_t_flags:
665 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
667 panic("Invalid AddCC_t proj found");
671 static ir_node *gen_AddX_t(ir_node *node)
673 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
674 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
678 * Creates an sparc Sub.
680 * @param node FIRM node
681 * @return the created sparc Sub node
683 static ir_node *gen_Sub(ir_node *node)
685 ir_mode *mode = get_irn_mode(node);
687 if (mode_is_float(mode)) {
688 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
689 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
692 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
693 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
696 static ir_node *gen_SubCC_t(ir_node *node)
698 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
699 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
702 static ir_node *gen_Proj_SubCC_t(ir_node *node)
704 long pn = get_Proj_proj(node);
705 ir_node *pred = get_Proj_pred(node);
706 ir_node *new_pred = be_transform_node(pred);
709 case pn_sparc_SubCC_t_res:
710 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
711 case pn_sparc_SubCC_t_flags:
712 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
714 panic("Invalid SubCC_t proj found");
718 static ir_node *gen_SubX_t(ir_node *node)
720 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
721 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
724 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
725 ir_node *mem, ir_mode *mode, ir_entity *entity,
726 long offset, bool is_frame_entity)
728 unsigned bits = get_mode_size_bits(mode);
729 assert(mode_is_float(mode));
731 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
732 offset, is_frame_entity);
733 } else if (bits == 64) {
734 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
735 offset, is_frame_entity);
738 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
739 offset, is_frame_entity);
743 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
744 ir_node *ptr, ir_node *mem, ir_mode *mode,
745 ir_entity *entity, long offset,
746 bool is_frame_entity)
748 unsigned bits = get_mode_size_bits(mode);
749 assert(mode_is_float(mode));
751 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
752 offset, is_frame_entity);
753 } else if (bits == 64) {
754 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
755 offset, is_frame_entity);
758 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
759 offset, is_frame_entity);
766 * @param node the ir Load node
767 * @return the created sparc Load node
769 static ir_node *gen_Load(ir_node *node)
771 dbg_info *dbgi = get_irn_dbg_info(node);
772 ir_mode *mode = get_Load_mode(node);
773 ir_node *block = be_transform_node(get_nodes_block(node));
774 ir_node *ptr = get_Load_ptr(node);
775 ir_node *mem = get_Load_mem(node);
776 ir_node *new_mem = be_transform_node(mem);
777 ir_node *new_load = NULL;
780 if (get_Load_unaligned(node) == align_non_aligned) {
781 panic("sparc: transformation of unaligned Loads not implemented yet");
784 if (mode_is_float(mode)) {
785 match_address(ptr, &address, false);
786 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
787 address.entity, address.offset, false);
789 match_address(ptr, &address, true);
790 if (address.ptr2 != NULL) {
791 assert(address.entity == NULL && address.offset == 0);
792 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
793 address.ptr2, new_mem, mode);
795 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
796 mode, address.entity, address.offset,
800 set_irn_pinned(new_load, get_irn_pinned(node));
806 * Transforms a Store.
808 * @param node the ir Store node
809 * @return the created sparc Store node
811 static ir_node *gen_Store(ir_node *node)
813 ir_node *block = be_transform_node(get_nodes_block(node));
814 ir_node *ptr = get_Store_ptr(node);
815 ir_node *mem = get_Store_mem(node);
816 ir_node *new_mem = be_transform_node(mem);
817 ir_node *val = get_Store_value(node);
818 ir_mode *mode = get_irn_mode(val);
819 dbg_info *dbgi = get_irn_dbg_info(node);
820 ir_node *new_store = NULL;
823 if (get_Store_unaligned(node) == align_non_aligned) {
824 panic("sparc: transformation of unaligned Stores not implemented yet");
827 if (mode_is_float(mode)) {
828 ir_node *new_val = be_transform_node(val);
829 /* TODO: variants with reg+reg address mode */
830 match_address(ptr, &address, false);
831 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
832 mode, address.entity, address.offset, false);
835 unsigned dest_bits = get_mode_size_bits(mode);
836 while (is_downconv(node)
837 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
838 val = get_Conv_op(val);
840 new_val = be_transform_node(val);
842 assert(dest_bits <= 32);
843 match_address(ptr, &address, true);
844 if (address.ptr2 != NULL) {
845 assert(address.entity == NULL && address.offset == 0);
846 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
847 address.ptr2, new_mem, mode);
849 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
850 new_mem, mode, address.entity,
851 address.offset, false);
854 set_irn_pinned(new_store, get_irn_pinned(node));
860 * Creates an sparc Mul.
861 * returns the lower 32bits of the 64bit multiply result
863 * @return the created sparc Mul node
865 static ir_node *gen_Mul(ir_node *node)
867 ir_mode *mode = get_irn_mode(node);
868 if (mode_is_float(mode)) {
869 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
870 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
873 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
874 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
878 * Creates an sparc Mulh.
879 * Mulh returns the upper 32bits of a mul instruction
881 * @return the created sparc Mulh node
883 static ir_node *gen_Mulh(ir_node *node)
885 ir_mode *mode = get_irn_mode(node);
888 if (mode_is_float(mode))
889 panic("FP not supported yet");
891 if (mode_is_signed(mode)) {
892 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
893 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
895 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
896 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
900 static ir_node *gen_sign_extension_value(ir_node *node)
902 ir_node *block = get_nodes_block(node);
903 ir_node *new_block = be_transform_node(block);
904 ir_node *new_node = be_transform_node(node);
905 /* TODO: we could do some shortcuts for some value types probably.
906 * (For constants or other cases where we know the sign bit in
908 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
912 * Creates an sparc Div.
914 * @return the created sparc Div node
916 static ir_node *gen_Div(ir_node *node)
918 dbg_info *dbgi = get_irn_dbg_info(node);
919 ir_node *block = get_nodes_block(node);
920 ir_node *new_block = be_transform_node(block);
921 ir_mode *mode = get_Div_resmode(node);
922 ir_node *left = get_Div_left(node);
923 ir_node *left_low = be_transform_node(left);
924 ir_node *right = get_Div_right(node);
927 if (mode_is_float(mode)) {
928 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
929 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
932 if (mode_is_signed(mode)) {
933 ir_node *left_high = gen_sign_extension_value(left);
935 if (is_imm_encodeable(right)) {
936 int32_t immediate = get_tarval_long(get_Const_tarval(right));
937 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
940 ir_node *new_right = be_transform_node(right);
941 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
945 ir_graph *irg = get_irn_irg(node);
946 ir_node *left_high = get_g0(irg);
947 if (is_imm_encodeable(right)) {
948 int32_t immediate = get_tarval_long(get_Const_tarval(right));
949 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
952 ir_node *new_right = be_transform_node(right);
953 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
962 * Transforms a Not node.
964 * @return the created sparc Not node
966 static ir_node *gen_Not(ir_node *node)
968 ir_node *op = get_Not_op(node);
969 ir_graph *irg = get_irn_irg(node);
970 ir_node *zero = get_g0(irg);
971 dbg_info *dbgi = get_irn_dbg_info(node);
972 ir_node *block = be_transform_node(get_nodes_block(node));
973 ir_node *new_op = be_transform_node(op);
975 /* Note: Not(Eor()) is normalize in firm localopts already so
976 * we don't match it for xnor here */
978 /* Not can be represented with xnor 0, n */
979 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
982 static ir_node *gen_helper_bitop(ir_node *node,
983 new_binop_reg_func new_reg,
984 new_binop_imm_func new_imm,
985 new_binop_reg_func new_not_reg,
986 new_binop_imm_func new_not_imm,
989 ir_node *op1 = get_binop_left(node);
990 ir_node *op2 = get_binop_right(node);
992 return gen_helper_binop_args(node, op2, get_Not_op(op1),
994 new_not_reg, new_not_imm);
997 return gen_helper_binop_args(node, op1, get_Not_op(op2),
999 new_not_reg, new_not_imm);
1001 return gen_helper_binop_args(node, op1, op2,
1002 flags | MATCH_COMMUTATIVE,
1006 static ir_node *gen_And(ir_node *node)
1008 return gen_helper_bitop(node,
1009 new_bd_sparc_And_reg,
1010 new_bd_sparc_And_imm,
1011 new_bd_sparc_AndN_reg,
1012 new_bd_sparc_AndN_imm,
1013 MATCH_MODE_NEUTRAL);
1016 static ir_node *gen_Or(ir_node *node)
1018 return gen_helper_bitop(node,
1019 new_bd_sparc_Or_reg,
1020 new_bd_sparc_Or_imm,
1021 new_bd_sparc_OrN_reg,
1022 new_bd_sparc_OrN_imm,
1023 MATCH_MODE_NEUTRAL);
1026 static ir_node *gen_Eor(ir_node *node)
1028 return gen_helper_bitop(node,
1029 new_bd_sparc_Xor_reg,
1030 new_bd_sparc_Xor_imm,
1031 new_bd_sparc_XNor_reg,
1032 new_bd_sparc_XNor_imm,
1033 MATCH_MODE_NEUTRAL);
1036 static ir_node *gen_Shl(ir_node *node)
1038 ir_mode *mode = get_irn_mode(node);
1039 if (get_mode_modulo_shift(mode) != 32)
1040 panic("modulo_shift!=32 not supported by sparc backend");
1041 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
1044 static ir_node *gen_Shr(ir_node *node)
1046 ir_mode *mode = get_irn_mode(node);
1047 if (get_mode_modulo_shift(mode) != 32)
1048 panic("modulo_shift!=32 not supported by sparc backend");
1049 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
1052 static ir_node *gen_Shrs(ir_node *node)
1054 ir_mode *mode = get_irn_mode(node);
1055 if (get_mode_modulo_shift(mode) != 32)
1056 panic("modulo_shift!=32 not supported by sparc backend");
1057 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
1061 * Transforms a Minus node.
1063 static ir_node *gen_Minus(ir_node *node)
1065 ir_mode *mode = get_irn_mode(node);
1072 if (mode_is_float(mode)) {
1073 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
1074 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
1076 block = be_transform_node(get_nodes_block(node));
1077 dbgi = get_irn_dbg_info(node);
1078 op = get_Minus_op(node);
1079 new_op = be_transform_node(op);
1080 zero = get_g0(get_irn_irg(node));
1081 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1085 * Create an entity for a given (floating point) tarval
1087 static ir_entity *create_float_const_entity(ir_tarval *tv)
1089 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
1090 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1091 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
1092 ir_initializer_t *initializer;
1100 mode = get_tarval_mode(tv);
1101 type = get_type_for_mode(mode);
1102 glob = get_glob_type();
1103 entity = new_entity(glob, id_unique("C%u"), type);
1104 set_entity_visibility(entity, ir_visibility_private);
1105 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1107 initializer = create_initializer_tarval(tv);
1108 set_entity_initializer(entity, initializer);
1110 pmap_insert(isa->constants, tv, entity);
1114 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1116 ir_entity *entity = create_float_const_entity(tv);
1117 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1118 ir_node *mem = get_irg_no_mem(current_ir_graph);
1119 ir_mode *mode = get_tarval_mode(tv);
1121 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1122 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1124 set_irn_pinned(new_op, op_pin_state_floats);
1128 static ir_node *gen_Const(ir_node *node)
1130 ir_node *block = be_transform_node(get_nodes_block(node));
1131 ir_mode *mode = get_irn_mode(node);
1132 dbg_info *dbgi = get_irn_dbg_info(node);
1133 ir_tarval *tv = get_Const_tarval(node);
1136 if (mode_is_float(mode)) {
1137 return gen_float_const(dbgi, block, tv);
1140 value = get_tarval_long(tv);
1142 return get_g0(get_irn_irg(node));
1143 } else if (sparc_is_value_imm_encodeable(value)) {
1144 ir_graph *irg = get_irn_irg(node);
1145 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1147 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1148 if ((value & 0x3ff) != 0) {
1149 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1156 static ir_node *gen_SwitchJmp(ir_node *node)
1158 dbg_info *dbgi = get_irn_dbg_info(node);
1159 ir_node *block = be_transform_node(get_nodes_block(node));
1160 ir_node *selector = get_Cond_selector(node);
1161 ir_node *new_selector = be_transform_node(selector);
1162 long default_pn = get_Cond_default_proj(node);
1164 ir_node *table_address;
1169 /* switch with smaller mode not implemented yet */
1170 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1172 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1173 set_entity_visibility(entity, ir_visibility_private);
1174 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1176 /* construct base address */
1177 table_address = make_address(dbgi, block, entity, 0);
1179 idx = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
1180 /* load from jumptable */
1181 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, idx,
1182 get_irg_no_mem(current_ir_graph),
1184 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1186 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
1189 static ir_node *gen_Cond(ir_node *node)
1191 ir_node *selector = get_Cond_selector(node);
1192 ir_mode *mode = get_irn_mode(selector);
1197 ir_relation relation;
1200 /* switch/case jumps */
1201 if (mode != mode_b) {
1202 return gen_SwitchJmp(node);
1205 /* note: after lower_mode_b we are guaranteed to have a Cmp input */
1206 block = be_transform_node(get_nodes_block(node));
1207 dbgi = get_irn_dbg_info(node);
1208 cmp_left = get_Cmp_left(selector);
1209 cmp_mode = get_irn_mode(cmp_left);
1210 flag_node = be_transform_node(selector);
1211 relation = get_Cmp_relation(selector);
1212 if (mode_is_float(cmp_mode)) {
1213 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1215 bool is_unsigned = !mode_is_signed(cmp_mode);
1216 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1223 static ir_node *gen_Cmp(ir_node *node)
1225 ir_node *op1 = get_Cmp_left(node);
1226 ir_node *op2 = get_Cmp_right(node);
1227 ir_mode *cmp_mode = get_irn_mode(op1);
1228 assert(get_irn_mode(op2) == cmp_mode);
1230 if (mode_is_float(cmp_mode)) {
1231 ir_node *block = be_transform_node(get_nodes_block(node));
1232 dbg_info *dbgi = get_irn_dbg_info(node);
1233 ir_node *new_op1 = be_transform_node(op1);
1234 ir_node *new_op2 = be_transform_node(op2);
1235 unsigned bits = get_mode_size_bits(cmp_mode);
1237 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1238 } else if (bits == 64) {
1239 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1241 assert(bits == 128);
1242 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1246 /* when we compare a bitop like and,or,... with 0 then we can directly use
1247 * the bitopcc variant.
1248 * Currently we only do this when we're the only user of the node...
1250 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1252 return gen_helper_bitop(op1,
1253 new_bd_sparc_AndCCZero_reg,
1254 new_bd_sparc_AndCCZero_imm,
1255 new_bd_sparc_AndNCCZero_reg,
1256 new_bd_sparc_AndNCCZero_imm,
1258 } else if (is_Or(op1)) {
1259 return gen_helper_bitop(op1,
1260 new_bd_sparc_OrCCZero_reg,
1261 new_bd_sparc_OrCCZero_imm,
1262 new_bd_sparc_OrNCCZero_reg,
1263 new_bd_sparc_OrNCCZero_imm,
1265 } else if (is_Eor(op1)) {
1266 return gen_helper_bitop(op1,
1267 new_bd_sparc_XorCCZero_reg,
1268 new_bd_sparc_XorCCZero_imm,
1269 new_bd_sparc_XNorCCZero_reg,
1270 new_bd_sparc_XNorCCZero_imm,
1275 /* integer compare */
1276 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1277 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1281 * Transforms a SymConst node.
1283 static ir_node *gen_SymConst(ir_node *node)
1285 ir_entity *entity = get_SymConst_entity(node);
1286 dbg_info *dbgi = get_irn_dbg_info(node);
1287 ir_node *block = get_nodes_block(node);
1288 ir_node *new_block = be_transform_node(block);
1289 return make_address(dbgi, new_block, entity, 0);
1292 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1293 ir_mode *src_mode, ir_mode *dst_mode)
1295 unsigned src_bits = get_mode_size_bits(src_mode);
1296 unsigned dst_bits = get_mode_size_bits(dst_mode);
1297 if (src_bits == 32) {
1298 if (dst_bits == 64) {
1299 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1301 assert(dst_bits == 128);
1302 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1304 } else if (src_bits == 64) {
1305 if (dst_bits == 32) {
1306 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1308 assert(dst_bits == 128);
1309 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1312 assert(src_bits == 128);
1313 if (dst_bits == 32) {
1314 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1316 assert(dst_bits == 64);
1317 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1322 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1326 unsigned bits = get_mode_size_bits(src_mode);
1328 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1329 } else if (bits == 64) {
1330 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1332 assert(bits == 128);
1333 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1337 ir_graph *irg = get_irn_irg(block);
1338 ir_node *sp = get_irg_frame(irg);
1339 ir_node *nomem = get_irg_no_mem(irg);
1340 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1342 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1344 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1345 set_irn_pinned(stf, op_pin_state_floats);
1346 set_irn_pinned(ld, op_pin_state_floats);
1351 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1354 ir_graph *irg = get_irn_irg(block);
1355 ir_node *sp = get_irg_frame(irg);
1356 ir_node *nomem = get_irg_no_mem(irg);
1357 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1358 mode_gp, NULL, 0, true);
1359 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1361 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1362 unsigned bits = get_mode_size_bits(dst_mode);
1363 set_irn_pinned(st, op_pin_state_floats);
1364 set_irn_pinned(ldf, op_pin_state_floats);
1367 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1368 } else if (bits == 64) {
1369 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1371 assert(bits == 128);
1372 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1376 static ir_node *gen_Conv(ir_node *node)
1378 ir_node *block = be_transform_node(get_nodes_block(node));
1379 ir_node *op = get_Conv_op(node);
1380 ir_mode *src_mode = get_irn_mode(op);
1381 ir_mode *dst_mode = get_irn_mode(node);
1382 dbg_info *dbgi = get_irn_dbg_info(node);
1385 int src_bits = get_mode_size_bits(src_mode);
1386 int dst_bits = get_mode_size_bits(dst_mode);
1388 if (src_mode == mode_b)
1389 panic("ConvB not lowered %+F", node);
1391 if (src_mode == dst_mode)
1392 return be_transform_node(op);
1394 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1395 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1397 new_op = be_transform_node(op);
1398 if (mode_is_float(src_mode)) {
1399 if (mode_is_float(dst_mode)) {
1400 /* float -> float conv */
1401 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1403 /* float -> int conv */
1404 if (!mode_is_signed(dst_mode))
1405 panic("float to unsigned not implemented yet");
1406 return create_ftoi(dbgi, block, new_op, src_mode);
1409 /* int -> float conv */
1410 if (src_bits < 32) {
1411 new_op = gen_extension(dbgi, block, new_op, src_mode);
1412 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1413 panic("unsigned to float not lowered!");
1415 return create_itof(dbgi, block, new_op, dst_mode);
1417 } else { /* complete in gp registers */
1421 if (src_bits == dst_bits || dst_mode == mode_b) {
1422 /* kill unnecessary conv */
1423 return be_transform_node(op);
1426 if (src_bits < dst_bits) {
1427 min_bits = src_bits;
1428 min_mode = src_mode;
1430 min_bits = dst_bits;
1431 min_mode = dst_mode;
1434 if (upper_bits_clean(op, min_mode)) {
1435 return be_transform_node(op);
1437 new_op = be_transform_node(op);
1439 if (mode_is_signed(min_mode)) {
1440 return gen_sign_extension(dbgi, block, new_op, min_bits);
1442 return gen_zero_extension(dbgi, block, new_op, min_bits);
1447 static ir_node *gen_Unknown(ir_node *node)
1449 /* just produce a 0 */
1450 ir_mode *mode = get_irn_mode(node);
1451 if (mode_is_float(mode)) {
1452 ir_node *block = be_transform_node(get_nodes_block(node));
1453 return gen_float_const(NULL, block, get_mode_null(mode));
1454 } else if (mode_needs_gp_reg(mode)) {
1455 ir_graph *irg = get_irn_irg(node);
1459 panic("Unexpected Unknown mode");
1463 * transform the start node to the prolog code
1465 static ir_node *gen_Start(ir_node *node)
1467 ir_graph *irg = get_irn_irg(node);
1468 ir_entity *entity = get_irg_entity(irg);
1469 ir_type *function_type = get_entity_type(entity);
1470 ir_node *block = get_nodes_block(node);
1471 ir_node *new_block = be_transform_node(block);
1472 dbg_info *dbgi = get_irn_dbg_info(node);
1473 struct obstack *obst = be_get_be_obst(irg);
1474 const arch_register_req_t *req;
1480 /* start building list of start constraints */
1481 assert(obstack_object_size(obst) == 0);
1483 /* calculate number of outputs */
1484 n_outs = 4; /* memory, g0, g7, sp */
1485 if (!current_cconv->omit_fp)
1486 ++n_outs; /* framepointer */
1487 /* function parameters */
1488 n_outs += current_cconv->n_param_regs;
1490 if (current_cconv->omit_fp) {
1491 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1494 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1498 /* first output is memory */
1499 start_mem_offset = o;
1500 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1503 /* the zero register */
1504 start_g0_offset = o;
1505 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1506 arch_register_req_type_ignore);
1507 arch_set_irn_register_req_out(start, o, req);
1508 arch_set_irn_register_out(start, o, &sparc_registers[REG_G0]);
1511 /* g7 is used for TLS data */
1512 start_g7_offset = o;
1513 req = be_create_reg_req(obst, &sparc_registers[REG_G7],
1514 arch_register_req_type_ignore);
1515 arch_set_irn_register_req_out(start, o, req);
1516 arch_set_irn_register_out(start, o, &sparc_registers[REG_G7]);
1519 /* we need an output for the stackpointer */
1520 start_sp_offset = o;
1521 req = be_create_reg_req(obst, sp_reg,
1522 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1523 arch_set_irn_register_req_out(start, o, req);
1524 arch_set_irn_register_out(start, o, sp_reg);
1527 if (!current_cconv->omit_fp) {
1528 start_fp_offset = o;
1529 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1530 arch_set_irn_register_req_out(start, o, req);
1531 arch_set_irn_register_out(start, o, fp_reg);
1535 /* function parameters in registers */
1536 start_params_offset = o;
1537 for (i = 0; i < get_method_n_params(function_type); ++i) {
1538 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1539 const arch_register_t *reg0 = param->reg0;
1540 const arch_register_t *reg1 = param->reg1;
1542 arch_set_irn_register_req_out(start, o, reg0->single_req);
1543 arch_set_irn_register_out(start, o, reg0);
1547 arch_set_irn_register_req_out(start, o, reg1->single_req);
1548 arch_set_irn_register_out(start, o, reg1);
1552 /* we need the values of the callee saves (Note: non omit-fp mode has no
1554 start_callee_saves_offset = o;
1555 if (current_cconv->omit_fp) {
1556 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1558 for (c = 0; c < n_callee_saves; ++c) {
1559 const arch_register_t *reg = omit_fp_callee_saves[c];
1560 arch_set_irn_register_req_out(start, o, reg->single_req);
1561 arch_set_irn_register_out(start, o, reg);
1565 assert(n_outs == o);
1570 static ir_node *get_initial_sp(ir_graph *irg)
1572 if (start_sp == NULL) {
1573 ir_node *start = get_irg_start(irg);
1574 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1579 static ir_node *get_initial_fp(ir_graph *irg)
1581 if (start_fp == NULL) {
1582 ir_node *start = get_irg_start(irg);
1583 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1588 static ir_node *get_initial_mem(ir_graph *irg)
1590 if (start_mem == NULL) {
1591 ir_node *start = get_irg_start(irg);
1592 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1597 static ir_node *get_stack_pointer_for(ir_node *node)
1599 /* get predecessor in stack_order list */
1600 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1603 if (stack_pred == NULL) {
1604 /* first stack user in the current block. We can simply use the
1605 * initial sp_proj for it */
1606 ir_graph *irg = get_irn_irg(node);
1607 return get_initial_sp(irg);
1610 be_transform_node(stack_pred);
1611 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1612 if (stack == NULL) {
1613 return get_stack_pointer_for(stack_pred);
1620 * transform a Return node into epilogue code + return statement
1622 static ir_node *gen_Return(ir_node *node)
1624 ir_node *block = get_nodes_block(node);
1625 ir_graph *irg = get_irn_irg(node);
1626 ir_node *new_block = be_transform_node(block);
1627 dbg_info *dbgi = get_irn_dbg_info(node);
1628 ir_node *mem = get_Return_mem(node);
1629 ir_node *new_mem = be_transform_node(mem);
1630 ir_node *sp = get_stack_pointer_for(node);
1631 size_t n_res = get_Return_n_ress(node);
1632 struct obstack *be_obst = be_get_be_obst(irg);
1635 const arch_register_req_t **reqs;
1640 /* estimate number of return values */
1641 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1642 if (current_cconv->omit_fp)
1643 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1645 in = ALLOCAN(ir_node*, n_ins);
1646 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1650 reqs[p] = arch_no_register_req;
1654 reqs[p] = sp_reg->single_req;
1658 for (i = 0; i < n_res; ++i) {
1659 ir_node *res_value = get_Return_res(node, i);
1660 ir_node *new_res_value = be_transform_node(res_value);
1661 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1662 assert(slot->req1 == NULL);
1663 in[p] = new_res_value;
1664 reqs[p] = slot->req0;
1668 if (current_cconv->omit_fp) {
1669 ir_node *start = get_irg_start(irg);
1670 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1671 for (i = 0; i < n_callee_saves; ++i) {
1672 const arch_register_t *reg = omit_fp_callee_saves[i];
1673 ir_mode *mode = reg->reg_class->mode;
1675 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1677 reqs[p] = reg->single_req;
1683 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1684 arch_set_irn_register_reqs_in(bereturn, reqs);
1689 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1690 ir_node *value0, ir_node *value1)
1692 ir_graph *irg = current_ir_graph;
1693 ir_node *sp = get_irg_frame(irg);
1694 ir_node *nomem = get_irg_no_mem(irg);
1695 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1696 mode_gp, NULL, 0, true);
1700 set_irn_pinned(st, op_pin_state_floats);
1702 if (value1 != NULL) {
1703 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1704 mode_gp, NULL, 4, true);
1705 ir_node *in[2] = { st, st1 };
1706 ir_node *sync = new_r_Sync(block, 2, in);
1707 set_irn_pinned(st1, op_pin_state_floats);
1715 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1716 set_irn_pinned(ldf, op_pin_state_floats);
1718 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1721 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1722 ir_node *node, ir_mode *float_mode,
1725 ir_graph *irg = current_ir_graph;
1726 ir_node *stack = get_irg_frame(irg);
1727 ir_node *nomem = get_irg_no_mem(irg);
1728 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1730 int bits = get_mode_size_bits(float_mode);
1732 set_irn_pinned(stf, op_pin_state_floats);
1734 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1735 set_irn_pinned(ld, op_pin_state_floats);
1736 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1739 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1741 set_irn_pinned(ld, op_pin_state_floats);
1742 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1744 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1745 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1752 static ir_node *gen_Call(ir_node *node)
1754 ir_graph *irg = get_irn_irg(node);
1755 ir_node *callee = get_Call_ptr(node);
1756 ir_node *block = get_nodes_block(node);
1757 ir_node *new_block = be_transform_node(block);
1758 ir_node *mem = get_Call_mem(node);
1759 ir_node *new_mem = be_transform_node(mem);
1760 dbg_info *dbgi = get_irn_dbg_info(node);
1761 ir_type *type = get_Call_type(node);
1762 size_t n_params = get_Call_n_params(node);
1763 size_t n_ress = get_method_n_ress(type);
1764 /* max inputs: memory, callee, register arguments */
1765 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1766 struct obstack *obst = be_get_be_obst(irg);
1767 calling_convention_t *cconv
1768 = sparc_decide_calling_convention(type, NULL);
1769 size_t n_param_regs = cconv->n_param_regs;
1770 /* param-regs + mem + stackpointer + callee */
1771 unsigned max_inputs = 3 + n_param_regs;
1772 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1773 const arch_register_req_t **in_req
1774 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1778 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1779 ir_entity *entity = NULL;
1780 ir_node *new_frame = get_stack_pointer_for(node);
1781 bool aggregate_return
1782 = get_method_calling_convention(type) & cc_compound_ret;
1792 assert(n_params == get_method_n_params(type));
1794 /* construct arguments */
1797 in_req[in_arity] = arch_no_register_req;
1801 /* stack pointer input */
1802 /* construct an IncSP -> we have to always be sure that the stack is
1803 * aligned even if we don't push arguments on it */
1804 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1805 cconv->param_stack_size, 1);
1806 in_req[in_arity] = sp_reg->single_req;
1807 in[in_arity] = incsp;
1811 for (p = 0; p < n_params; ++p) {
1812 ir_node *value = get_Call_param(node, p);
1813 ir_node *new_value = be_transform_node(value);
1814 const reg_or_stackslot_t *param = &cconv->parameters[p];
1815 ir_type *param_type = get_method_param_type(type, p);
1816 ir_mode *mode = get_type_mode(param_type);
1817 ir_node *new_values[2];
1821 if (mode_is_float(mode) && param->reg0 != NULL) {
1822 unsigned size_bits = get_mode_size_bits(mode);
1823 assert(size_bits <= 64);
1824 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1826 new_values[0] = new_value;
1827 new_values[1] = NULL;
1830 /* put value into registers */
1831 if (param->reg0 != NULL) {
1832 in[in_arity] = new_values[0];
1833 in_req[in_arity] = param->reg0->single_req;
1835 if (new_values[1] == NULL)
1838 if (param->reg1 != NULL) {
1839 assert(new_values[1] != NULL);
1840 in[in_arity] = new_values[1];
1841 in_req[in_arity] = param->reg1->single_req;
1846 /* we need a store if we're here */
1847 if (new_values[1] != NULL) {
1848 new_value = new_values[1];
1852 /* we need to skip over our save area when constructing the call
1853 * arguments on stack */
1854 offset = param->offset + SPARC_MIN_STACKSIZE;
1856 if (mode_is_float(mode)) {
1857 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1858 mode, NULL, offset, true);
1860 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1861 new_mem, mode, NULL, offset, true);
1863 set_irn_pinned(str, op_pin_state_floats);
1864 sync_ins[sync_arity++] = str;
1867 /* construct memory input */
1868 if (sync_arity == 0) {
1869 in[mem_pos] = new_mem;
1870 } else if (sync_arity == 1) {
1871 in[mem_pos] = sync_ins[0];
1873 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1876 if (is_SymConst(callee)) {
1877 entity = get_SymConst_entity(callee);
1879 in[in_arity] = be_transform_node(callee);
1880 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1883 assert(in_arity <= (int)max_inputs);
1890 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1892 /* create call node */
1893 if (entity != NULL) {
1894 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1895 entity, 0, aggregate_return);
1897 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1900 arch_set_irn_register_reqs_in(res, in_req);
1902 /* create output register reqs */
1904 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1905 /* add register requirements for the result regs */
1906 for (r = 0; r < n_ress; ++r) {
1907 const reg_or_stackslot_t *result_info = &cconv->results[r];
1908 const arch_register_req_t *req = result_info->req0;
1910 arch_set_irn_register_req_out(res, o++, req);
1912 assert(result_info->req1 == NULL);
1914 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1915 const arch_register_t *reg;
1916 if (!rbitset_is_set(cconv->caller_saves, i))
1918 reg = &sparc_registers[i];
1919 arch_set_irn_register_req_out(res, o++, reg->single_req);
1921 assert(o == out_arity);
1923 /* copy pinned attribute */
1924 set_irn_pinned(res, get_irn_pinned(node));
1926 /* IncSP to destroy the call stackframe */
1927 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1928 /* if we are the last IncSP producer in a block then we have to keep
1930 * Note: This here keeps all producers which is more than necessary */
1931 add_irn_dep(incsp, res);
1934 pmap_insert(node_to_stack, node, incsp);
1936 sparc_free_calling_convention(cconv);
1940 static ir_node *gen_Sel(ir_node *node)
1942 dbg_info *dbgi = get_irn_dbg_info(node);
1943 ir_node *block = get_nodes_block(node);
1944 ir_node *new_block = be_transform_node(block);
1945 ir_node *ptr = get_Sel_ptr(node);
1946 ir_node *new_ptr = be_transform_node(ptr);
1947 ir_entity *entity = get_Sel_entity(node);
1949 /* must be the frame pointer all other sels must have been lowered
1951 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1953 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1956 static ir_node *gen_Alloc(ir_node *node)
1958 dbg_info *dbgi = get_irn_dbg_info(node);
1959 ir_node *block = get_nodes_block(node);
1960 ir_node *new_block = be_transform_node(block);
1961 ir_type *type = get_Alloc_type(node);
1962 ir_node *size = get_Alloc_count(node);
1963 ir_node *stack_pred = get_stack_pointer_for(node);
1965 if (get_Alloc_where(node) != stack_alloc)
1966 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1967 /* lowerer should have transformed all allocas to byte size */
1968 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1969 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1971 if (is_Const(size)) {
1972 ir_tarval *tv = get_Const_tarval(size);
1973 long sizel = get_tarval_long(tv);
1974 subsp = be_new_IncSP(sp_reg, new_block, stack_pred, sizel, 0);
1975 set_irn_dbg_info(subsp, dbgi);
1977 ir_node *new_size = be_transform_node(size);
1978 subsp = new_bd_sparc_SubSP(dbgi, new_block, stack_pred, new_size);
1979 arch_set_irn_register(subsp, sp_reg);
1982 /* if we are the last IncSP producer in a block then we have to keep
1984 * Note: This here keeps all producers which is more than necessary */
1987 pmap_insert(node_to_stack, node, subsp);
1988 /* the "result" is the unmodified sp value */
1992 static ir_node *gen_Proj_Alloc(ir_node *node)
1994 ir_node *alloc = get_Proj_pred(node);
1995 long pn = get_Proj_proj(node);
1997 switch ((pn_Alloc)pn) {
1999 ir_node *alloc_mem = get_Alloc_mem(alloc);
2000 return be_transform_node(alloc_mem);
2002 case pn_Alloc_res: {
2003 ir_node *new_alloc = be_transform_node(alloc);
2006 case pn_Alloc_X_regular:
2007 case pn_Alloc_X_except:
2008 panic("sparc backend: exception output of alloc not supported (at %+F)",
2011 panic("sparc backend: invalid Proj->Alloc");
2014 static ir_node *gen_Free(ir_node *node)
2016 dbg_info *dbgi = get_irn_dbg_info(node);
2017 ir_node *block = get_nodes_block(node);
2018 ir_node *new_block = be_transform_node(block);
2019 ir_type *type = get_Free_type(node);
2020 ir_node *size = get_Free_count(node);
2021 ir_node *mem = get_Free_mem(node);
2022 ir_node *new_mem = be_transform_node(mem);
2023 ir_node *stack_pred = get_stack_pointer_for(node);
2025 if (get_Alloc_where(node) != stack_alloc)
2026 panic("only stack-alloc supported in sparc backend (at %+F)", node);
2027 /* lowerer should have transformed all allocas to byte size */
2028 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
2029 panic("Found non-byte alloc in sparc backend (at %+F)", node);
2031 if (is_Const(size)) {
2032 ir_tarval *tv = get_Const_tarval(size);
2033 long sizel = get_tarval_long(tv);
2034 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
2035 set_irn_dbg_info(addsp, dbgi);
2037 ir_node *new_size = be_transform_node(size);
2038 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
2039 arch_set_irn_register(addsp, sp_reg);
2042 /* if we are the last IncSP producer in a block then we have to keep
2044 * Note: This here keeps all producers which is more than necessary */
2047 pmap_insert(node_to_stack, node, addsp);
2048 /* the "result" is the unmodified sp value */
2052 static const arch_register_req_t float1_req = {
2053 arch_register_req_type_normal,
2054 &sparc_reg_classes[CLASS_sparc_fp],
2060 static const arch_register_req_t float2_req = {
2061 arch_register_req_type_normal | arch_register_req_type_aligned,
2062 &sparc_reg_classes[CLASS_sparc_fp],
2068 static const arch_register_req_t float4_req = {
2069 arch_register_req_type_normal | arch_register_req_type_aligned,
2070 &sparc_reg_classes[CLASS_sparc_fp],
2078 static const arch_register_req_t *get_float_req(ir_mode *mode)
2080 unsigned bits = get_mode_size_bits(mode);
2082 assert(mode_is_float(mode));
2085 } else if (bits == 64) {
2088 assert(bits == 128);
2094 * Transform some Phi nodes
2096 static ir_node *gen_Phi(ir_node *node)
2098 const arch_register_req_t *req;
2099 ir_node *block = be_transform_node(get_nodes_block(node));
2100 ir_graph *irg = current_ir_graph;
2101 dbg_info *dbgi = get_irn_dbg_info(node);
2102 ir_mode *mode = get_irn_mode(node);
2105 if (mode_needs_gp_reg(mode)) {
2106 /* we shouldn't have any 64bit stuff around anymore */
2107 assert(get_mode_size_bits(mode) <= 32);
2108 /* all integer operations are on 32bit registers now */
2110 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2111 } else if (mode_is_float(mode)) {
2113 req = get_float_req(mode);
2115 req = arch_no_register_req;
2118 /* phi nodes allow loops, so we use the old arguments for now
2119 * and fix this later */
2120 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2121 copy_node_attr(irg, node, phi);
2122 be_duplicate_deps(node, phi);
2123 arch_set_irn_register_req_out(phi, 0, req);
2124 be_enqueue_preds(node);
2129 * Transform a Proj from a Load.
2131 static ir_node *gen_Proj_Load(ir_node *node)
2133 ir_node *load = get_Proj_pred(node);
2134 ir_node *new_load = be_transform_node(load);
2135 dbg_info *dbgi = get_irn_dbg_info(node);
2136 long pn = get_Proj_proj(node);
2138 /* renumber the proj */
2139 switch (get_sparc_irn_opcode(new_load)) {
2141 /* handle all gp loads equal: they have the same proj numbers. */
2142 if (pn == pn_Load_res) {
2143 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2144 } else if (pn == pn_Load_M) {
2145 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2149 if (pn == pn_Load_res) {
2150 const sparc_load_store_attr_t *attr
2151 = get_sparc_load_store_attr_const(new_load);
2152 ir_mode *mode = attr->load_store_mode;
2153 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2154 } else if (pn == pn_Load_M) {
2155 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2161 panic("Unsupported Proj from Load");
2164 static ir_node *gen_Proj_Store(ir_node *node)
2166 ir_node *store = get_Proj_pred(node);
2167 ir_node *new_store = be_transform_node(store);
2168 long pn = get_Proj_proj(node);
2170 /* renumber the proj */
2171 switch (get_sparc_irn_opcode(new_store)) {
2173 if (pn == pn_Store_M) {
2178 if (pn == pn_Store_M) {
2185 panic("Unsupported Proj from Store");
2189 * Transform the Projs from a Cmp.
2191 static ir_node *gen_Proj_Cmp(ir_node *node)
2194 panic("not implemented");
2198 * transform Projs from a Div
2200 static ir_node *gen_Proj_Div(ir_node *node)
2202 ir_node *pred = get_Proj_pred(node);
2203 ir_node *new_pred = be_transform_node(pred);
2204 long pn = get_Proj_proj(node);
2207 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2209 } else if (is_sparc_fdiv(new_pred)) {
2210 res_mode = get_Div_resmode(pred);
2212 panic("sparc backend: Div transformed to something unexpected: %+F",
2215 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2216 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2217 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2218 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2221 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2223 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
2227 panic("Unsupported Proj from Div");
2230 static ir_node *get_frame_base(ir_graph *irg)
2232 if (frame_base == NULL) {
2233 if (current_cconv->omit_fp) {
2234 frame_base = get_initial_sp(irg);
2236 frame_base = get_initial_fp(irg);
2242 static ir_node *gen_Proj_Start(ir_node *node)
2244 ir_node *block = get_nodes_block(node);
2245 ir_node *new_block = be_transform_node(block);
2246 long pn = get_Proj_proj(node);
2247 /* make sure prolog is constructed */
2248 be_transform_node(get_Proj_pred(node));
2250 switch ((pn_Start) pn) {
2251 case pn_Start_X_initial_exec:
2252 /* exchange ProjX with a jump */
2253 return new_bd_sparc_Ba(NULL, new_block);
2255 ir_graph *irg = get_irn_irg(node);
2256 return get_initial_mem(irg);
2258 case pn_Start_T_args:
2259 return new_r_Bad(get_irn_irg(block), mode_T);
2260 case pn_Start_P_frame_base:
2261 return get_frame_base(get_irn_irg(block));
2263 panic("Unexpected start proj: %ld\n", pn);
2266 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2268 long pn = get_Proj_proj(node);
2269 ir_node *block = get_nodes_block(node);
2270 ir_graph *irg = get_irn_irg(node);
2271 ir_node *new_block = be_transform_node(block);
2272 ir_node *args = get_Proj_pred(node);
2273 ir_node *start = get_Proj_pred(args);
2274 ir_node *new_start = be_transform_node(start);
2275 const reg_or_stackslot_t *param;
2277 /* Proj->Proj->Start must be a method argument */
2278 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2280 param = ¤t_cconv->parameters[pn];
2282 if (param->reg0 != NULL) {
2283 /* argument transmitted in register */
2284 const arch_register_t *reg = param->reg0;
2285 ir_mode *reg_mode = reg->reg_class->mode;
2286 long new_pn = param->reg_offset + start_params_offset;
2287 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2288 bool is_float = false;
2291 ir_entity *entity = get_irg_entity(irg);
2292 ir_type *method_type = get_entity_type(entity);
2293 if (pn < (long)get_method_n_params(method_type)) {
2294 ir_type *param_type = get_method_param_type(method_type, pn);
2295 ir_mode *mode = get_type_mode(param_type);
2296 is_float = mode_is_float(mode);
2301 const arch_register_t *reg1 = param->reg1;
2302 ir_node *value1 = NULL;
2305 ir_mode *reg1_mode = reg1->reg_class->mode;
2306 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2307 } else if (param->entity != NULL) {
2308 ir_node *fp = get_initial_fp(irg);
2309 ir_node *mem = get_initial_mem(irg);
2310 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2311 mode_gp, param->entity,
2313 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2316 /* convert integer value to float */
2317 value = bitcast_int_to_float(NULL, new_block, value, value1);
2321 /* argument transmitted on stack */
2322 ir_node *mem = get_initial_mem(irg);
2323 ir_mode *mode = get_type_mode(param->type);
2324 ir_node *base = get_frame_base(irg);
2328 if (mode_is_float(mode)) {
2329 load = create_ldf(NULL, new_block, base, mem, mode,
2330 param->entity, 0, true);
2331 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2333 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2334 param->entity, 0, true);
2335 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2337 set_irn_pinned(load, op_pin_state_floats);
2343 static ir_node *gen_Proj_Call(ir_node *node)
2345 long pn = get_Proj_proj(node);
2346 ir_node *call = get_Proj_pred(node);
2347 ir_node *new_call = be_transform_node(call);
2349 switch ((pn_Call) pn) {
2351 return new_r_Proj(new_call, mode_M, 0);
2352 case pn_Call_X_regular:
2353 case pn_Call_X_except:
2354 case pn_Call_T_result:
2357 panic("Unexpected Call proj %ld\n", pn);
2360 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2362 long pn = get_Proj_proj(node);
2363 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2364 ir_node *new_call = be_transform_node(call);
2365 ir_type *function_type = get_Call_type(call);
2366 calling_convention_t *cconv
2367 = sparc_decide_calling_convention(function_type, NULL);
2368 const reg_or_stackslot_t *res = &cconv->results[pn];
2369 ir_mode *mode = get_irn_mode(node);
2370 long new_pn = 1 + res->reg_offset;
2372 assert(res->req0 != NULL && res->req1 == NULL);
2373 if (mode_needs_gp_reg(mode)) {
2376 sparc_free_calling_convention(cconv);
2378 return new_r_Proj(new_call, mode, new_pn);
2382 * Transform a Proj node.
2384 static ir_node *gen_Proj(ir_node *node)
2386 ir_node *pred = get_Proj_pred(node);
2388 switch (get_irn_opcode(pred)) {
2390 return gen_Proj_Alloc(node);
2392 return gen_Proj_Store(node);
2394 return gen_Proj_Load(node);
2396 return gen_Proj_Call(node);
2398 return gen_Proj_Cmp(node);
2400 return be_duplicate_node(node);
2402 return gen_Proj_Div(node);
2404 return gen_Proj_Start(node);
2406 ir_node *pred_pred = get_Proj_pred(pred);
2407 if (is_Call(pred_pred)) {
2408 return gen_Proj_Proj_Call(node);
2409 } else if (is_Start(pred_pred)) {
2410 return gen_Proj_Proj_Start(node);
2415 if (is_sparc_AddCC_t(pred)) {
2416 return gen_Proj_AddCC_t(node);
2417 } else if (is_sparc_SubCC_t(pred)) {
2418 return gen_Proj_SubCC_t(node);
2420 panic("code selection didn't expect Proj after %+F\n", pred);
2427 static ir_node *gen_Jmp(ir_node *node)
2429 ir_node *block = get_nodes_block(node);
2430 ir_node *new_block = be_transform_node(block);
2431 dbg_info *dbgi = get_irn_dbg_info(node);
2433 return new_bd_sparc_Ba(dbgi, new_block);
2437 * configure transformation callbacks
2439 static void sparc_register_transformers(void)
2441 be_start_transform_setup();
2443 be_set_transform_function(op_Add, gen_Add);
2444 be_set_transform_function(op_Alloc, gen_Alloc);
2445 be_set_transform_function(op_And, gen_And);
2446 be_set_transform_function(op_Call, gen_Call);
2447 be_set_transform_function(op_Cmp, gen_Cmp);
2448 be_set_transform_function(op_Cond, gen_Cond);
2449 be_set_transform_function(op_Const, gen_Const);
2450 be_set_transform_function(op_Conv, gen_Conv);
2451 be_set_transform_function(op_Div, gen_Div);
2452 be_set_transform_function(op_Eor, gen_Eor);
2453 be_set_transform_function(op_Free, gen_Free);
2454 be_set_transform_function(op_Jmp, gen_Jmp);
2455 be_set_transform_function(op_Load, gen_Load);
2456 be_set_transform_function(op_Minus, gen_Minus);
2457 be_set_transform_function(op_Mul, gen_Mul);
2458 be_set_transform_function(op_Mulh, gen_Mulh);
2459 be_set_transform_function(op_Not, gen_Not);
2460 be_set_transform_function(op_Or, gen_Or);
2461 be_set_transform_function(op_Phi, gen_Phi);
2462 be_set_transform_function(op_Proj, gen_Proj);
2463 be_set_transform_function(op_Return, gen_Return);
2464 be_set_transform_function(op_Sel, gen_Sel);
2465 be_set_transform_function(op_Shl, gen_Shl);
2466 be_set_transform_function(op_Shr, gen_Shr);
2467 be_set_transform_function(op_Shrs, gen_Shrs);
2468 be_set_transform_function(op_Start, gen_Start);
2469 be_set_transform_function(op_Store, gen_Store);
2470 be_set_transform_function(op_Sub, gen_Sub);
2471 be_set_transform_function(op_SymConst, gen_SymConst);
2472 be_set_transform_function(op_Unknown, gen_Unknown);
2474 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2475 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2476 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2477 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2478 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2482 * Transform a Firm graph into a SPARC graph.
2484 void sparc_transform_graph(ir_graph *irg)
2486 ir_entity *entity = get_irg_entity(irg);
2487 ir_type *frame_type;
2489 sparc_register_transformers();
2491 node_to_stack = pmap_create();
2493 mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
2494 mode_fp = sparc_reg_classes[CLASS_sparc_fp].mode;
2497 mode_flags = sparc_reg_classes[CLASS_sparc_flags_class].mode;
2498 assert(sparc_reg_classes[CLASS_sparc_fpflags_class].mode == mode_flags);
2507 stackorder = be_collect_stacknodes(irg);
2509 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2510 if (sparc_variadic_fixups(irg, current_cconv)) {
2511 sparc_free_calling_convention(current_cconv);
2513 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2515 sparc_create_stacklayout(irg, current_cconv);
2516 be_add_parameter_entity_stores(irg);
2518 be_transform_graph(irg, NULL);
2520 be_free_stackorder(stackorder);
2521 sparc_free_calling_convention(current_cconv);
2523 frame_type = get_irg_frame_type(irg);
2524 if (get_type_state(frame_type) == layout_undefined)
2525 default_layout_compound_type(frame_type);
2527 pmap_destroy(node_to_stack);
2528 node_to_stack = NULL;
2530 be_add_missing_keeps(irg);
2532 /* do code placement, to optimize the position of constants */
2534 /* backend expects outedges to be always on */
2538 void sparc_init_transform(void)
2540 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");