2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
32 #include "irgraph_t.h"
38 #include "iroptimize.h"
45 #include "../benode.h"
47 #include "../beutil.h"
48 #include "../betranshlp.h"
49 #include "../beabihelper.h"
50 #include "bearch_sparc_t.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_transform.h"
54 #include "sparc_new_nodes.h"
55 #include "gen_sparc_new_nodes.h"
57 #include "gen_sparc_regalloc_if.h"
58 #include "sparc_cconv.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *current_cconv = NULL;
67 static be_stackorder_t *stackorder;
68 static ir_mode *mode_gp;
69 static ir_mode *mode_flags;
70 static ir_mode *mode_fp;
71 static ir_mode *mode_fp2;
72 //static ir_mode *mode_fp4;
73 static pmap *node_to_stack;
74 static size_t start_mem_offset;
75 static ir_node *start_mem;
76 static size_t start_g0_offset;
77 static ir_node *start_g0;
78 static size_t start_g7_offset;
79 static ir_node *start_g7;
80 static size_t start_sp_offset;
81 static ir_node *start_sp;
82 static size_t start_fp_offset;
83 static ir_node *start_fp;
84 static ir_node *frame_base;
85 static size_t start_params_offset;
86 static size_t start_callee_saves_offset;
88 static const arch_register_t *const omit_fp_callee_saves[] = {
89 &sparc_registers[REG_L0],
90 &sparc_registers[REG_L1],
91 &sparc_registers[REG_L2],
92 &sparc_registers[REG_L3],
93 &sparc_registers[REG_L4],
94 &sparc_registers[REG_L5],
95 &sparc_registers[REG_L6],
96 &sparc_registers[REG_L7],
97 &sparc_registers[REG_I0],
98 &sparc_registers[REG_I1],
99 &sparc_registers[REG_I2],
100 &sparc_registers[REG_I3],
101 &sparc_registers[REG_I4],
102 &sparc_registers[REG_I5],
105 static inline bool mode_needs_gp_reg(ir_mode *mode)
107 if (mode_is_int(mode) || mode_is_reference(mode)) {
108 /* we should only see 32bit code */
109 assert(get_mode_size_bits(mode) <= 32);
116 * Create an And that will zero out upper bits.
118 * @param dbgi debug info
119 * @param block the basic block
120 * @param op the original node
121 * @param src_bits number of lower bits that will remain
123 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
127 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
128 } else if (src_bits == 16) {
129 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
130 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
133 panic("zero extension only supported for 8 and 16 bits");
138 * Generate code for a sign extension.
140 * @param dbgi debug info
141 * @param block the basic block
142 * @param op the original node
143 * @param src_bits number of lower bits that will remain
145 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
148 int shift_width = 32 - src_bits;
149 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
150 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
155 * returns true if it is assured, that the upper bits of a node are "clean"
156 * which means for a 16 or 8 bit value, that the upper bits in the register
157 * are 0 for unsigned and a copy of the last significant bit for signed
160 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
162 (void) transformed_node;
169 * Extend a value to 32 bit signed/unsigned depending on its mode.
171 * @param dbgi debug info
172 * @param block the basic block
173 * @param op the original node
174 * @param orig_mode the original mode of op
176 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
179 int bits = get_mode_size_bits(orig_mode);
183 if (mode_is_signed(orig_mode)) {
184 return gen_sign_extension(dbgi, block, op, bits);
186 return gen_zero_extension(dbgi, block, op, bits);
192 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
193 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
194 influence the significant lower bit at
195 all (for cases where mode < 32bit) */
197 ENUM_BITSET(match_flags_t)
199 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
200 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
201 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
202 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
205 * checks if a node's value can be encoded as a immediate
207 static bool is_imm_encodeable(const ir_node *node)
213 value = get_tarval_long(get_Const_tarval(node));
214 return sparc_is_value_imm_encodeable(value);
217 static bool needs_extension(ir_mode *mode)
219 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
223 * Check, if a given node is a Down-Conv, ie. a integer Conv
224 * from a mode with a mode with more bits to a mode with lesser bits.
225 * Moreover, we return only true if the node has not more than 1 user.
227 * @param node the node
228 * @return non-zero if node is a Down-Conv
230 static bool is_downconv(const ir_node *node)
238 src_mode = get_irn_mode(get_Conv_op(node));
239 dest_mode = get_irn_mode(node);
241 mode_needs_gp_reg(src_mode) &&
242 mode_needs_gp_reg(dest_mode) &&
243 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
246 static ir_node *skip_downconv(ir_node *node)
248 while (is_downconv(node)) {
249 node = get_Conv_op(node);
255 * helper function for binop operations
257 * @param new_reg register generation function ptr
258 * @param new_imm immediate generation function ptr
260 static ir_node *gen_helper_binop_args(ir_node *node,
261 ir_node *op1, ir_node *op2,
263 new_binop_reg_func new_reg,
264 new_binop_imm_func new_imm)
266 dbg_info *dbgi = get_irn_dbg_info(node);
267 ir_node *block = be_transform_node(get_nodes_block(node));
273 if (flags & MATCH_MODE_NEUTRAL) {
274 op1 = skip_downconv(op1);
275 op2 = skip_downconv(op2);
277 mode1 = get_irn_mode(op1);
278 mode2 = get_irn_mode(op2);
279 /* we shouldn't see 64bit code */
280 assert(get_mode_size_bits(mode1) <= 32);
281 assert(get_mode_size_bits(mode2) <= 32);
283 if (is_imm_encodeable(op2)) {
284 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
285 new_op1 = be_transform_node(op1);
286 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
287 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
289 return new_imm(dbgi, block, new_op1, NULL, immediate);
291 new_op2 = be_transform_node(op2);
292 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
293 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
296 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
297 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
298 return new_imm(dbgi, block, new_op2, NULL, immediate);
301 new_op1 = be_transform_node(op1);
302 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
303 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
305 return new_reg(dbgi, block, new_op1, new_op2);
308 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
309 new_binop_reg_func new_reg,
310 new_binop_imm_func new_imm)
312 ir_node *op1 = get_binop_left(node);
313 ir_node *op2 = get_binop_right(node);
314 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
318 * helper function for FP binop operations
320 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
321 new_binop_fp_func new_func_single,
322 new_binop_fp_func new_func_double,
323 new_binop_fp_func new_func_quad)
325 ir_node *block = be_transform_node(get_nodes_block(node));
326 ir_node *op1 = get_binop_left(node);
327 ir_node *new_op1 = be_transform_node(op1);
328 ir_node *op2 = get_binop_right(node);
329 ir_node *new_op2 = be_transform_node(op2);
330 dbg_info *dbgi = get_irn_dbg_info(node);
331 unsigned bits = get_mode_size_bits(mode);
335 return new_func_single(dbgi, block, new_op1, new_op2, mode);
337 return new_func_double(dbgi, block, new_op1, new_op2, mode);
339 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
343 panic("unsupported mode %+F for float op", mode);
346 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
347 new_unop_fp_func new_func_single,
348 new_unop_fp_func new_func_double,
349 new_unop_fp_func new_func_quad)
351 ir_node *block = be_transform_node(get_nodes_block(node));
352 ir_node *op = get_unop_op(node);
353 ir_node *new_op = be_transform_node(op);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 unsigned bits = get_mode_size_bits(mode);
359 return new_func_single(dbgi, block, new_op, mode);
361 return new_func_double(dbgi, block, new_op, mode);
363 return new_func_quad(dbgi, block, new_op, mode);
367 panic("unsupported mode %+F for float op", mode);
370 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
371 ir_node *op1, ir_node *flags,
372 ir_entity *imm_entity, int32_t imm);
374 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
375 ir_node *op1, ir_node *op2,
378 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
379 new_binopx_reg_func new_binopx_reg,
380 new_binopx_imm_func new_binopx_imm)
382 dbg_info *dbgi = get_irn_dbg_info(node);
383 ir_node *block = be_transform_node(get_nodes_block(node));
384 ir_node *op1 = get_irn_n(node, 0);
385 ir_node *op2 = get_irn_n(node, 1);
386 ir_node *flags = get_irn_n(node, 2);
387 ir_node *new_flags = be_transform_node(flags);
391 /* only support for mode-neutral implemented so far */
392 assert(match_flags & MATCH_MODE_NEUTRAL);
394 if (is_imm_encodeable(op2)) {
395 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
396 new_op1 = be_transform_node(op1);
397 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
399 new_op2 = be_transform_node(op2);
400 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
401 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
402 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
404 new_op1 = be_transform_node(op1);
405 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
409 static ir_node *get_g0(ir_graph *irg)
411 if (start_g0 == NULL) {
412 /* this is already the transformed start node */
413 ir_node *start = get_irg_start(irg);
414 assert(is_sparc_Start(start));
415 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
420 static ir_node *get_g7(ir_graph *irg)
422 if (start_g7 == NULL) {
423 ir_node *start = get_irg_start(irg);
424 assert(is_sparc_Start(start));
425 start_g7 = new_r_Proj(start, mode_gp, start_g7_offset);
430 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
431 ir_entity *entity, int32_t offset)
433 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
434 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
438 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
441 if (get_entity_owner(entity) == get_tls_type()) {
442 ir_graph *irg = get_irn_irg(block);
443 ir_node *g7 = get_g7(irg);
444 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
445 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
448 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
449 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
454 typedef struct address_t {
462 * Match a load/store address
464 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
467 ir_node *ptr2 = NULL;
469 ir_entity *entity = NULL;
472 ir_node *add_right = get_Add_right(base);
473 if (is_Const(add_right)) {
474 base = get_Add_left(base);
475 offset += get_tarval_long(get_Const_tarval(add_right));
478 /* Note that we don't match sub(x, Const) or chains of adds/subs
479 * because this should all be normalized by now */
481 /* we only use the symconst if we're the only user otherwise we probably
482 * won't save anything but produce multiple sethi+or combinations with
483 * just different offsets */
484 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
485 ir_entity *sc_entity = get_SymConst_entity(base);
486 dbg_info *dbgi = get_irn_dbg_info(ptr);
487 ir_node *block = get_nodes_block(ptr);
488 ir_node *new_block = be_transform_node(block);
490 if (get_entity_owner(sc_entity) == get_tls_type()) {
494 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
496 base = get_g7(get_irn_irg(base));
500 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
502 } else if (use_ptr2 && is_Add(base) && offset == 0) {
503 ptr2 = be_transform_node(get_Add_right(base));
504 base = be_transform_node(get_Add_left(base));
507 if (sparc_is_value_imm_encodeable(offset)) {
508 base = be_transform_node(base);
510 base = be_transform_node(ptr);
516 address->ptr2 = ptr2;
517 address->entity = entity;
518 address->offset = offset;
522 * Creates an sparc Add.
524 * @param node FIRM node
525 * @return the created sparc Add node
527 static ir_node *gen_Add(ir_node *node)
529 ir_mode *mode = get_irn_mode(node);
532 if (mode_is_float(mode)) {
533 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
534 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
537 /* special case: + 0x1000 can be represented as - 0x1000 */
538 right = get_Add_right(node);
539 if (is_Const(right)) {
540 ir_node *left = get_Add_left(node);
543 /* is this simple address arithmetic? then we can let the linker do
544 * the calculation. */
545 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
546 dbg_info *dbgi = get_irn_dbg_info(node);
547 ir_node *block = be_transform_node(get_nodes_block(node));
550 /* the value of use_ptr2 shouldn't matter here */
551 match_address(node, &address, false);
552 assert(is_sparc_SetHi(address.ptr));
553 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
554 address.entity, address.offset);
557 tv = get_Const_tarval(right);
558 val = get_tarval_long(tv);
560 dbg_info *dbgi = get_irn_dbg_info(node);
561 ir_node *block = be_transform_node(get_nodes_block(node));
562 ir_node *op = get_Add_left(node);
563 ir_node *new_op = be_transform_node(op);
564 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
568 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
569 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
572 static ir_node *gen_AddCC_t(ir_node *node)
574 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
575 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
578 static ir_node *gen_Proj_AddCC_t(ir_node *node)
580 long pn = get_Proj_proj(node);
581 ir_node *pred = get_Proj_pred(node);
582 ir_node *new_pred = be_transform_node(pred);
585 case pn_sparc_AddCC_t_res:
586 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
587 case pn_sparc_AddCC_t_flags:
588 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
590 panic("Invalid AddCC_t proj found");
594 static ir_node *gen_AddX_t(ir_node *node)
596 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
597 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
601 * Creates an sparc Sub.
603 * @param node FIRM node
604 * @return the created sparc Sub node
606 static ir_node *gen_Sub(ir_node *node)
608 ir_mode *mode = get_irn_mode(node);
610 if (mode_is_float(mode)) {
611 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
612 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
615 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
616 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
619 static ir_node *gen_SubCC_t(ir_node *node)
621 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
622 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
625 static ir_node *gen_Proj_SubCC_t(ir_node *node)
627 long pn = get_Proj_proj(node);
628 ir_node *pred = get_Proj_pred(node);
629 ir_node *new_pred = be_transform_node(pred);
632 case pn_sparc_SubCC_t_res:
633 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
634 case pn_sparc_SubCC_t_flags:
635 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
637 panic("Invalid SubCC_t proj found");
641 static ir_node *gen_SubX_t(ir_node *node)
643 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
644 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
647 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
648 ir_node *mem, ir_mode *mode, ir_entity *entity,
649 long offset, bool is_frame_entity)
651 unsigned bits = get_mode_size_bits(mode);
652 assert(mode_is_float(mode));
654 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
655 offset, is_frame_entity);
656 } else if (bits == 64) {
657 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
658 offset, is_frame_entity);
661 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
662 offset, is_frame_entity);
666 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
667 ir_node *ptr, ir_node *mem, ir_mode *mode,
668 ir_entity *entity, long offset,
669 bool is_frame_entity)
671 unsigned bits = get_mode_size_bits(mode);
672 assert(mode_is_float(mode));
674 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
675 offset, is_frame_entity);
676 } else if (bits == 64) {
677 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
678 offset, is_frame_entity);
681 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
682 offset, is_frame_entity);
689 * @param node the ir Load node
690 * @return the created sparc Load node
692 static ir_node *gen_Load(ir_node *node)
694 dbg_info *dbgi = get_irn_dbg_info(node);
695 ir_mode *mode = get_Load_mode(node);
696 ir_node *block = be_transform_node(get_nodes_block(node));
697 ir_node *ptr = get_Load_ptr(node);
698 ir_node *mem = get_Load_mem(node);
699 ir_node *new_mem = be_transform_node(mem);
700 ir_node *new_load = NULL;
703 if (get_Load_unaligned(node) == align_non_aligned) {
704 panic("sparc: transformation of unaligned Loads not implemented yet");
707 if (mode_is_float(mode)) {
708 match_address(ptr, &address, false);
709 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
710 address.entity, address.offset, false);
712 match_address(ptr, &address, true);
713 if (address.ptr2 != NULL) {
714 assert(address.entity == NULL && address.offset == 0);
715 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
716 address.ptr2, new_mem, mode);
718 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
719 mode, address.entity, address.offset,
723 set_irn_pinned(new_load, get_irn_pinned(node));
729 * Transforms a Store.
731 * @param node the ir Store node
732 * @return the created sparc Store node
734 static ir_node *gen_Store(ir_node *node)
736 ir_node *block = be_transform_node(get_nodes_block(node));
737 ir_node *ptr = get_Store_ptr(node);
738 ir_node *mem = get_Store_mem(node);
739 ir_node *new_mem = be_transform_node(mem);
740 ir_node *val = get_Store_value(node);
741 ir_mode *mode = get_irn_mode(val);
742 dbg_info *dbgi = get_irn_dbg_info(node);
743 ir_node *new_store = NULL;
746 if (get_Store_unaligned(node) == align_non_aligned) {
747 panic("sparc: transformation of unaligned Stores not implemented yet");
750 if (mode_is_float(mode)) {
751 ir_node *new_val = be_transform_node(val);
752 /* TODO: variants with reg+reg address mode */
753 match_address(ptr, &address, false);
754 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
755 mode, address.entity, address.offset, false);
758 unsigned dest_bits = get_mode_size_bits(mode);
759 while (is_downconv(node)
760 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
761 val = get_Conv_op(val);
763 new_val = be_transform_node(val);
765 assert(dest_bits <= 32);
766 match_address(ptr, &address, true);
767 if (address.ptr2 != NULL) {
768 assert(address.entity == NULL && address.offset == 0);
769 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
770 address.ptr2, new_mem, mode);
772 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
773 new_mem, mode, address.entity,
774 address.offset, false);
777 set_irn_pinned(new_store, get_irn_pinned(node));
783 * Creates an sparc Mul.
784 * returns the lower 32bits of the 64bit multiply result
786 * @return the created sparc Mul node
788 static ir_node *gen_Mul(ir_node *node)
790 ir_mode *mode = get_irn_mode(node);
791 if (mode_is_float(mode)) {
792 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
793 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
796 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
797 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
801 * Creates an sparc Mulh.
802 * Mulh returns the upper 32bits of a mul instruction
804 * @return the created sparc Mulh node
806 static ir_node *gen_Mulh(ir_node *node)
808 ir_mode *mode = get_irn_mode(node);
811 if (mode_is_float(mode))
812 panic("FP not supported yet");
814 if (mode_is_signed(mode)) {
815 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
816 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
818 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
819 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
823 static ir_node *gen_sign_extension_value(ir_node *node)
825 ir_node *block = get_nodes_block(node);
826 ir_node *new_block = be_transform_node(block);
827 ir_node *new_node = be_transform_node(node);
828 /* TODO: we could do some shortcuts for some value types probably.
829 * (For constants or other cases where we know the sign bit in
831 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
835 * Creates an sparc Div.
837 * @return the created sparc Div node
839 static ir_node *gen_Div(ir_node *node)
841 dbg_info *dbgi = get_irn_dbg_info(node);
842 ir_node *block = get_nodes_block(node);
843 ir_node *new_block = be_transform_node(block);
844 ir_mode *mode = get_Div_resmode(node);
845 ir_node *left = get_Div_left(node);
846 ir_node *left_low = be_transform_node(left);
847 ir_node *right = get_Div_right(node);
850 if (mode_is_float(mode)) {
851 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
852 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
855 if (mode_is_signed(mode)) {
856 ir_node *left_high = gen_sign_extension_value(left);
858 if (is_imm_encodeable(right)) {
859 int32_t immediate = get_tarval_long(get_Const_tarval(right));
860 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
863 ir_node *new_right = be_transform_node(right);
864 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
868 ir_graph *irg = get_irn_irg(node);
869 ir_node *left_high = get_g0(irg);
870 if (is_imm_encodeable(right)) {
871 int32_t immediate = get_tarval_long(get_Const_tarval(right));
872 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
875 ir_node *new_right = be_transform_node(right);
876 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
885 * Transforms a Not node.
887 * @return the created sparc Not node
889 static ir_node *gen_Not(ir_node *node)
891 ir_node *op = get_Not_op(node);
892 ir_graph *irg = get_irn_irg(node);
893 ir_node *zero = get_g0(irg);
894 dbg_info *dbgi = get_irn_dbg_info(node);
895 ir_node *block = be_transform_node(get_nodes_block(node));
896 ir_node *new_op = be_transform_node(op);
898 /* Note: Not(Eor()) is normalize in firm localopts already so
899 * we don't match it for xnor here */
901 /* Not can be represented with xnor 0, n */
902 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
905 static ir_node *gen_helper_bitop(ir_node *node,
906 new_binop_reg_func new_reg,
907 new_binop_imm_func new_imm,
908 new_binop_reg_func new_not_reg,
909 new_binop_imm_func new_not_imm,
912 ir_node *op1 = get_binop_left(node);
913 ir_node *op2 = get_binop_right(node);
915 return gen_helper_binop_args(node, op2, get_Not_op(op1),
917 new_not_reg, new_not_imm);
920 return gen_helper_binop_args(node, op1, get_Not_op(op2),
922 new_not_reg, new_not_imm);
924 return gen_helper_binop_args(node, op1, op2,
925 flags | MATCH_COMMUTATIVE,
929 static ir_node *gen_And(ir_node *node)
931 return gen_helper_bitop(node,
932 new_bd_sparc_And_reg,
933 new_bd_sparc_And_imm,
934 new_bd_sparc_AndN_reg,
935 new_bd_sparc_AndN_imm,
939 static ir_node *gen_Or(ir_node *node)
941 return gen_helper_bitop(node,
944 new_bd_sparc_OrN_reg,
945 new_bd_sparc_OrN_imm,
949 static ir_node *gen_Eor(ir_node *node)
951 return gen_helper_bitop(node,
952 new_bd_sparc_Xor_reg,
953 new_bd_sparc_Xor_imm,
954 new_bd_sparc_XNor_reg,
955 new_bd_sparc_XNor_imm,
959 static ir_node *gen_Shl(ir_node *node)
961 ir_mode *mode = get_irn_mode(node);
962 if (get_mode_modulo_shift(mode) != 32)
963 panic("modulo_shift!=32 not supported by sparc backend");
964 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
967 static ir_node *gen_Shr(ir_node *node)
969 ir_mode *mode = get_irn_mode(node);
970 if (get_mode_modulo_shift(mode) != 32)
971 panic("modulo_shift!=32 not supported by sparc backend");
972 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
975 static ir_node *gen_Shrs(ir_node *node)
977 ir_mode *mode = get_irn_mode(node);
978 if (get_mode_modulo_shift(mode) != 32)
979 panic("modulo_shift!=32 not supported by sparc backend");
980 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
984 * Transforms a Minus node.
986 static ir_node *gen_Minus(ir_node *node)
988 ir_mode *mode = get_irn_mode(node);
995 if (mode_is_float(mode)) {
996 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
997 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
999 block = be_transform_node(get_nodes_block(node));
1000 dbgi = get_irn_dbg_info(node);
1001 op = get_Minus_op(node);
1002 new_op = be_transform_node(op);
1003 zero = get_g0(get_irn_irg(node));
1004 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1008 * Create an entity for a given (floating point) tarval
1010 static ir_entity *create_float_const_entity(ir_tarval *tv)
1012 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
1013 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1014 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
1015 ir_initializer_t *initializer;
1023 mode = get_tarval_mode(tv);
1024 type = get_type_for_mode(mode);
1025 glob = get_glob_type();
1026 entity = new_entity(glob, id_unique("C%u"), type);
1027 set_entity_visibility(entity, ir_visibility_private);
1028 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1030 initializer = create_initializer_tarval(tv);
1031 set_entity_initializer(entity, initializer);
1033 pmap_insert(isa->constants, tv, entity);
1037 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1039 ir_entity *entity = create_float_const_entity(tv);
1040 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1041 ir_node *mem = get_irg_no_mem(current_ir_graph);
1042 ir_mode *mode = get_tarval_mode(tv);
1044 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1045 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1047 set_irn_pinned(new_op, op_pin_state_floats);
1051 static ir_node *gen_Const(ir_node *node)
1053 ir_node *block = be_transform_node(get_nodes_block(node));
1054 ir_mode *mode = get_irn_mode(node);
1055 dbg_info *dbgi = get_irn_dbg_info(node);
1056 ir_tarval *tv = get_Const_tarval(node);
1059 if (mode_is_float(mode)) {
1060 return gen_float_const(dbgi, block, tv);
1063 value = get_tarval_long(tv);
1065 return get_g0(get_irn_irg(node));
1066 } else if (sparc_is_value_imm_encodeable(value)) {
1067 ir_graph *irg = get_irn_irg(node);
1068 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1070 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1071 if ((value & 0x3ff) != 0) {
1072 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1079 static ir_mode *get_cmp_mode(ir_node *b_value)
1083 if (!is_Cmp(b_value))
1084 panic("can't determine cond signednes (no cmp)");
1085 op = get_Cmp_left(b_value);
1086 return get_irn_mode(op);
1089 static ir_node *gen_SwitchJmp(ir_node *node)
1091 dbg_info *dbgi = get_irn_dbg_info(node);
1092 ir_node *block = be_transform_node(get_nodes_block(node));
1093 ir_node *selector = get_Cond_selector(node);
1094 ir_node *new_selector = be_transform_node(selector);
1095 long default_pn = get_Cond_default_proj(node);
1097 ir_node *table_address;
1102 /* switch with smaller mode not implemented yet */
1103 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1105 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1106 set_entity_visibility(entity, ir_visibility_private);
1107 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1109 /* construct base address */
1110 table_address = make_address(dbgi, block, entity, 0);
1112 idx = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
1113 /* load from jumptable */
1114 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, idx,
1115 get_irg_no_mem(current_ir_graph),
1117 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1119 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
1122 static ir_node *gen_Cond(ir_node *node)
1124 ir_node *selector = get_Cond_selector(node);
1125 ir_mode *mode = get_irn_mode(selector);
1129 ir_relation relation;
1132 /* switch/case jumps */
1133 if (mode != mode_b) {
1134 return gen_SwitchJmp(node);
1137 block = be_transform_node(get_nodes_block(node));
1138 dbgi = get_irn_dbg_info(node);
1140 /* regular if/else jumps */
1141 if (is_Cmp(selector)) {
1144 cmp_mode = get_cmp_mode(selector);
1145 flag_node = be_transform_node(selector);
1146 relation = get_Cmp_relation(selector);
1147 is_unsigned = !mode_is_signed(cmp_mode);
1148 if (mode_is_float(cmp_mode)) {
1149 assert(!is_unsigned);
1150 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1152 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1155 /* in this case, the selector must already deliver a mode_b value.
1156 * this happens, for example, when the Cond is connected to a Conv
1157 * which converts its argument to mode_b. */
1160 assert(mode == mode_b);
1162 block = be_transform_node(get_nodes_block(node));
1163 irg = get_irn_irg(block);
1164 dbgi = get_irn_dbg_info(node);
1165 new_op = be_transform_node(selector);
1166 /* follow the SPARC architecture manual and use orcc for tst */
1167 flag_node = new_bd_sparc_OrCCZero_reg(dbgi, block, new_op, get_g0(irg));
1168 return new_bd_sparc_Bicc(dbgi, block, flag_node, ir_relation_less_greater, true);
1175 static ir_node *gen_Cmp(ir_node *node)
1177 ir_node *op1 = get_Cmp_left(node);
1178 ir_node *op2 = get_Cmp_right(node);
1179 ir_mode *cmp_mode = get_irn_mode(op1);
1180 assert(get_irn_mode(op2) == cmp_mode);
1182 if (mode_is_float(cmp_mode)) {
1183 ir_node *block = be_transform_node(get_nodes_block(node));
1184 dbg_info *dbgi = get_irn_dbg_info(node);
1185 ir_node *new_op1 = be_transform_node(op1);
1186 ir_node *new_op2 = be_transform_node(op2);
1187 unsigned bits = get_mode_size_bits(cmp_mode);
1189 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1190 } else if (bits == 64) {
1191 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1193 assert(bits == 128);
1194 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1198 /* when we compare a bitop like and,or,... with 0 then we can directly use
1199 * the bitopcc variant.
1200 * Currently we only do this when we're the only user of the node...
1202 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1204 return gen_helper_bitop(op1,
1205 new_bd_sparc_AndCCZero_reg,
1206 new_bd_sparc_AndCCZero_imm,
1207 new_bd_sparc_AndNCCZero_reg,
1208 new_bd_sparc_AndNCCZero_imm,
1210 } else if (is_Or(op1)) {
1211 return gen_helper_bitop(op1,
1212 new_bd_sparc_OrCCZero_reg,
1213 new_bd_sparc_OrCCZero_imm,
1214 new_bd_sparc_OrNCCZero_reg,
1215 new_bd_sparc_OrNCCZero_imm,
1217 } else if (is_Eor(op1)) {
1218 return gen_helper_bitop(op1,
1219 new_bd_sparc_XorCCZero_reg,
1220 new_bd_sparc_XorCCZero_imm,
1221 new_bd_sparc_XNorCCZero_reg,
1222 new_bd_sparc_XNorCCZero_imm,
1227 /* integer compare */
1228 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1229 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1233 * Transforms a SymConst node.
1235 static ir_node *gen_SymConst(ir_node *node)
1237 ir_entity *entity = get_SymConst_entity(node);
1238 dbg_info *dbgi = get_irn_dbg_info(node);
1239 ir_node *block = get_nodes_block(node);
1240 ir_node *new_block = be_transform_node(block);
1241 return make_address(dbgi, new_block, entity, 0);
1244 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1245 ir_mode *src_mode, ir_mode *dst_mode)
1247 unsigned src_bits = get_mode_size_bits(src_mode);
1248 unsigned dst_bits = get_mode_size_bits(dst_mode);
1249 if (src_bits == 32) {
1250 if (dst_bits == 64) {
1251 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1253 assert(dst_bits == 128);
1254 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1256 } else if (src_bits == 64) {
1257 if (dst_bits == 32) {
1258 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1260 assert(dst_bits == 128);
1261 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1264 assert(src_bits == 128);
1265 if (dst_bits == 32) {
1266 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1268 assert(dst_bits == 64);
1269 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1274 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1278 unsigned bits = get_mode_size_bits(src_mode);
1280 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1281 } else if (bits == 64) {
1282 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1284 assert(bits == 128);
1285 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1289 ir_graph *irg = get_irn_irg(block);
1290 ir_node *sp = get_irg_frame(irg);
1291 ir_node *nomem = get_irg_no_mem(irg);
1292 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1294 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1296 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1297 set_irn_pinned(stf, op_pin_state_floats);
1298 set_irn_pinned(ld, op_pin_state_floats);
1303 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1306 ir_graph *irg = get_irn_irg(block);
1307 ir_node *sp = get_irg_frame(irg);
1308 ir_node *nomem = get_irg_no_mem(irg);
1309 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1310 mode_gp, NULL, 0, true);
1311 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1313 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1314 unsigned bits = get_mode_size_bits(dst_mode);
1315 set_irn_pinned(st, op_pin_state_floats);
1316 set_irn_pinned(ldf, op_pin_state_floats);
1319 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1320 } else if (bits == 64) {
1321 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1323 assert(bits == 128);
1324 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1328 static ir_node *gen_Conv(ir_node *node)
1330 ir_node *block = be_transform_node(get_nodes_block(node));
1331 ir_node *op = get_Conv_op(node);
1332 ir_mode *src_mode = get_irn_mode(op);
1333 ir_mode *dst_mode = get_irn_mode(node);
1334 dbg_info *dbgi = get_irn_dbg_info(node);
1337 int src_bits = get_mode_size_bits(src_mode);
1338 int dst_bits = get_mode_size_bits(dst_mode);
1340 if (src_mode == mode_b)
1341 panic("ConvB not lowered %+F", node);
1343 new_op = be_transform_node(op);
1344 if (src_mode == dst_mode)
1347 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1348 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1350 if (mode_is_float(src_mode)) {
1351 if (mode_is_float(dst_mode)) {
1352 /* float -> float conv */
1353 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1355 /* float -> int conv */
1356 if (!mode_is_signed(dst_mode))
1357 panic("float to unsigned not implemented yet");
1358 return create_ftoi(dbgi, block, new_op, src_mode);
1361 /* int -> float conv */
1362 if (src_bits < 32) {
1363 new_op = gen_extension(dbgi, block, new_op, src_mode);
1364 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1365 panic("unsigned to float not lowered!");
1367 return create_itof(dbgi, block, new_op, dst_mode);
1369 } else if (src_mode == mode_b) {
1370 panic("ConvB not lowered %+F", node);
1371 } else { /* complete in gp registers */
1375 if (src_bits == dst_bits) {
1376 /* kill unnecessary conv */
1380 if (dst_mode == mode_b) {
1381 /* mode_b lowering already took care that we only have 0/1 values */
1385 if (src_bits < dst_bits) {
1386 min_bits = src_bits;
1387 min_mode = src_mode;
1389 min_bits = dst_bits;
1390 min_mode = dst_mode;
1393 if (upper_bits_clean(new_op, min_mode)) {
1397 if (mode_is_signed(min_mode)) {
1398 return gen_sign_extension(dbgi, block, new_op, min_bits);
1400 return gen_zero_extension(dbgi, block, new_op, min_bits);
1405 static ir_node *gen_Unknown(ir_node *node)
1407 /* just produce a 0 */
1408 ir_mode *mode = get_irn_mode(node);
1409 if (mode_is_float(mode)) {
1410 ir_node *block = be_transform_node(get_nodes_block(node));
1411 return gen_float_const(NULL, block, get_mode_null(mode));
1412 } else if (mode_needs_gp_reg(mode)) {
1413 ir_graph *irg = get_irn_irg(node);
1417 panic("Unexpected Unknown mode");
1421 * transform the start node to the prolog code
1423 static ir_node *gen_Start(ir_node *node)
1425 ir_graph *irg = get_irn_irg(node);
1426 ir_entity *entity = get_irg_entity(irg);
1427 ir_type *function_type = get_entity_type(entity);
1428 ir_node *block = get_nodes_block(node);
1429 ir_node *new_block = be_transform_node(block);
1430 dbg_info *dbgi = get_irn_dbg_info(node);
1431 struct obstack *obst = be_get_be_obst(irg);
1432 const arch_register_req_t *req;
1438 /* start building list of start constraints */
1439 assert(obstack_object_size(obst) == 0);
1441 /* calculate number of outputs */
1442 n_outs = 4; /* memory, g0, g7, sp */
1443 if (!current_cconv->omit_fp)
1444 ++n_outs; /* framepointer */
1445 /* function parameters */
1446 n_outs += current_cconv->n_param_regs;
1448 if (current_cconv->omit_fp) {
1449 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1452 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1456 /* first output is memory */
1457 start_mem_offset = o;
1458 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1461 /* the zero register */
1462 start_g0_offset = o;
1463 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1464 arch_register_req_type_ignore);
1465 arch_set_irn_register_req_out(start, o, req);
1466 arch_set_irn_register_out(start, o, &sparc_registers[REG_G0]);
1469 /* g7 is used for TLS data */
1470 start_g7_offset = o;
1471 req = be_create_reg_req(obst, &sparc_registers[REG_G7],
1472 arch_register_req_type_ignore);
1473 arch_set_irn_register_req_out(start, o, req);
1474 arch_set_irn_register_out(start, o, &sparc_registers[REG_G7]);
1477 /* we need an output for the stackpointer */
1478 start_sp_offset = o;
1479 req = be_create_reg_req(obst, sp_reg,
1480 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1481 arch_set_irn_register_req_out(start, o, req);
1482 arch_set_irn_register_out(start, o, sp_reg);
1485 if (!current_cconv->omit_fp) {
1486 start_fp_offset = o;
1487 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1488 arch_set_irn_register_req_out(start, o, req);
1489 arch_set_irn_register_out(start, o, fp_reg);
1493 /* function parameters in registers */
1494 start_params_offset = o;
1495 for (i = 0; i < get_method_n_params(function_type); ++i) {
1496 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1497 const arch_register_t *reg0 = param->reg0;
1498 const arch_register_t *reg1 = param->reg1;
1500 arch_set_irn_register_req_out(start, o, reg0->single_req);
1501 arch_set_irn_register_out(start, o, reg0);
1505 arch_set_irn_register_req_out(start, o, reg1->single_req);
1506 arch_set_irn_register_out(start, o, reg1);
1510 /* we need the values of the callee saves (Note: non omit-fp mode has no
1512 start_callee_saves_offset = o;
1513 if (current_cconv->omit_fp) {
1514 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1516 for (c = 0; c < n_callee_saves; ++c) {
1517 const arch_register_t *reg = omit_fp_callee_saves[c];
1518 arch_set_irn_register_req_out(start, o, reg->single_req);
1519 arch_set_irn_register_out(start, o, reg);
1523 assert(n_outs == o);
1528 static ir_node *get_initial_sp(ir_graph *irg)
1530 if (start_sp == NULL) {
1531 ir_node *start = get_irg_start(irg);
1532 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1537 static ir_node *get_initial_fp(ir_graph *irg)
1539 if (start_fp == NULL) {
1540 ir_node *start = get_irg_start(irg);
1541 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1546 static ir_node *get_initial_mem(ir_graph *irg)
1548 if (start_mem == NULL) {
1549 ir_node *start = get_irg_start(irg);
1550 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1555 static ir_node *get_stack_pointer_for(ir_node *node)
1557 /* get predecessor in stack_order list */
1558 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1561 if (stack_pred == NULL) {
1562 /* first stack user in the current block. We can simply use the
1563 * initial sp_proj for it */
1564 ir_graph *irg = get_irn_irg(node);
1565 return get_initial_sp(irg);
1568 be_transform_node(stack_pred);
1569 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1570 if (stack == NULL) {
1571 return get_stack_pointer_for(stack_pred);
1578 * transform a Return node into epilogue code + return statement
1580 static ir_node *gen_Return(ir_node *node)
1582 ir_node *block = get_nodes_block(node);
1583 ir_graph *irg = get_irn_irg(node);
1584 ir_node *new_block = be_transform_node(block);
1585 dbg_info *dbgi = get_irn_dbg_info(node);
1586 ir_node *mem = get_Return_mem(node);
1587 ir_node *new_mem = be_transform_node(mem);
1588 ir_node *sp = get_stack_pointer_for(node);
1589 size_t n_res = get_Return_n_ress(node);
1590 struct obstack *be_obst = be_get_be_obst(irg);
1593 const arch_register_req_t **reqs;
1598 /* estimate number of return values */
1599 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1600 if (current_cconv->omit_fp)
1601 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1603 in = ALLOCAN(ir_node*, n_ins);
1604 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1608 reqs[p] = arch_no_register_req;
1612 reqs[p] = sp_reg->single_req;
1616 for (i = 0; i < n_res; ++i) {
1617 ir_node *res_value = get_Return_res(node, i);
1618 ir_node *new_res_value = be_transform_node(res_value);
1619 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1620 assert(slot->req1 == NULL);
1621 in[p] = new_res_value;
1622 reqs[p] = slot->req0;
1626 if (current_cconv->omit_fp) {
1627 ir_node *start = get_irg_start(irg);
1628 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1629 for (i = 0; i < n_callee_saves; ++i) {
1630 const arch_register_t *reg = omit_fp_callee_saves[i];
1631 ir_mode *mode = reg->reg_class->mode;
1633 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1635 reqs[p] = reg->single_req;
1641 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1642 arch_set_irn_register_reqs_in(bereturn, reqs);
1647 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1648 ir_node *value0, ir_node *value1)
1650 ir_graph *irg = current_ir_graph;
1651 ir_node *sp = get_irg_frame(irg);
1652 ir_node *nomem = get_irg_no_mem(irg);
1653 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1654 mode_gp, NULL, 0, true);
1658 set_irn_pinned(st, op_pin_state_floats);
1660 if (value1 != NULL) {
1661 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1662 mode_gp, NULL, 4, true);
1663 ir_node *in[2] = { st, st1 };
1664 ir_node *sync = new_r_Sync(block, 2, in);
1665 set_irn_pinned(st1, op_pin_state_floats);
1673 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1674 set_irn_pinned(ldf, op_pin_state_floats);
1676 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1679 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1680 ir_node *node, ir_mode *float_mode,
1683 ir_graph *irg = current_ir_graph;
1684 ir_node *stack = get_irg_frame(irg);
1685 ir_node *nomem = get_irg_no_mem(irg);
1686 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1688 int bits = get_mode_size_bits(float_mode);
1690 set_irn_pinned(stf, op_pin_state_floats);
1692 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1693 set_irn_pinned(ld, op_pin_state_floats);
1694 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1697 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1699 set_irn_pinned(ld, op_pin_state_floats);
1700 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1702 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1703 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1710 static ir_node *gen_Call(ir_node *node)
1712 ir_graph *irg = get_irn_irg(node);
1713 ir_node *callee = get_Call_ptr(node);
1714 ir_node *block = get_nodes_block(node);
1715 ir_node *new_block = be_transform_node(block);
1716 ir_node *mem = get_Call_mem(node);
1717 ir_node *new_mem = be_transform_node(mem);
1718 dbg_info *dbgi = get_irn_dbg_info(node);
1719 ir_type *type = get_Call_type(node);
1720 size_t n_params = get_Call_n_params(node);
1721 size_t n_ress = get_method_n_ress(type);
1722 /* max inputs: memory, callee, register arguments */
1723 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1724 struct obstack *obst = be_get_be_obst(irg);
1725 calling_convention_t *cconv
1726 = sparc_decide_calling_convention(type, NULL);
1727 size_t n_param_regs = cconv->n_param_regs;
1728 /* param-regs + mem + stackpointer + callee */
1729 unsigned max_inputs = 3 + n_param_regs;
1730 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1731 const arch_register_req_t **in_req
1732 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1736 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1737 ir_entity *entity = NULL;
1738 ir_node *new_frame = get_stack_pointer_for(node);
1739 bool aggregate_return
1740 = get_method_calling_convention(type) & cc_compound_ret;
1750 assert(n_params == get_method_n_params(type));
1752 /* construct arguments */
1755 in_req[in_arity] = arch_no_register_req;
1759 /* stack pointer input */
1760 /* construct an IncSP -> we have to always be sure that the stack is
1761 * aligned even if we don't push arguments on it */
1762 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1763 cconv->param_stack_size, 1);
1764 in_req[in_arity] = sp_reg->single_req;
1765 in[in_arity] = incsp;
1769 for (p = 0; p < n_params; ++p) {
1770 ir_node *value = get_Call_param(node, p);
1771 ir_node *new_value = be_transform_node(value);
1772 const reg_or_stackslot_t *param = &cconv->parameters[p];
1773 ir_type *param_type = get_method_param_type(type, p);
1774 ir_mode *mode = get_type_mode(param_type);
1775 ir_node *new_values[2];
1779 if (mode_is_float(mode) && param->reg0 != NULL) {
1780 unsigned size_bits = get_mode_size_bits(mode);
1781 assert(size_bits <= 64);
1782 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1784 new_values[0] = new_value;
1785 new_values[1] = NULL;
1788 /* put value into registers */
1789 if (param->reg0 != NULL) {
1790 in[in_arity] = new_values[0];
1791 in_req[in_arity] = param->reg0->single_req;
1793 if (new_values[1] == NULL)
1796 if (param->reg1 != NULL) {
1797 assert(new_values[1] != NULL);
1798 in[in_arity] = new_values[1];
1799 in_req[in_arity] = param->reg1->single_req;
1804 /* we need a store if we're here */
1805 if (new_values[1] != NULL) {
1806 new_value = new_values[1];
1810 /* we need to skip over our save area when constructing the call
1811 * arguments on stack */
1812 offset = param->offset + SPARC_MIN_STACKSIZE;
1814 if (mode_is_float(mode)) {
1815 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1816 mode, NULL, offset, true);
1818 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1819 new_mem, mode, NULL, offset, true);
1821 set_irn_pinned(str, op_pin_state_floats);
1822 sync_ins[sync_arity++] = str;
1825 /* construct memory input */
1826 if (sync_arity == 0) {
1827 in[mem_pos] = new_mem;
1828 } else if (sync_arity == 1) {
1829 in[mem_pos] = sync_ins[0];
1831 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1834 if (is_SymConst(callee)) {
1835 entity = get_SymConst_entity(callee);
1837 in[in_arity] = be_transform_node(callee);
1838 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1841 assert(in_arity <= (int)max_inputs);
1848 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1850 /* create call node */
1851 if (entity != NULL) {
1852 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1853 entity, 0, aggregate_return);
1855 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1858 arch_set_irn_register_reqs_in(res, in_req);
1860 /* create output register reqs */
1862 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1863 /* add register requirements for the result regs */
1864 for (r = 0; r < n_ress; ++r) {
1865 const reg_or_stackslot_t *result_info = &cconv->results[r];
1866 const arch_register_req_t *req = result_info->req0;
1868 arch_set_irn_register_req_out(res, o++, req);
1870 assert(result_info->req1 == NULL);
1872 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1873 const arch_register_t *reg;
1874 if (!rbitset_is_set(cconv->caller_saves, i))
1876 reg = &sparc_registers[i];
1877 arch_set_irn_register_req_out(res, o++, reg->single_req);
1879 assert(o == out_arity);
1881 /* copy pinned attribute */
1882 set_irn_pinned(res, get_irn_pinned(node));
1884 /* IncSP to destroy the call stackframe */
1885 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1886 /* if we are the last IncSP producer in a block then we have to keep
1888 * Note: This here keeps all producers which is more than necessary */
1889 add_irn_dep(incsp, res);
1892 pmap_insert(node_to_stack, node, incsp);
1894 sparc_free_calling_convention(cconv);
1898 static ir_node *gen_Sel(ir_node *node)
1900 dbg_info *dbgi = get_irn_dbg_info(node);
1901 ir_node *block = get_nodes_block(node);
1902 ir_node *new_block = be_transform_node(block);
1903 ir_node *ptr = get_Sel_ptr(node);
1904 ir_node *new_ptr = be_transform_node(ptr);
1905 ir_entity *entity = get_Sel_entity(node);
1907 /* must be the frame pointer all other sels must have been lowered
1909 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1911 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1914 static ir_node *gen_Alloc(ir_node *node)
1916 dbg_info *dbgi = get_irn_dbg_info(node);
1917 ir_node *block = get_nodes_block(node);
1918 ir_node *new_block = be_transform_node(block);
1919 ir_type *type = get_Alloc_type(node);
1920 ir_node *size = get_Alloc_count(node);
1921 ir_node *stack_pred = get_stack_pointer_for(node);
1923 if (get_Alloc_where(node) != stack_alloc)
1924 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1925 /* lowerer should have transformed all allocas to byte size */
1926 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1927 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1929 if (is_Const(size)) {
1930 ir_tarval *tv = get_Const_tarval(size);
1931 long sizel = get_tarval_long(tv);
1932 subsp = be_new_IncSP(sp_reg, new_block, stack_pred, sizel, 0);
1933 set_irn_dbg_info(subsp, dbgi);
1935 ir_node *new_size = be_transform_node(size);
1936 subsp = new_bd_sparc_SubSP(dbgi, new_block, stack_pred, new_size);
1937 arch_set_irn_register(subsp, sp_reg);
1940 /* if we are the last IncSP producer in a block then we have to keep
1942 * Note: This here keeps all producers which is more than necessary */
1945 pmap_insert(node_to_stack, node, subsp);
1946 /* the "result" is the unmodified sp value */
1950 static ir_node *gen_Proj_Alloc(ir_node *node)
1952 ir_node *alloc = get_Proj_pred(node);
1953 long pn = get_Proj_proj(node);
1955 switch ((pn_Alloc)pn) {
1957 ir_node *alloc_mem = get_Alloc_mem(alloc);
1958 return be_transform_node(alloc_mem);
1960 case pn_Alloc_res: {
1961 ir_node *new_alloc = be_transform_node(alloc);
1964 case pn_Alloc_X_regular:
1965 case pn_Alloc_X_except:
1966 panic("sparc backend: exception output of alloc not supported (at %+F)",
1969 panic("sparc backend: invalid Proj->Alloc");
1972 static ir_node *gen_Free(ir_node *node)
1974 dbg_info *dbgi = get_irn_dbg_info(node);
1975 ir_node *block = get_nodes_block(node);
1976 ir_node *new_block = be_transform_node(block);
1977 ir_type *type = get_Free_type(node);
1978 ir_node *size = get_Free_count(node);
1979 ir_node *mem = get_Free_mem(node);
1980 ir_node *new_mem = be_transform_node(mem);
1981 ir_node *stack_pred = get_stack_pointer_for(node);
1983 if (get_Alloc_where(node) != stack_alloc)
1984 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1985 /* lowerer should have transformed all allocas to byte size */
1986 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1987 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1989 if (is_Const(size)) {
1990 ir_tarval *tv = get_Const_tarval(size);
1991 long sizel = get_tarval_long(tv);
1992 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
1993 set_irn_dbg_info(addsp, dbgi);
1995 ir_node *new_size = be_transform_node(size);
1996 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
1997 arch_set_irn_register(addsp, sp_reg);
2000 /* if we are the last IncSP producer in a block then we have to keep
2002 * Note: This here keeps all producers which is more than necessary */
2005 pmap_insert(node_to_stack, node, addsp);
2006 /* the "result" is the unmodified sp value */
2010 static const arch_register_req_t float1_req = {
2011 arch_register_req_type_normal,
2012 &sparc_reg_classes[CLASS_sparc_fp],
2018 static const arch_register_req_t float2_req = {
2019 arch_register_req_type_normal | arch_register_req_type_aligned,
2020 &sparc_reg_classes[CLASS_sparc_fp],
2026 static const arch_register_req_t float4_req = {
2027 arch_register_req_type_normal | arch_register_req_type_aligned,
2028 &sparc_reg_classes[CLASS_sparc_fp],
2036 static const arch_register_req_t *get_float_req(ir_mode *mode)
2038 unsigned bits = get_mode_size_bits(mode);
2040 assert(mode_is_float(mode));
2043 } else if (bits == 64) {
2046 assert(bits == 128);
2052 * Transform some Phi nodes
2054 static ir_node *gen_Phi(ir_node *node)
2056 const arch_register_req_t *req;
2057 ir_node *block = be_transform_node(get_nodes_block(node));
2058 ir_graph *irg = current_ir_graph;
2059 dbg_info *dbgi = get_irn_dbg_info(node);
2060 ir_mode *mode = get_irn_mode(node);
2063 if (mode_needs_gp_reg(mode)) {
2064 /* we shouldn't have any 64bit stuff around anymore */
2065 assert(get_mode_size_bits(mode) <= 32);
2066 /* all integer operations are on 32bit registers now */
2068 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2069 } else if (mode_is_float(mode)) {
2071 req = get_float_req(mode);
2073 req = arch_no_register_req;
2076 /* phi nodes allow loops, so we use the old arguments for now
2077 * and fix this later */
2078 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2079 copy_node_attr(irg, node, phi);
2080 be_duplicate_deps(node, phi);
2081 arch_set_irn_register_req_out(phi, 0, req);
2082 be_enqueue_preds(node);
2087 * Transform a Proj from a Load.
2089 static ir_node *gen_Proj_Load(ir_node *node)
2091 ir_node *load = get_Proj_pred(node);
2092 ir_node *new_load = be_transform_node(load);
2093 dbg_info *dbgi = get_irn_dbg_info(node);
2094 long pn = get_Proj_proj(node);
2096 /* renumber the proj */
2097 switch (get_sparc_irn_opcode(new_load)) {
2099 /* handle all gp loads equal: they have the same proj numbers. */
2100 if (pn == pn_Load_res) {
2101 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2102 } else if (pn == pn_Load_M) {
2103 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2107 if (pn == pn_Load_res) {
2108 const sparc_load_store_attr_t *attr
2109 = get_sparc_load_store_attr_const(new_load);
2110 ir_mode *mode = attr->load_store_mode;
2111 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2112 } else if (pn == pn_Load_M) {
2113 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2119 panic("Unsupported Proj from Load");
2122 static ir_node *gen_Proj_Store(ir_node *node)
2124 ir_node *store = get_Proj_pred(node);
2125 ir_node *new_store = be_transform_node(store);
2126 long pn = get_Proj_proj(node);
2128 /* renumber the proj */
2129 switch (get_sparc_irn_opcode(new_store)) {
2131 if (pn == pn_Store_M) {
2136 if (pn == pn_Store_M) {
2143 panic("Unsupported Proj from Store");
2147 * Transform the Projs from a Cmp.
2149 static ir_node *gen_Proj_Cmp(ir_node *node)
2152 panic("not implemented");
2156 * transform Projs from a Div
2158 static ir_node *gen_Proj_Div(ir_node *node)
2160 ir_node *pred = get_Proj_pred(node);
2161 ir_node *new_pred = be_transform_node(pred);
2162 long pn = get_Proj_proj(node);
2165 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2167 } else if (is_sparc_fdiv(new_pred)) {
2168 res_mode = get_Div_resmode(pred);
2170 panic("sparc backend: Div transformed to something unexpected: %+F",
2173 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2174 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2175 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2176 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2179 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2181 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
2185 panic("Unsupported Proj from Div");
2188 static ir_node *get_frame_base(ir_graph *irg)
2190 if (frame_base == NULL) {
2191 if (current_cconv->omit_fp) {
2192 frame_base = get_initial_sp(irg);
2194 frame_base = get_initial_fp(irg);
2200 static ir_node *gen_Proj_Start(ir_node *node)
2202 ir_node *block = get_nodes_block(node);
2203 ir_node *new_block = be_transform_node(block);
2204 long pn = get_Proj_proj(node);
2205 /* make sure prolog is constructed */
2206 be_transform_node(get_Proj_pred(node));
2208 switch ((pn_Start) pn) {
2209 case pn_Start_X_initial_exec:
2210 /* exchange ProjX with a jump */
2211 return new_bd_sparc_Ba(NULL, new_block);
2213 ir_graph *irg = get_irn_irg(node);
2214 return get_initial_mem(irg);
2216 case pn_Start_T_args:
2217 return new_r_Bad(get_irn_irg(block), mode_T);
2218 case pn_Start_P_frame_base:
2219 return get_frame_base(get_irn_irg(block));
2221 panic("Unexpected start proj: %ld\n", pn);
2224 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2226 long pn = get_Proj_proj(node);
2227 ir_node *block = get_nodes_block(node);
2228 ir_graph *irg = get_irn_irg(node);
2229 ir_node *new_block = be_transform_node(block);
2230 ir_node *args = get_Proj_pred(node);
2231 ir_node *start = get_Proj_pred(args);
2232 ir_node *new_start = be_transform_node(start);
2233 const reg_or_stackslot_t *param;
2235 /* Proj->Proj->Start must be a method argument */
2236 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2238 param = ¤t_cconv->parameters[pn];
2240 if (param->reg0 != NULL) {
2241 /* argument transmitted in register */
2242 const arch_register_t *reg = param->reg0;
2243 ir_mode *reg_mode = reg->reg_class->mode;
2244 long new_pn = param->reg_offset + start_params_offset;
2245 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2246 bool is_float = false;
2249 ir_entity *entity = get_irg_entity(irg);
2250 ir_type *method_type = get_entity_type(entity);
2251 if (pn < (long)get_method_n_params(method_type)) {
2252 ir_type *param_type = get_method_param_type(method_type, pn);
2253 ir_mode *mode = get_type_mode(param_type);
2254 is_float = mode_is_float(mode);
2259 const arch_register_t *reg1 = param->reg1;
2260 ir_node *value1 = NULL;
2263 ir_mode *reg1_mode = reg1->reg_class->mode;
2264 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2265 } else if (param->entity != NULL) {
2266 ir_node *fp = get_initial_fp(irg);
2267 ir_node *mem = get_initial_mem(irg);
2268 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2269 mode_gp, param->entity,
2271 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2274 /* convert integer value to float */
2275 value = bitcast_int_to_float(NULL, new_block, value, value1);
2279 /* argument transmitted on stack */
2280 ir_node *mem = get_initial_mem(irg);
2281 ir_mode *mode = get_type_mode(param->type);
2282 ir_node *base = get_frame_base(irg);
2286 if (mode_is_float(mode)) {
2287 load = create_ldf(NULL, new_block, base, mem, mode,
2288 param->entity, 0, true);
2289 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2291 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2292 param->entity, 0, true);
2293 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2295 set_irn_pinned(load, op_pin_state_floats);
2301 static ir_node *gen_Proj_Call(ir_node *node)
2303 long pn = get_Proj_proj(node);
2304 ir_node *call = get_Proj_pred(node);
2305 ir_node *new_call = be_transform_node(call);
2307 switch ((pn_Call) pn) {
2309 return new_r_Proj(new_call, mode_M, 0);
2310 case pn_Call_X_regular:
2311 case pn_Call_X_except:
2312 case pn_Call_T_result:
2315 panic("Unexpected Call proj %ld\n", pn);
2318 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2320 long pn = get_Proj_proj(node);
2321 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2322 ir_node *new_call = be_transform_node(call);
2323 ir_type *function_type = get_Call_type(call);
2324 calling_convention_t *cconv
2325 = sparc_decide_calling_convention(function_type, NULL);
2326 const reg_or_stackslot_t *res = &cconv->results[pn];
2327 ir_mode *mode = get_irn_mode(node);
2328 long new_pn = 1 + res->reg_offset;
2330 assert(res->req0 != NULL && res->req1 == NULL);
2331 if (mode_needs_gp_reg(mode)) {
2334 sparc_free_calling_convention(cconv);
2336 return new_r_Proj(new_call, mode, new_pn);
2340 * Transform a Proj node.
2342 static ir_node *gen_Proj(ir_node *node)
2344 ir_node *pred = get_Proj_pred(node);
2346 switch (get_irn_opcode(pred)) {
2348 return gen_Proj_Alloc(node);
2350 return gen_Proj_Store(node);
2352 return gen_Proj_Load(node);
2354 return gen_Proj_Call(node);
2356 return gen_Proj_Cmp(node);
2358 return be_duplicate_node(node);
2360 return gen_Proj_Div(node);
2362 return gen_Proj_Start(node);
2364 ir_node *pred_pred = get_Proj_pred(pred);
2365 if (is_Call(pred_pred)) {
2366 return gen_Proj_Proj_Call(node);
2367 } else if (is_Start(pred_pred)) {
2368 return gen_Proj_Proj_Start(node);
2373 if (is_sparc_AddCC_t(pred)) {
2374 return gen_Proj_AddCC_t(node);
2375 } else if (is_sparc_SubCC_t(pred)) {
2376 return gen_Proj_SubCC_t(node);
2378 panic("code selection didn't expect Proj after %+F\n", pred);
2385 static ir_node *gen_Jmp(ir_node *node)
2387 ir_node *block = get_nodes_block(node);
2388 ir_node *new_block = be_transform_node(block);
2389 dbg_info *dbgi = get_irn_dbg_info(node);
2391 return new_bd_sparc_Ba(dbgi, new_block);
2395 * configure transformation callbacks
2397 static void sparc_register_transformers(void)
2399 be_start_transform_setup();
2401 be_set_transform_function(op_Add, gen_Add);
2402 be_set_transform_function(op_Alloc, gen_Alloc);
2403 be_set_transform_function(op_And, gen_And);
2404 be_set_transform_function(op_Call, gen_Call);
2405 be_set_transform_function(op_Cmp, gen_Cmp);
2406 be_set_transform_function(op_Cond, gen_Cond);
2407 be_set_transform_function(op_Const, gen_Const);
2408 be_set_transform_function(op_Conv, gen_Conv);
2409 be_set_transform_function(op_Div, gen_Div);
2410 be_set_transform_function(op_Eor, gen_Eor);
2411 be_set_transform_function(op_Free, gen_Free);
2412 be_set_transform_function(op_Jmp, gen_Jmp);
2413 be_set_transform_function(op_Load, gen_Load);
2414 be_set_transform_function(op_Minus, gen_Minus);
2415 be_set_transform_function(op_Mul, gen_Mul);
2416 be_set_transform_function(op_Mulh, gen_Mulh);
2417 be_set_transform_function(op_Not, gen_Not);
2418 be_set_transform_function(op_Or, gen_Or);
2419 be_set_transform_function(op_Phi, gen_Phi);
2420 be_set_transform_function(op_Proj, gen_Proj);
2421 be_set_transform_function(op_Return, gen_Return);
2422 be_set_transform_function(op_Sel, gen_Sel);
2423 be_set_transform_function(op_Shl, gen_Shl);
2424 be_set_transform_function(op_Shr, gen_Shr);
2425 be_set_transform_function(op_Shrs, gen_Shrs);
2426 be_set_transform_function(op_Start, gen_Start);
2427 be_set_transform_function(op_Store, gen_Store);
2428 be_set_transform_function(op_Sub, gen_Sub);
2429 be_set_transform_function(op_SymConst, gen_SymConst);
2430 be_set_transform_function(op_Unknown, gen_Unknown);
2432 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2433 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2434 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2435 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2436 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2440 * Transform a Firm graph into a SPARC graph.
2442 void sparc_transform_graph(ir_graph *irg)
2444 ir_entity *entity = get_irg_entity(irg);
2445 ir_type *frame_type;
2447 sparc_register_transformers();
2449 node_to_stack = pmap_create();
2454 mode_flags = mode_Bu;
2464 stackorder = be_collect_stacknodes(irg);
2466 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2467 if (sparc_variadic_fixups(irg, current_cconv)) {
2468 sparc_free_calling_convention(current_cconv);
2470 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2472 sparc_create_stacklayout(irg, current_cconv);
2473 be_add_parameter_entity_stores(irg);
2475 be_transform_graph(irg, NULL);
2477 be_free_stackorder(stackorder);
2478 sparc_free_calling_convention(current_cconv);
2480 frame_type = get_irg_frame_type(irg);
2481 if (get_type_state(frame_type) == layout_undefined)
2482 default_layout_compound_type(frame_type);
2484 pmap_destroy(node_to_stack);
2485 node_to_stack = NULL;
2487 be_add_missing_keeps(irg);
2489 /* do code placement, to optimize the position of constants */
2493 void sparc_init_transform(void)
2495 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");