2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
31 #include "irgraph_t.h"
37 #include "iroptimize.h"
47 #include "betranshlp.h"
48 #include "beabihelper.h"
49 #include "bearch_sparc_t.h"
51 #include "sparc_nodes_attr.h"
52 #include "sparc_transform.h"
53 #include "sparc_new_nodes.h"
54 #include "gen_sparc_new_nodes.h"
56 #include "gen_sparc_regalloc_if.h"
57 #include "sparc_cconv.h"
61 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
63 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
64 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
65 static calling_convention_t *current_cconv = NULL;
66 static be_stackorder_t *stackorder;
67 static ir_mode *mode_gp;
68 static ir_mode *mode_flags;
69 static ir_mode *mode_fp;
70 static ir_mode *mode_fp2;
71 //static ir_mode *mode_fp4;
72 static pmap *node_to_stack;
73 static size_t start_mem_offset;
74 static ir_node *start_mem;
75 static size_t start_g0_offset;
76 static ir_node *start_g0;
77 static size_t start_g7_offset;
78 static ir_node *start_g7;
79 static size_t start_sp_offset;
80 static ir_node *start_sp;
81 static size_t start_fp_offset;
82 static ir_node *start_fp;
83 static ir_node *frame_base;
84 static size_t start_params_offset;
85 static size_t start_callee_saves_offset;
87 static const arch_register_t *const omit_fp_callee_saves[] = {
88 &sparc_registers[REG_L0],
89 &sparc_registers[REG_L1],
90 &sparc_registers[REG_L2],
91 &sparc_registers[REG_L3],
92 &sparc_registers[REG_L4],
93 &sparc_registers[REG_L5],
94 &sparc_registers[REG_L6],
95 &sparc_registers[REG_L7],
96 &sparc_registers[REG_I0],
97 &sparc_registers[REG_I1],
98 &sparc_registers[REG_I2],
99 &sparc_registers[REG_I3],
100 &sparc_registers[REG_I4],
101 &sparc_registers[REG_I5],
104 static inline bool mode_needs_gp_reg(ir_mode *mode)
106 if (mode_is_int(mode) || mode_is_reference(mode)) {
107 /* we should only see 32bit code */
108 assert(get_mode_size_bits(mode) <= 32);
115 * Create an And that will zero out upper bits.
117 * @param dbgi debug info
118 * @param block the basic block
119 * @param op the original node
120 * @param src_bits number of lower bits that will remain
122 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
126 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
127 } else if (src_bits == 16) {
128 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
129 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
132 panic("zero extension only supported for 8 and 16 bits");
137 * Generate code for a sign extension.
139 * @param dbgi debug info
140 * @param block the basic block
141 * @param op the original node
142 * @param src_bits number of lower bits that will remain
144 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
147 int shift_width = 32 - src_bits;
148 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
149 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
154 * returns true if it is assured, that the upper bits of a node are "clean"
155 * which means for a 16 or 8 bit value, that the upper bits in the register
156 * are 0 for unsigned and a copy of the last significant bit for signed
159 static bool upper_bits_clean(ir_node *node, ir_mode *mode)
161 switch ((ir_opcode)get_irn_opcode(node)) {
163 if (!mode_is_signed(mode)) {
164 return upper_bits_clean(get_And_left(node), mode)
165 || upper_bits_clean(get_And_right(node), mode);
170 return upper_bits_clean(get_binop_left(node), mode)
171 && upper_bits_clean(get_binop_right(node), mode);
174 if (mode_is_signed(mode)) {
175 return false; /* TODO */
177 ir_node *right = get_Shr_right(node);
178 if (is_Const(right)) {
179 ir_tarval *tv = get_Const_tarval(right);
180 long val = get_tarval_long(tv);
181 if (val >= 32 - (long)get_mode_size_bits(mode))
184 return upper_bits_clean(get_Shr_left(node), mode);
188 return upper_bits_clean(get_Shrs_left(node), mode);
191 ir_tarval *tv = get_Const_tarval(node);
192 long val = get_tarval_long(tv);
193 if (mode_is_signed(mode)) {
194 long shifted = val >> (get_mode_size_bits(mode)-1);
195 return shifted == 0 || shifted == -1;
197 unsigned long shifted = (unsigned long)val;
198 shifted >>= get_mode_size_bits(mode)-1;
205 ir_mode *dest_mode = get_irn_mode(node);
206 ir_node *op = get_Conv_op(node);
207 ir_mode *src_mode = get_irn_mode(op);
208 unsigned src_bits = get_mode_size_bits(src_mode);
209 unsigned dest_bits = get_mode_size_bits(dest_mode);
210 /* downconvs are a nop */
211 if (src_bits <= dest_bits)
212 return upper_bits_clean(op, mode);
213 if (dest_bits <= get_mode_size_bits(mode)
214 && mode_is_signed(dest_mode) == mode_is_signed(mode))
220 ir_node *pred = get_Proj_pred(node);
221 switch (get_irn_opcode(pred)) {
223 ir_mode *load_mode = get_Load_mode(pred);
224 unsigned load_bits = get_mode_size_bits(load_mode);
225 unsigned bits = get_mode_size_bits(mode);
226 if (load_bits > bits)
228 if (mode_is_signed(mode) != mode_is_signed(load_mode))
243 * Extend a value to 32 bit signed/unsigned depending on its mode.
245 * @param dbgi debug info
246 * @param block the basic block
247 * @param op the original node
248 * @param orig_mode the original mode of op
250 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
253 int bits = get_mode_size_bits(orig_mode);
256 if (mode_is_signed(orig_mode)) {
257 return gen_sign_extension(dbgi, block, op, bits);
259 return gen_zero_extension(dbgi, block, op, bits);
265 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
266 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
267 influence the significant lower bit at
268 all (for cases where mode < 32bit) */
270 ENUM_BITSET(match_flags_t)
272 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
273 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
274 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
275 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
278 * checks if a node's value can be encoded as a immediate
280 static bool is_imm_encodeable(const ir_node *node)
286 value = get_tarval_long(get_Const_tarval(node));
287 return sparc_is_value_imm_encodeable(value);
290 static bool needs_extension(ir_node *op)
292 ir_mode *mode = get_irn_mode(op);
293 if (get_mode_size_bits(mode) >= get_mode_size_bits(mode_gp))
295 return !upper_bits_clean(op, mode);
299 * Check, if a given node is a Down-Conv, ie. a integer Conv
300 * from a mode with a mode with more bits to a mode with lesser bits.
301 * Moreover, we return only true if the node has not more than 1 user.
303 * @param node the node
304 * @return non-zero if node is a Down-Conv
306 static bool is_downconv(const ir_node *node)
314 src_mode = get_irn_mode(get_Conv_op(node));
315 dest_mode = get_irn_mode(node);
317 mode_needs_gp_reg(src_mode) &&
318 mode_needs_gp_reg(dest_mode) &&
319 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
322 static ir_node *skip_downconv(ir_node *node)
324 while (is_downconv(node)) {
325 node = get_Conv_op(node);
331 * helper function for binop operations
333 * @param new_reg register generation function ptr
334 * @param new_imm immediate generation function ptr
336 static ir_node *gen_helper_binop_args(ir_node *node,
337 ir_node *op1, ir_node *op2,
339 new_binop_reg_func new_reg,
340 new_binop_imm_func new_imm)
342 dbg_info *dbgi = get_irn_dbg_info(node);
343 ir_node *block = be_transform_node(get_nodes_block(node));
349 if (flags & MATCH_MODE_NEUTRAL) {
350 op1 = skip_downconv(op1);
351 op2 = skip_downconv(op2);
353 mode1 = get_irn_mode(op1);
354 mode2 = get_irn_mode(op2);
355 /* we shouldn't see 64bit code */
356 assert(get_mode_size_bits(mode1) <= 32);
357 assert(get_mode_size_bits(mode2) <= 32);
359 if (is_imm_encodeable(op2)) {
360 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
361 new_op1 = be_transform_node(op1);
362 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
363 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
365 return new_imm(dbgi, block, new_op1, NULL, immediate);
367 new_op2 = be_transform_node(op2);
368 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op2)) {
369 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
372 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
373 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
374 return new_imm(dbgi, block, new_op2, NULL, immediate);
377 new_op1 = be_transform_node(op1);
378 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
379 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
381 return new_reg(dbgi, block, new_op1, new_op2);
384 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
385 new_binop_reg_func new_reg,
386 new_binop_imm_func new_imm)
388 ir_node *op1 = get_binop_left(node);
389 ir_node *op2 = get_binop_right(node);
390 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
394 * helper function for FP binop operations
396 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
397 new_binop_fp_func new_func_single,
398 new_binop_fp_func new_func_double,
399 new_binop_fp_func new_func_quad)
401 ir_node *block = be_transform_node(get_nodes_block(node));
402 ir_node *op1 = get_binop_left(node);
403 ir_node *new_op1 = be_transform_node(op1);
404 ir_node *op2 = get_binop_right(node);
405 ir_node *new_op2 = be_transform_node(op2);
406 dbg_info *dbgi = get_irn_dbg_info(node);
407 unsigned bits = get_mode_size_bits(mode);
411 return new_func_single(dbgi, block, new_op1, new_op2, mode);
413 return new_func_double(dbgi, block, new_op1, new_op2, mode);
415 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
419 panic("unsupported mode %+F for float op", mode);
422 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
423 new_unop_fp_func new_func_single,
424 new_unop_fp_func new_func_double,
425 new_unop_fp_func new_func_quad)
427 ir_node *block = be_transform_node(get_nodes_block(node));
428 ir_node *op = get_unop_op(node);
429 ir_node *new_op = be_transform_node(op);
430 dbg_info *dbgi = get_irn_dbg_info(node);
431 unsigned bits = get_mode_size_bits(mode);
435 return new_func_single(dbgi, block, new_op, mode);
437 return new_func_double(dbgi, block, new_op, mode);
439 return new_func_quad(dbgi, block, new_op, mode);
443 panic("unsupported mode %+F for float op", mode);
446 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
447 ir_node *op1, ir_node *flags,
448 ir_entity *imm_entity, int32_t imm);
450 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
451 ir_node *op1, ir_node *op2,
454 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
455 new_binopx_reg_func new_binopx_reg,
456 new_binopx_imm_func new_binopx_imm)
458 dbg_info *dbgi = get_irn_dbg_info(node);
459 ir_node *block = be_transform_node(get_nodes_block(node));
460 ir_node *op1 = get_irn_n(node, 0);
461 ir_node *op2 = get_irn_n(node, 1);
462 ir_node *flags = get_irn_n(node, 2);
463 ir_node *new_flags = be_transform_node(flags);
467 /* only support for mode-neutral implemented so far */
468 assert(match_flags & MATCH_MODE_NEUTRAL);
470 if (is_imm_encodeable(op2)) {
471 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
472 new_op1 = be_transform_node(op1);
473 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
475 new_op2 = be_transform_node(op2);
476 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
477 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
478 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
480 new_op1 = be_transform_node(op1);
481 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
485 static ir_node *get_g0(ir_graph *irg)
487 if (start_g0 == NULL) {
488 /* this is already the transformed start node */
489 ir_node *start = get_irg_start(irg);
490 assert(is_sparc_Start(start));
491 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
496 static ir_node *get_g7(ir_graph *irg)
498 if (start_g7 == NULL) {
499 ir_node *start = get_irg_start(irg);
500 assert(is_sparc_Start(start));
501 start_g7 = new_r_Proj(start, mode_gp, start_g7_offset);
506 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
507 ir_entity *entity, int32_t offset)
509 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
510 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
514 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
517 if (get_entity_owner(entity) == get_tls_type()) {
518 ir_graph *irg = get_irn_irg(block);
519 ir_node *g7 = get_g7(irg);
520 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
521 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
524 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
525 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
530 typedef struct address_t {
538 * Match a load/store address
540 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
543 ir_node *ptr2 = NULL;
545 ir_entity *entity = NULL;
548 ir_node *add_right = get_Add_right(base);
549 if (is_Const(add_right)) {
550 base = get_Add_left(base);
551 offset += get_tarval_long(get_Const_tarval(add_right));
554 /* Note that we don't match sub(x, Const) or chains of adds/subs
555 * because this should all be normalized by now */
557 /* we only use the symconst if we're the only user otherwise we probably
558 * won't save anything but produce multiple sethi+or combinations with
559 * just different offsets */
560 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
561 ir_entity *sc_entity = get_SymConst_entity(base);
562 dbg_info *dbgi = get_irn_dbg_info(ptr);
563 ir_node *block = get_nodes_block(ptr);
564 ir_node *new_block = be_transform_node(block);
566 if (get_entity_owner(sc_entity) == get_tls_type()) {
570 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
572 base = get_g7(get_irn_irg(base));
576 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
578 } else if (use_ptr2 && is_Add(base) && offset == 0) {
579 ptr2 = be_transform_node(get_Add_right(base));
580 base = be_transform_node(get_Add_left(base));
583 if (sparc_is_value_imm_encodeable(offset)) {
584 base = be_transform_node(base);
586 base = be_transform_node(ptr);
592 address->ptr2 = ptr2;
593 address->entity = entity;
594 address->offset = offset;
598 * Creates an sparc Add.
600 * @param node FIRM node
601 * @return the created sparc Add node
603 static ir_node *gen_Add(ir_node *node)
605 ir_mode *mode = get_irn_mode(node);
608 if (mode_is_float(mode)) {
609 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
610 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
613 /* special case: + 0x1000 can be represented as - 0x1000 */
614 right = get_Add_right(node);
615 if (is_Const(right)) {
616 ir_node *left = get_Add_left(node);
619 /* is this simple address arithmetic? then we can let the linker do
620 * the calculation. */
621 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_node *block = be_transform_node(get_nodes_block(node));
626 /* the value of use_ptr2 shouldn't matter here */
627 match_address(node, &address, false);
628 assert(is_sparc_SetHi(address.ptr));
629 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
630 address.entity, address.offset);
633 tv = get_Const_tarval(right);
634 val = get_tarval_long(tv);
636 dbg_info *dbgi = get_irn_dbg_info(node);
637 ir_node *block = be_transform_node(get_nodes_block(node));
638 ir_node *op = get_Add_left(node);
639 ir_node *new_op = be_transform_node(op);
640 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
644 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
645 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
648 static ir_node *gen_AddCC_t(ir_node *node)
650 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
651 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
654 static ir_node *gen_Proj_AddCC_t(ir_node *node)
656 long pn = get_Proj_proj(node);
657 ir_node *pred = get_Proj_pred(node);
658 ir_node *new_pred = be_transform_node(pred);
661 case pn_sparc_AddCC_t_res:
662 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
663 case pn_sparc_AddCC_t_flags:
664 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
666 panic("Invalid AddCC_t proj found");
670 static ir_node *gen_AddX_t(ir_node *node)
672 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
673 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
677 * Creates an sparc Sub.
679 * @param node FIRM node
680 * @return the created sparc Sub node
682 static ir_node *gen_Sub(ir_node *node)
684 ir_mode *mode = get_irn_mode(node);
686 if (mode_is_float(mode)) {
687 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
688 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
691 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
692 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
695 static ir_node *gen_SubCC_t(ir_node *node)
697 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
698 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
701 static ir_node *gen_Proj_SubCC_t(ir_node *node)
703 long pn = get_Proj_proj(node);
704 ir_node *pred = get_Proj_pred(node);
705 ir_node *new_pred = be_transform_node(pred);
708 case pn_sparc_SubCC_t_res:
709 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
710 case pn_sparc_SubCC_t_flags:
711 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
713 panic("Invalid SubCC_t proj found");
717 static ir_node *gen_SubX_t(ir_node *node)
719 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
720 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
723 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
724 ir_node *mem, ir_mode *mode, ir_entity *entity,
725 long offset, bool is_frame_entity)
727 unsigned bits = get_mode_size_bits(mode);
728 assert(mode_is_float(mode));
730 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
731 offset, is_frame_entity);
732 } else if (bits == 64) {
733 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
734 offset, is_frame_entity);
737 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
738 offset, is_frame_entity);
742 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
743 ir_node *ptr, ir_node *mem, ir_mode *mode,
744 ir_entity *entity, long offset,
745 bool is_frame_entity)
747 unsigned bits = get_mode_size_bits(mode);
748 assert(mode_is_float(mode));
750 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
751 offset, is_frame_entity);
752 } else if (bits == 64) {
753 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
754 offset, is_frame_entity);
757 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
758 offset, is_frame_entity);
765 * @param node the ir Load node
766 * @return the created sparc Load node
768 static ir_node *gen_Load(ir_node *node)
770 dbg_info *dbgi = get_irn_dbg_info(node);
771 ir_mode *mode = get_Load_mode(node);
772 ir_node *block = be_transform_node(get_nodes_block(node));
773 ir_node *ptr = get_Load_ptr(node);
774 ir_node *mem = get_Load_mem(node);
775 ir_node *new_mem = be_transform_node(mem);
776 ir_node *new_load = NULL;
779 if (get_Load_unaligned(node) == align_non_aligned) {
780 panic("sparc: transformation of unaligned Loads not implemented yet");
783 if (mode_is_float(mode)) {
784 match_address(ptr, &address, false);
785 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
786 address.entity, address.offset, false);
788 match_address(ptr, &address, true);
789 if (address.ptr2 != NULL) {
790 assert(address.entity == NULL && address.offset == 0);
791 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
792 address.ptr2, new_mem, mode);
794 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
795 mode, address.entity, address.offset,
799 set_irn_pinned(new_load, get_irn_pinned(node));
805 * Transforms a Store.
807 * @param node the ir Store node
808 * @return the created sparc Store node
810 static ir_node *gen_Store(ir_node *node)
812 ir_node *block = be_transform_node(get_nodes_block(node));
813 ir_node *ptr = get_Store_ptr(node);
814 ir_node *mem = get_Store_mem(node);
815 ir_node *new_mem = be_transform_node(mem);
816 ir_node *val = get_Store_value(node);
817 ir_mode *mode = get_irn_mode(val);
818 dbg_info *dbgi = get_irn_dbg_info(node);
819 ir_node *new_store = NULL;
822 if (get_Store_unaligned(node) == align_non_aligned) {
823 panic("sparc: transformation of unaligned Stores not implemented yet");
826 if (mode_is_float(mode)) {
827 ir_node *new_val = be_transform_node(val);
828 /* TODO: variants with reg+reg address mode */
829 match_address(ptr, &address, false);
830 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
831 mode, address.entity, address.offset, false);
834 unsigned dest_bits = get_mode_size_bits(mode);
835 while (is_downconv(node)
836 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
837 val = get_Conv_op(val);
839 new_val = be_transform_node(val);
841 assert(dest_bits <= 32);
842 match_address(ptr, &address, true);
843 if (address.ptr2 != NULL) {
844 assert(address.entity == NULL && address.offset == 0);
845 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
846 address.ptr2, new_mem, mode);
848 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
849 new_mem, mode, address.entity,
850 address.offset, false);
853 set_irn_pinned(new_store, get_irn_pinned(node));
859 * Creates an sparc Mul.
860 * returns the lower 32bits of the 64bit multiply result
862 * @return the created sparc Mul node
864 static ir_node *gen_Mul(ir_node *node)
866 ir_mode *mode = get_irn_mode(node);
867 if (mode_is_float(mode)) {
868 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
869 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
872 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
873 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
877 * Creates an sparc Mulh.
878 * Mulh returns the upper 32bits of a mul instruction
880 * @return the created sparc Mulh node
882 static ir_node *gen_Mulh(ir_node *node)
884 ir_mode *mode = get_irn_mode(node);
887 if (mode_is_float(mode))
888 panic("FP not supported yet");
890 if (mode_is_signed(mode)) {
891 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
892 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
894 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
895 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
899 static ir_node *gen_sign_extension_value(ir_node *node)
901 ir_node *block = get_nodes_block(node);
902 ir_node *new_block = be_transform_node(block);
903 ir_node *new_node = be_transform_node(node);
904 /* TODO: we could do some shortcuts for some value types probably.
905 * (For constants or other cases where we know the sign bit in
907 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
911 * Creates an sparc Div.
913 * @return the created sparc Div node
915 static ir_node *gen_Div(ir_node *node)
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_node *block = get_nodes_block(node);
919 ir_node *new_block = be_transform_node(block);
920 ir_mode *mode = get_Div_resmode(node);
921 ir_node *left = get_Div_left(node);
922 ir_node *left_low = be_transform_node(left);
923 ir_node *right = get_Div_right(node);
926 if (mode_is_float(mode)) {
927 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
928 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
931 if (mode_is_signed(mode)) {
932 ir_node *left_high = gen_sign_extension_value(left);
934 if (is_imm_encodeable(right)) {
935 int32_t immediate = get_tarval_long(get_Const_tarval(right));
936 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
939 ir_node *new_right = be_transform_node(right);
940 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
944 ir_graph *irg = get_irn_irg(node);
945 ir_node *left_high = get_g0(irg);
946 if (is_imm_encodeable(right)) {
947 int32_t immediate = get_tarval_long(get_Const_tarval(right));
948 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
951 ir_node *new_right = be_transform_node(right);
952 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
961 * Transforms a Not node.
963 * @return the created sparc Not node
965 static ir_node *gen_Not(ir_node *node)
967 ir_node *op = get_Not_op(node);
968 ir_graph *irg = get_irn_irg(node);
969 ir_node *zero = get_g0(irg);
970 dbg_info *dbgi = get_irn_dbg_info(node);
971 ir_node *block = be_transform_node(get_nodes_block(node));
972 ir_node *new_op = be_transform_node(op);
974 /* Note: Not(Eor()) is normalize in firm localopts already so
975 * we don't match it for xnor here */
977 /* Not can be represented with xnor 0, n */
978 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
981 static ir_node *gen_helper_bitop(ir_node *node,
982 new_binop_reg_func new_reg,
983 new_binop_imm_func new_imm,
984 new_binop_reg_func new_not_reg,
985 new_binop_imm_func new_not_imm,
988 ir_node *op1 = get_binop_left(node);
989 ir_node *op2 = get_binop_right(node);
991 return gen_helper_binop_args(node, op2, get_Not_op(op1),
993 new_not_reg, new_not_imm);
996 return gen_helper_binop_args(node, op1, get_Not_op(op2),
998 new_not_reg, new_not_imm);
1000 if (is_Const(op2) && get_irn_n_edges(op2) == 1) {
1001 ir_tarval *tv = get_Const_tarval(op2);
1002 long value = get_tarval_long(tv);
1003 if (!sparc_is_value_imm_encodeable(value)) {
1004 long notvalue = ~value;
1005 if ((notvalue & 0x3ff) == 0) {
1006 ir_node *block = get_nodes_block(node);
1007 ir_node *new_block = be_transform_node(block);
1008 dbg_info *dbgi = get_irn_dbg_info(node);
1010 = new_bd_sparc_SetHi(NULL, new_block, NULL, notvalue);
1011 ir_node *new_op1 = be_transform_node(op1);
1013 = new_not_reg(dbgi, new_block, new_op1, new_op2);
1018 return gen_helper_binop_args(node, op1, op2,
1019 flags | MATCH_COMMUTATIVE,
1023 static ir_node *gen_And(ir_node *node)
1025 return gen_helper_bitop(node,
1026 new_bd_sparc_And_reg,
1027 new_bd_sparc_And_imm,
1028 new_bd_sparc_AndN_reg,
1029 new_bd_sparc_AndN_imm,
1030 MATCH_MODE_NEUTRAL);
1033 static ir_node *gen_Or(ir_node *node)
1035 return gen_helper_bitop(node,
1036 new_bd_sparc_Or_reg,
1037 new_bd_sparc_Or_imm,
1038 new_bd_sparc_OrN_reg,
1039 new_bd_sparc_OrN_imm,
1040 MATCH_MODE_NEUTRAL);
1043 static ir_node *gen_Eor(ir_node *node)
1045 return gen_helper_bitop(node,
1046 new_bd_sparc_Xor_reg,
1047 new_bd_sparc_Xor_imm,
1048 new_bd_sparc_XNor_reg,
1049 new_bd_sparc_XNor_imm,
1050 MATCH_MODE_NEUTRAL);
1053 static ir_node *gen_Shl(ir_node *node)
1055 ir_mode *mode = get_irn_mode(node);
1056 if (get_mode_modulo_shift(mode) != 32)
1057 panic("modulo_shift!=32 not supported by sparc backend");
1058 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
1061 static ir_node *gen_Shr(ir_node *node)
1063 ir_mode *mode = get_irn_mode(node);
1064 if (get_mode_modulo_shift(mode) != 32)
1065 panic("modulo_shift!=32 not supported by sparc backend");
1066 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
1069 static ir_node *gen_Shrs(ir_node *node)
1071 ir_mode *mode = get_irn_mode(node);
1072 if (get_mode_modulo_shift(mode) != 32)
1073 panic("modulo_shift!=32 not supported by sparc backend");
1074 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
1078 * Transforms a Minus node.
1080 static ir_node *gen_Minus(ir_node *node)
1082 ir_mode *mode = get_irn_mode(node);
1089 if (mode_is_float(mode)) {
1090 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
1091 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
1093 block = be_transform_node(get_nodes_block(node));
1094 dbgi = get_irn_dbg_info(node);
1095 op = get_Minus_op(node);
1096 new_op = be_transform_node(op);
1097 zero = get_g0(get_irn_irg(node));
1098 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1102 * Create an entity for a given (floating point) tarval
1104 static ir_entity *create_float_const_entity(ir_tarval *tv)
1106 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
1107 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1108 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
1109 ir_initializer_t *initializer;
1117 mode = get_tarval_mode(tv);
1118 type = get_type_for_mode(mode);
1119 glob = get_glob_type();
1120 entity = new_entity(glob, id_unique("C%u"), type);
1121 set_entity_visibility(entity, ir_visibility_private);
1122 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1124 initializer = create_initializer_tarval(tv);
1125 set_entity_initializer(entity, initializer);
1127 pmap_insert(isa->constants, tv, entity);
1131 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1133 ir_entity *entity = create_float_const_entity(tv);
1134 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1135 ir_node *mem = get_irg_no_mem(current_ir_graph);
1136 ir_mode *mode = get_tarval_mode(tv);
1138 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1139 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1141 set_irn_pinned(new_op, op_pin_state_floats);
1145 static ir_node *gen_Const(ir_node *node)
1147 ir_node *block = be_transform_node(get_nodes_block(node));
1148 ir_mode *mode = get_irn_mode(node);
1149 dbg_info *dbgi = get_irn_dbg_info(node);
1150 ir_tarval *tv = get_Const_tarval(node);
1153 if (mode_is_float(mode)) {
1154 return gen_float_const(dbgi, block, tv);
1157 value = get_tarval_long(tv);
1159 return get_g0(get_irn_irg(node));
1160 } else if (sparc_is_value_imm_encodeable(value)) {
1161 ir_graph *irg = get_irn_irg(node);
1162 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1164 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1165 if ((value & 0x3ff) != 0) {
1166 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1173 static ir_node *gen_Switch(ir_node *node)
1175 dbg_info *dbgi = get_irn_dbg_info(node);
1176 ir_node *block = get_nodes_block(node);
1177 ir_node *new_block = be_transform_node(block);
1178 ir_graph *irg = get_irn_irg(block);
1179 ir_node *selector = get_Switch_selector(node);
1180 ir_node *new_selector = be_transform_node(selector);
1181 const ir_switch_table *table = get_Switch_table(node);
1182 unsigned n_outs = get_Switch_n_outs(node);
1184 ir_node *table_address;
1189 table = ir_switch_table_duplicate(irg, table);
1191 /* switch with smaller mode not implemented yet */
1192 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1194 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1195 set_entity_visibility(entity, ir_visibility_private);
1196 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1198 /* construct base address */
1199 table_address = make_address(dbgi, new_block, entity, 0);
1201 idx = new_bd_sparc_Sll_imm(dbgi, new_block, new_selector, NULL, 2);
1202 /* load from jumptable */
1203 load = new_bd_sparc_Ld_reg(dbgi, new_block, table_address, idx,
1204 get_irg_no_mem(current_ir_graph),
1206 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1208 return new_bd_sparc_SwitchJmp(dbgi, new_block, address, n_outs, table, entity);
1211 static ir_node *gen_Cond(ir_node *node)
1213 ir_node *selector = get_Cond_selector(node);
1218 ir_relation relation;
1221 /* note: after lower_mode_b we are guaranteed to have a Cmp input */
1222 block = be_transform_node(get_nodes_block(node));
1223 dbgi = get_irn_dbg_info(node);
1224 cmp_left = get_Cmp_left(selector);
1225 cmp_mode = get_irn_mode(cmp_left);
1226 flag_node = be_transform_node(selector);
1227 relation = get_Cmp_relation(selector);
1228 if (mode_is_float(cmp_mode)) {
1229 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1231 bool is_unsigned = !mode_is_signed(cmp_mode);
1232 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1239 static ir_node *gen_Cmp(ir_node *node)
1241 ir_node *op1 = get_Cmp_left(node);
1242 ir_node *op2 = get_Cmp_right(node);
1243 ir_mode *cmp_mode = get_irn_mode(op1);
1244 assert(get_irn_mode(op2) == cmp_mode);
1246 if (mode_is_float(cmp_mode)) {
1247 ir_node *block = be_transform_node(get_nodes_block(node));
1248 dbg_info *dbgi = get_irn_dbg_info(node);
1249 ir_node *new_op1 = be_transform_node(op1);
1250 ir_node *new_op2 = be_transform_node(op2);
1251 unsigned bits = get_mode_size_bits(cmp_mode);
1253 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1254 } else if (bits == 64) {
1255 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1257 assert(bits == 128);
1258 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1262 /* when we compare a bitop like and,or,... with 0 then we can directly use
1263 * the bitopcc variant.
1264 * Currently we only do this when we're the only user of the node...
1266 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1268 return gen_helper_bitop(op1,
1269 new_bd_sparc_AndCCZero_reg,
1270 new_bd_sparc_AndCCZero_imm,
1271 new_bd_sparc_AndNCCZero_reg,
1272 new_bd_sparc_AndNCCZero_imm,
1274 } else if (is_Or(op1)) {
1275 return gen_helper_bitop(op1,
1276 new_bd_sparc_OrCCZero_reg,
1277 new_bd_sparc_OrCCZero_imm,
1278 new_bd_sparc_OrNCCZero_reg,
1279 new_bd_sparc_OrNCCZero_imm,
1281 } else if (is_Eor(op1)) {
1282 return gen_helper_bitop(op1,
1283 new_bd_sparc_XorCCZero_reg,
1284 new_bd_sparc_XorCCZero_imm,
1285 new_bd_sparc_XNorCCZero_reg,
1286 new_bd_sparc_XNorCCZero_imm,
1288 } else if (is_Add(op1)) {
1289 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1290 new_bd_sparc_AddCCZero_reg,
1291 new_bd_sparc_AddCCZero_imm);
1292 } else if (is_Sub(op1)) {
1293 return gen_helper_binop(op1, MATCH_NONE,
1294 new_bd_sparc_SubCCZero_reg,
1295 new_bd_sparc_SubCCZero_imm);
1296 } else if (is_Mul(op1)) {
1297 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1298 new_bd_sparc_MulCCZero_reg,
1299 new_bd_sparc_MulCCZero_imm);
1303 /* integer compare */
1304 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1305 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1309 * Transforms a SymConst node.
1311 static ir_node *gen_SymConst(ir_node *node)
1313 ir_entity *entity = get_SymConst_entity(node);
1314 dbg_info *dbgi = get_irn_dbg_info(node);
1315 ir_node *block = get_nodes_block(node);
1316 ir_node *new_block = be_transform_node(block);
1317 return make_address(dbgi, new_block, entity, 0);
1320 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1321 ir_mode *src_mode, ir_mode *dst_mode)
1323 unsigned src_bits = get_mode_size_bits(src_mode);
1324 unsigned dst_bits = get_mode_size_bits(dst_mode);
1325 if (src_bits == 32) {
1326 if (dst_bits == 64) {
1327 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1329 assert(dst_bits == 128);
1330 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1332 } else if (src_bits == 64) {
1333 if (dst_bits == 32) {
1334 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1336 assert(dst_bits == 128);
1337 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1340 assert(src_bits == 128);
1341 if (dst_bits == 32) {
1342 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1344 assert(dst_bits == 64);
1345 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1350 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1354 unsigned bits = get_mode_size_bits(src_mode);
1356 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1357 } else if (bits == 64) {
1358 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1360 assert(bits == 128);
1361 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1365 ir_graph *irg = get_irn_irg(block);
1366 ir_node *sp = get_irg_frame(irg);
1367 ir_node *nomem = get_irg_no_mem(irg);
1368 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1370 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1372 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1373 set_irn_pinned(stf, op_pin_state_floats);
1374 set_irn_pinned(ld, op_pin_state_floats);
1379 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1382 ir_graph *irg = get_irn_irg(block);
1383 ir_node *sp = get_irg_frame(irg);
1384 ir_node *nomem = get_irg_no_mem(irg);
1385 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1386 mode_gp, NULL, 0, true);
1387 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1389 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1390 unsigned bits = get_mode_size_bits(dst_mode);
1391 set_irn_pinned(st, op_pin_state_floats);
1392 set_irn_pinned(ldf, op_pin_state_floats);
1395 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1396 } else if (bits == 64) {
1397 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1399 assert(bits == 128);
1400 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1404 static ir_node *gen_Conv(ir_node *node)
1406 ir_node *block = be_transform_node(get_nodes_block(node));
1407 ir_node *op = get_Conv_op(node);
1408 ir_mode *src_mode = get_irn_mode(op);
1409 ir_mode *dst_mode = get_irn_mode(node);
1410 dbg_info *dbgi = get_irn_dbg_info(node);
1413 int src_bits = get_mode_size_bits(src_mode);
1414 int dst_bits = get_mode_size_bits(dst_mode);
1416 if (src_mode == mode_b)
1417 panic("ConvB not lowered %+F", node);
1419 if (src_mode == dst_mode)
1420 return be_transform_node(op);
1422 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1423 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1425 new_op = be_transform_node(op);
1426 if (mode_is_float(src_mode)) {
1427 if (mode_is_float(dst_mode)) {
1428 /* float -> float conv */
1429 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1431 /* float -> int conv */
1432 if (!mode_is_signed(dst_mode))
1433 panic("float to unsigned not implemented yet");
1434 return create_ftoi(dbgi, block, new_op, src_mode);
1437 /* int -> float conv */
1438 if (src_bits < 32) {
1439 new_op = gen_extension(dbgi, block, new_op, src_mode);
1440 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1441 panic("unsigned to float not lowered!");
1443 return create_itof(dbgi, block, new_op, dst_mode);
1445 } else { /* complete in gp registers */
1449 if (src_bits == dst_bits || dst_mode == mode_b) {
1450 /* kill unnecessary conv */
1451 return be_transform_node(op);
1454 if (src_bits < dst_bits) {
1455 min_bits = src_bits;
1456 min_mode = src_mode;
1458 min_bits = dst_bits;
1459 min_mode = dst_mode;
1462 if (upper_bits_clean(op, min_mode)) {
1463 return be_transform_node(op);
1465 new_op = be_transform_node(op);
1467 if (mode_is_signed(min_mode)) {
1468 return gen_sign_extension(dbgi, block, new_op, min_bits);
1470 return gen_zero_extension(dbgi, block, new_op, min_bits);
1475 static ir_node *gen_Unknown(ir_node *node)
1477 /* just produce a 0 */
1478 ir_mode *mode = get_irn_mode(node);
1479 if (mode_is_float(mode)) {
1480 ir_node *block = be_transform_node(get_nodes_block(node));
1481 return gen_float_const(NULL, block, get_mode_null(mode));
1482 } else if (mode_needs_gp_reg(mode)) {
1483 ir_graph *irg = get_irn_irg(node);
1487 panic("Unexpected Unknown mode");
1491 * transform the start node to the prolog code
1493 static ir_node *gen_Start(ir_node *node)
1495 ir_graph *irg = get_irn_irg(node);
1496 ir_entity *entity = get_irg_entity(irg);
1497 ir_type *function_type = get_entity_type(entity);
1498 ir_node *block = get_nodes_block(node);
1499 ir_node *new_block = be_transform_node(block);
1500 dbg_info *dbgi = get_irn_dbg_info(node);
1501 struct obstack *obst = be_get_be_obst(irg);
1502 const arch_register_req_t *req;
1508 /* start building list of start constraints */
1509 assert(obstack_object_size(obst) == 0);
1511 /* calculate number of outputs */
1512 n_outs = 4; /* memory, g0, g7, sp */
1513 if (!current_cconv->omit_fp)
1514 ++n_outs; /* framepointer */
1515 /* function parameters */
1516 n_outs += current_cconv->n_param_regs;
1518 if (current_cconv->omit_fp) {
1519 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1522 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1526 /* first output is memory */
1527 start_mem_offset = o;
1528 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1531 /* the zero register */
1532 start_g0_offset = o;
1533 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1534 arch_register_req_type_ignore);
1535 arch_set_irn_register_req_out(start, o, req);
1536 arch_set_irn_register_out(start, o, &sparc_registers[REG_G0]);
1539 /* g7 is used for TLS data */
1540 start_g7_offset = o;
1541 req = be_create_reg_req(obst, &sparc_registers[REG_G7],
1542 arch_register_req_type_ignore);
1543 arch_set_irn_register_req_out(start, o, req);
1544 arch_set_irn_register_out(start, o, &sparc_registers[REG_G7]);
1547 /* we need an output for the stackpointer */
1548 start_sp_offset = o;
1549 req = be_create_reg_req(obst, sp_reg,
1550 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1551 arch_set_irn_register_req_out(start, o, req);
1552 arch_set_irn_register_out(start, o, sp_reg);
1555 if (!current_cconv->omit_fp) {
1556 start_fp_offset = o;
1557 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1558 arch_set_irn_register_req_out(start, o, req);
1559 arch_set_irn_register_out(start, o, fp_reg);
1563 /* function parameters in registers */
1564 start_params_offset = o;
1565 for (i = 0; i < get_method_n_params(function_type); ++i) {
1566 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1567 const arch_register_t *reg0 = param->reg0;
1568 const arch_register_t *reg1 = param->reg1;
1570 arch_set_irn_register_req_out(start, o, reg0->single_req);
1571 arch_set_irn_register_out(start, o, reg0);
1575 arch_set_irn_register_req_out(start, o, reg1->single_req);
1576 arch_set_irn_register_out(start, o, reg1);
1580 /* we need the values of the callee saves (Note: non omit-fp mode has no
1582 start_callee_saves_offset = o;
1583 if (current_cconv->omit_fp) {
1584 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1586 for (c = 0; c < n_callee_saves; ++c) {
1587 const arch_register_t *reg = omit_fp_callee_saves[c];
1588 arch_set_irn_register_req_out(start, o, reg->single_req);
1589 arch_set_irn_register_out(start, o, reg);
1593 assert(n_outs == o);
1598 static ir_node *get_initial_sp(ir_graph *irg)
1600 if (start_sp == NULL) {
1601 ir_node *start = get_irg_start(irg);
1602 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1607 static ir_node *get_initial_fp(ir_graph *irg)
1609 if (start_fp == NULL) {
1610 ir_node *start = get_irg_start(irg);
1611 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1616 static ir_node *get_initial_mem(ir_graph *irg)
1618 if (start_mem == NULL) {
1619 ir_node *start = get_irg_start(irg);
1620 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1625 static ir_node *get_stack_pointer_for(ir_node *node)
1627 /* get predecessor in stack_order list */
1628 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1631 if (stack_pred == NULL) {
1632 /* first stack user in the current block. We can simply use the
1633 * initial sp_proj for it */
1634 ir_graph *irg = get_irn_irg(node);
1635 return get_initial_sp(irg);
1638 be_transform_node(stack_pred);
1639 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1640 if (stack == NULL) {
1641 return get_stack_pointer_for(stack_pred);
1648 * transform a Return node into epilogue code + return statement
1650 static ir_node *gen_Return(ir_node *node)
1652 ir_node *block = get_nodes_block(node);
1653 ir_graph *irg = get_irn_irg(node);
1654 ir_node *new_block = be_transform_node(block);
1655 dbg_info *dbgi = get_irn_dbg_info(node);
1656 ir_node *mem = get_Return_mem(node);
1657 ir_node *new_mem = be_transform_node(mem);
1658 ir_node *sp = get_stack_pointer_for(node);
1659 size_t n_res = get_Return_n_ress(node);
1660 struct obstack *be_obst = be_get_be_obst(irg);
1663 const arch_register_req_t **reqs;
1668 /* estimate number of return values */
1669 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1670 if (current_cconv->omit_fp)
1671 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1673 in = ALLOCAN(ir_node*, n_ins);
1674 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1678 reqs[p] = arch_no_register_req;
1682 reqs[p] = sp_reg->single_req;
1686 for (i = 0; i < n_res; ++i) {
1687 ir_node *res_value = get_Return_res(node, i);
1688 ir_node *new_res_value = be_transform_node(res_value);
1689 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1690 assert(slot->req1 == NULL);
1691 in[p] = new_res_value;
1692 reqs[p] = slot->req0;
1696 if (current_cconv->omit_fp) {
1697 ir_node *start = get_irg_start(irg);
1698 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1699 for (i = 0; i < n_callee_saves; ++i) {
1700 const arch_register_t *reg = omit_fp_callee_saves[i];
1701 ir_mode *mode = reg->reg_class->mode;
1703 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1705 reqs[p] = reg->single_req;
1711 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1712 arch_set_irn_register_reqs_in(bereturn, reqs);
1717 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1718 ir_node *value0, ir_node *value1)
1720 ir_graph *irg = current_ir_graph;
1721 ir_node *sp = get_irg_frame(irg);
1722 ir_node *nomem = get_irg_no_mem(irg);
1723 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1724 mode_gp, NULL, 0, true);
1728 set_irn_pinned(st, op_pin_state_floats);
1730 if (value1 != NULL) {
1731 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1732 mode_gp, NULL, 4, true);
1733 ir_node *in[2] = { st, st1 };
1734 ir_node *sync = new_r_Sync(block, 2, in);
1735 set_irn_pinned(st1, op_pin_state_floats);
1743 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1744 set_irn_pinned(ldf, op_pin_state_floats);
1746 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1749 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1750 ir_node *node, ir_mode *float_mode,
1753 ir_graph *irg = current_ir_graph;
1754 ir_node *stack = get_irg_frame(irg);
1755 ir_node *nomem = get_irg_no_mem(irg);
1756 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1758 int bits = get_mode_size_bits(float_mode);
1760 set_irn_pinned(stf, op_pin_state_floats);
1762 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1763 set_irn_pinned(ld, op_pin_state_floats);
1764 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1767 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1769 set_irn_pinned(ld, op_pin_state_floats);
1770 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1772 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1773 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1780 static ir_node *gen_Call(ir_node *node)
1782 ir_graph *irg = get_irn_irg(node);
1783 ir_node *callee = get_Call_ptr(node);
1784 ir_node *block = get_nodes_block(node);
1785 ir_node *new_block = be_transform_node(block);
1786 ir_node *mem = get_Call_mem(node);
1787 ir_node *new_mem = be_transform_node(mem);
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_type *type = get_Call_type(node);
1790 size_t n_params = get_Call_n_params(node);
1791 size_t n_ress = get_method_n_ress(type);
1792 /* max inputs: memory, callee, register arguments */
1793 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1794 struct obstack *obst = be_get_be_obst(irg);
1795 calling_convention_t *cconv
1796 = sparc_decide_calling_convention(type, NULL);
1797 size_t n_param_regs = cconv->n_param_regs;
1798 /* param-regs + mem + stackpointer + callee */
1799 unsigned max_inputs = 3 + n_param_regs;
1800 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1801 const arch_register_req_t **in_req
1802 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1806 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1807 ir_entity *entity = NULL;
1808 ir_node *new_frame = get_stack_pointer_for(node);
1809 bool aggregate_return
1810 = get_method_calling_convention(type) & cc_compound_ret;
1820 assert(n_params == get_method_n_params(type));
1822 /* construct arguments */
1825 in_req[in_arity] = arch_no_register_req;
1829 /* stack pointer input */
1830 /* construct an IncSP -> we have to always be sure that the stack is
1831 * aligned even if we don't push arguments on it */
1832 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1833 cconv->param_stack_size, 1);
1834 in_req[in_arity] = sp_reg->single_req;
1835 in[in_arity] = incsp;
1839 for (p = 0; p < n_params; ++p) {
1840 ir_node *value = get_Call_param(node, p);
1841 ir_node *new_value = be_transform_node(value);
1842 const reg_or_stackslot_t *param = &cconv->parameters[p];
1843 ir_type *param_type = get_method_param_type(type, p);
1844 ir_mode *mode = get_type_mode(param_type);
1845 ir_node *new_values[2];
1849 if (mode_is_float(mode) && param->reg0 != NULL) {
1850 unsigned size_bits = get_mode_size_bits(mode);
1851 assert(size_bits <= 64);
1852 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1854 new_values[0] = new_value;
1855 new_values[1] = NULL;
1858 /* put value into registers */
1859 if (param->reg0 != NULL) {
1860 in[in_arity] = new_values[0];
1861 in_req[in_arity] = param->reg0->single_req;
1863 if (new_values[1] == NULL)
1866 if (param->reg1 != NULL) {
1867 assert(new_values[1] != NULL);
1868 in[in_arity] = new_values[1];
1869 in_req[in_arity] = param->reg1->single_req;
1874 /* we need a store if we're here */
1875 if (new_values[1] != NULL) {
1876 new_value = new_values[1];
1880 /* we need to skip over our save area when constructing the call
1881 * arguments on stack */
1882 offset = param->offset + SPARC_MIN_STACKSIZE;
1884 if (mode_is_float(mode)) {
1885 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1886 mode, NULL, offset, true);
1888 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1889 new_mem, mode, NULL, offset, true);
1891 set_irn_pinned(str, op_pin_state_floats);
1892 sync_ins[sync_arity++] = str;
1895 /* construct memory input */
1896 if (sync_arity == 0) {
1897 in[mem_pos] = new_mem;
1898 } else if (sync_arity == 1) {
1899 in[mem_pos] = sync_ins[0];
1901 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1904 if (is_SymConst(callee)) {
1905 entity = get_SymConst_entity(callee);
1907 in[in_arity] = be_transform_node(callee);
1908 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1911 assert(in_arity <= (int)max_inputs);
1918 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1920 /* create call node */
1921 if (entity != NULL) {
1922 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1923 entity, 0, aggregate_return);
1925 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1928 arch_set_irn_register_reqs_in(res, in_req);
1930 /* create output register reqs */
1932 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1933 /* add register requirements for the result regs */
1934 for (r = 0; r < n_ress; ++r) {
1935 const reg_or_stackslot_t *result_info = &cconv->results[r];
1936 const arch_register_req_t *req = result_info->req0;
1938 arch_set_irn_register_req_out(res, o++, req);
1940 assert(result_info->req1 == NULL);
1942 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1943 const arch_register_t *reg;
1944 if (!rbitset_is_set(cconv->caller_saves, i))
1946 reg = &sparc_registers[i];
1947 arch_set_irn_register_req_out(res, o++, reg->single_req);
1949 assert(o == out_arity);
1951 /* copy pinned attribute */
1952 set_irn_pinned(res, get_irn_pinned(node));
1954 /* IncSP to destroy the call stackframe */
1955 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1956 /* if we are the last IncSP producer in a block then we have to keep
1958 * Note: This here keeps all producers which is more than necessary */
1959 add_irn_dep(incsp, res);
1962 pmap_insert(node_to_stack, node, incsp);
1964 sparc_free_calling_convention(cconv);
1968 static ir_node *gen_Sel(ir_node *node)
1970 dbg_info *dbgi = get_irn_dbg_info(node);
1971 ir_node *block = get_nodes_block(node);
1972 ir_node *new_block = be_transform_node(block);
1973 ir_node *ptr = get_Sel_ptr(node);
1974 ir_node *new_ptr = be_transform_node(ptr);
1975 ir_entity *entity = get_Sel_entity(node);
1977 /* must be the frame pointer all other sels must have been lowered
1979 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1981 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1984 static ir_node *gen_Alloc(ir_node *node)
1986 dbg_info *dbgi = get_irn_dbg_info(node);
1987 ir_node *block = get_nodes_block(node);
1988 ir_node *new_block = be_transform_node(block);
1989 ir_type *type = get_Alloc_type(node);
1990 ir_node *size = get_Alloc_count(node);
1991 ir_node *stack_pred = get_stack_pointer_for(node);
1993 if (get_Alloc_where(node) != stack_alloc)
1994 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1995 /* lowerer should have transformed all allocas to byte size */
1996 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1997 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1999 if (is_Const(size)) {
2000 ir_tarval *tv = get_Const_tarval(size);
2001 long sizel = get_tarval_long(tv);
2002 subsp = be_new_IncSP(sp_reg, new_block, stack_pred, sizel, 0);
2003 set_irn_dbg_info(subsp, dbgi);
2005 ir_node *new_size = be_transform_node(size);
2006 subsp = new_bd_sparc_SubSP(dbgi, new_block, stack_pred, new_size);
2007 arch_set_irn_register(subsp, sp_reg);
2010 /* if we are the last IncSP producer in a block then we have to keep
2012 * Note: This here keeps all producers which is more than necessary */
2015 pmap_insert(node_to_stack, node, subsp);
2016 /* the "result" is the unmodified sp value */
2020 static ir_node *gen_Proj_Alloc(ir_node *node)
2022 ir_node *alloc = get_Proj_pred(node);
2023 long pn = get_Proj_proj(node);
2025 switch ((pn_Alloc)pn) {
2027 ir_node *alloc_mem = get_Alloc_mem(alloc);
2028 return be_transform_node(alloc_mem);
2030 case pn_Alloc_res: {
2031 ir_node *new_alloc = be_transform_node(alloc);
2034 case pn_Alloc_X_regular:
2035 case pn_Alloc_X_except:
2036 panic("sparc backend: exception output of alloc not supported (at %+F)",
2039 panic("sparc backend: invalid Proj->Alloc");
2042 static ir_node *gen_Free(ir_node *node)
2044 dbg_info *dbgi = get_irn_dbg_info(node);
2045 ir_node *block = get_nodes_block(node);
2046 ir_node *new_block = be_transform_node(block);
2047 ir_type *type = get_Free_type(node);
2048 ir_node *size = get_Free_count(node);
2049 ir_node *mem = get_Free_mem(node);
2050 ir_node *new_mem = be_transform_node(mem);
2051 ir_node *stack_pred = get_stack_pointer_for(node);
2053 if (get_Alloc_where(node) != stack_alloc)
2054 panic("only stack-alloc supported in sparc backend (at %+F)", node);
2055 /* lowerer should have transformed all allocas to byte size */
2056 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
2057 panic("Found non-byte alloc in sparc backend (at %+F)", node);
2059 if (is_Const(size)) {
2060 ir_tarval *tv = get_Const_tarval(size);
2061 long sizel = get_tarval_long(tv);
2062 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
2063 set_irn_dbg_info(addsp, dbgi);
2065 ir_node *new_size = be_transform_node(size);
2066 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
2067 arch_set_irn_register(addsp, sp_reg);
2070 /* if we are the last IncSP producer in a block then we have to keep
2072 * Note: This here keeps all producers which is more than necessary */
2075 pmap_insert(node_to_stack, node, addsp);
2076 /* the "result" is the unmodified sp value */
2080 static const arch_register_req_t float1_req = {
2081 arch_register_req_type_normal,
2082 &sparc_reg_classes[CLASS_sparc_fp],
2088 static const arch_register_req_t float2_req = {
2089 arch_register_req_type_normal | arch_register_req_type_aligned,
2090 &sparc_reg_classes[CLASS_sparc_fp],
2096 static const arch_register_req_t float4_req = {
2097 arch_register_req_type_normal | arch_register_req_type_aligned,
2098 &sparc_reg_classes[CLASS_sparc_fp],
2106 static const arch_register_req_t *get_float_req(ir_mode *mode)
2108 unsigned bits = get_mode_size_bits(mode);
2110 assert(mode_is_float(mode));
2113 } else if (bits == 64) {
2116 assert(bits == 128);
2122 * Transform some Phi nodes
2124 static ir_node *gen_Phi(ir_node *node)
2126 const arch_register_req_t *req;
2127 ir_node *block = be_transform_node(get_nodes_block(node));
2128 ir_graph *irg = current_ir_graph;
2129 dbg_info *dbgi = get_irn_dbg_info(node);
2130 ir_mode *mode = get_irn_mode(node);
2133 if (mode_needs_gp_reg(mode)) {
2134 /* we shouldn't have any 64bit stuff around anymore */
2135 assert(get_mode_size_bits(mode) <= 32);
2136 /* all integer operations are on 32bit registers now */
2138 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2139 } else if (mode_is_float(mode)) {
2141 req = get_float_req(mode);
2143 req = arch_no_register_req;
2146 /* phi nodes allow loops, so we use the old arguments for now
2147 * and fix this later */
2148 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2149 copy_node_attr(irg, node, phi);
2150 be_duplicate_deps(node, phi);
2151 arch_set_irn_register_req_out(phi, 0, req);
2152 be_enqueue_preds(node);
2157 * Transform a Proj from a Load.
2159 static ir_node *gen_Proj_Load(ir_node *node)
2161 ir_node *load = get_Proj_pred(node);
2162 ir_node *new_load = be_transform_node(load);
2163 dbg_info *dbgi = get_irn_dbg_info(node);
2164 long pn = get_Proj_proj(node);
2166 /* renumber the proj */
2167 switch (get_sparc_irn_opcode(new_load)) {
2169 /* handle all gp loads equal: they have the same proj numbers. */
2170 if (pn == pn_Load_res) {
2171 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2172 } else if (pn == pn_Load_M) {
2173 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2177 if (pn == pn_Load_res) {
2178 const sparc_load_store_attr_t *attr
2179 = get_sparc_load_store_attr_const(new_load);
2180 ir_mode *mode = attr->load_store_mode;
2181 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2182 } else if (pn == pn_Load_M) {
2183 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2189 panic("Unsupported Proj from Load");
2192 static ir_node *gen_Proj_Store(ir_node *node)
2194 ir_node *store = get_Proj_pred(node);
2195 ir_node *new_store = be_transform_node(store);
2196 long pn = get_Proj_proj(node);
2198 /* renumber the proj */
2199 switch (get_sparc_irn_opcode(new_store)) {
2201 if (pn == pn_Store_M) {
2206 if (pn == pn_Store_M) {
2213 panic("Unsupported Proj from Store");
2217 * Transform the Projs from a Cmp.
2219 static ir_node *gen_Proj_Cmp(ir_node *node)
2222 panic("not implemented");
2226 * transform Projs from a Div
2228 static ir_node *gen_Proj_Div(ir_node *node)
2230 ir_node *pred = get_Proj_pred(node);
2231 ir_node *new_pred = be_transform_node(pred);
2232 long pn = get_Proj_proj(node);
2235 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2237 } else if (is_sparc_fdiv(new_pred)) {
2238 res_mode = get_Div_resmode(pred);
2240 panic("sparc backend: Div transformed to something unexpected: %+F",
2243 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2244 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2245 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2246 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2249 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2251 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
2255 panic("Unsupported Proj from Div");
2258 static ir_node *get_frame_base(ir_graph *irg)
2260 if (frame_base == NULL) {
2261 if (current_cconv->omit_fp) {
2262 frame_base = get_initial_sp(irg);
2264 frame_base = get_initial_fp(irg);
2270 static ir_node *gen_Proj_Start(ir_node *node)
2272 ir_node *block = get_nodes_block(node);
2273 ir_node *new_block = be_transform_node(block);
2274 long pn = get_Proj_proj(node);
2275 /* make sure prolog is constructed */
2276 be_transform_node(get_Proj_pred(node));
2278 switch ((pn_Start) pn) {
2279 case pn_Start_X_initial_exec:
2280 /* exchange ProjX with a jump */
2281 return new_bd_sparc_Ba(NULL, new_block);
2283 ir_graph *irg = get_irn_irg(node);
2284 return get_initial_mem(irg);
2286 case pn_Start_T_args:
2287 return new_r_Bad(get_irn_irg(block), mode_T);
2288 case pn_Start_P_frame_base:
2289 return get_frame_base(get_irn_irg(block));
2291 panic("Unexpected start proj: %ld\n", pn);
2294 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2296 long pn = get_Proj_proj(node);
2297 ir_node *block = get_nodes_block(node);
2298 ir_graph *irg = get_irn_irg(node);
2299 ir_node *new_block = be_transform_node(block);
2300 ir_node *args = get_Proj_pred(node);
2301 ir_node *start = get_Proj_pred(args);
2302 ir_node *new_start = be_transform_node(start);
2303 const reg_or_stackslot_t *param;
2305 /* Proj->Proj->Start must be a method argument */
2306 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2308 param = ¤t_cconv->parameters[pn];
2310 if (param->reg0 != NULL) {
2311 /* argument transmitted in register */
2312 const arch_register_t *reg = param->reg0;
2313 ir_mode *reg_mode = reg->reg_class->mode;
2314 long new_pn = param->reg_offset + start_params_offset;
2315 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2316 bool is_float = false;
2319 ir_entity *entity = get_irg_entity(irg);
2320 ir_type *method_type = get_entity_type(entity);
2321 if (pn < (long)get_method_n_params(method_type)) {
2322 ir_type *param_type = get_method_param_type(method_type, pn);
2323 ir_mode *mode = get_type_mode(param_type);
2324 is_float = mode_is_float(mode);
2329 const arch_register_t *reg1 = param->reg1;
2330 ir_node *value1 = NULL;
2333 ir_mode *reg1_mode = reg1->reg_class->mode;
2334 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2335 } else if (param->entity != NULL) {
2336 ir_node *fp = get_initial_fp(irg);
2337 ir_node *mem = get_initial_mem(irg);
2338 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2339 mode_gp, param->entity,
2341 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2344 /* convert integer value to float */
2345 value = bitcast_int_to_float(NULL, new_block, value, value1);
2349 /* argument transmitted on stack */
2350 ir_node *mem = get_initial_mem(irg);
2351 ir_mode *mode = get_type_mode(param->type);
2352 ir_node *base = get_frame_base(irg);
2356 if (mode_is_float(mode)) {
2357 load = create_ldf(NULL, new_block, base, mem, mode,
2358 param->entity, 0, true);
2359 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2361 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2362 param->entity, 0, true);
2363 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2365 set_irn_pinned(load, op_pin_state_floats);
2371 static ir_node *gen_Proj_Call(ir_node *node)
2373 long pn = get_Proj_proj(node);
2374 ir_node *call = get_Proj_pred(node);
2375 ir_node *new_call = be_transform_node(call);
2377 switch ((pn_Call) pn) {
2379 return new_r_Proj(new_call, mode_M, 0);
2380 case pn_Call_X_regular:
2381 case pn_Call_X_except:
2382 case pn_Call_T_result:
2385 panic("Unexpected Call proj %ld\n", pn);
2388 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2390 long pn = get_Proj_proj(node);
2391 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2392 ir_node *new_call = be_transform_node(call);
2393 ir_type *function_type = get_Call_type(call);
2394 calling_convention_t *cconv
2395 = sparc_decide_calling_convention(function_type, NULL);
2396 const reg_or_stackslot_t *res = &cconv->results[pn];
2397 ir_mode *mode = get_irn_mode(node);
2398 long new_pn = 1 + res->reg_offset;
2400 assert(res->req0 != NULL && res->req1 == NULL);
2401 if (mode_needs_gp_reg(mode)) {
2404 sparc_free_calling_convention(cconv);
2406 return new_r_Proj(new_call, mode, new_pn);
2410 * Transform a Proj node.
2412 static ir_node *gen_Proj(ir_node *node)
2414 ir_node *pred = get_Proj_pred(node);
2416 switch (get_irn_opcode(pred)) {
2418 return gen_Proj_Alloc(node);
2420 return gen_Proj_Store(node);
2422 return gen_Proj_Load(node);
2424 return gen_Proj_Call(node);
2426 return gen_Proj_Cmp(node);
2429 return be_duplicate_node(node);
2431 return gen_Proj_Div(node);
2433 return gen_Proj_Start(node);
2435 ir_node *pred_pred = get_Proj_pred(pred);
2436 if (is_Call(pred_pred)) {
2437 return gen_Proj_Proj_Call(node);
2438 } else if (is_Start(pred_pred)) {
2439 return gen_Proj_Proj_Start(node);
2444 if (is_sparc_AddCC_t(pred)) {
2445 return gen_Proj_AddCC_t(node);
2446 } else if (is_sparc_SubCC_t(pred)) {
2447 return gen_Proj_SubCC_t(node);
2449 panic("code selection didn't expect Proj after %+F\n", pred);
2456 static ir_node *gen_Jmp(ir_node *node)
2458 ir_node *block = get_nodes_block(node);
2459 ir_node *new_block = be_transform_node(block);
2460 dbg_info *dbgi = get_irn_dbg_info(node);
2462 return new_bd_sparc_Ba(dbgi, new_block);
2466 * configure transformation callbacks
2468 static void sparc_register_transformers(void)
2470 be_start_transform_setup();
2472 be_set_transform_function(op_Add, gen_Add);
2473 be_set_transform_function(op_Alloc, gen_Alloc);
2474 be_set_transform_function(op_And, gen_And);
2475 be_set_transform_function(op_Call, gen_Call);
2476 be_set_transform_function(op_Cmp, gen_Cmp);
2477 be_set_transform_function(op_Cond, gen_Cond);
2478 be_set_transform_function(op_Const, gen_Const);
2479 be_set_transform_function(op_Conv, gen_Conv);
2480 be_set_transform_function(op_Div, gen_Div);
2481 be_set_transform_function(op_Eor, gen_Eor);
2482 be_set_transform_function(op_Free, gen_Free);
2483 be_set_transform_function(op_Jmp, gen_Jmp);
2484 be_set_transform_function(op_Load, gen_Load);
2485 be_set_transform_function(op_Minus, gen_Minus);
2486 be_set_transform_function(op_Mul, gen_Mul);
2487 be_set_transform_function(op_Mulh, gen_Mulh);
2488 be_set_transform_function(op_Not, gen_Not);
2489 be_set_transform_function(op_Or, gen_Or);
2490 be_set_transform_function(op_Phi, gen_Phi);
2491 be_set_transform_function(op_Proj, gen_Proj);
2492 be_set_transform_function(op_Return, gen_Return);
2493 be_set_transform_function(op_Sel, gen_Sel);
2494 be_set_transform_function(op_Shl, gen_Shl);
2495 be_set_transform_function(op_Shr, gen_Shr);
2496 be_set_transform_function(op_Shrs, gen_Shrs);
2497 be_set_transform_function(op_Start, gen_Start);
2498 be_set_transform_function(op_Store, gen_Store);
2499 be_set_transform_function(op_Sub, gen_Sub);
2500 be_set_transform_function(op_Switch, gen_Switch);
2501 be_set_transform_function(op_SymConst, gen_SymConst);
2502 be_set_transform_function(op_Unknown, gen_Unknown);
2504 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2505 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2506 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2507 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2508 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2512 * Transform a Firm graph into a SPARC graph.
2514 void sparc_transform_graph(ir_graph *irg)
2516 ir_entity *entity = get_irg_entity(irg);
2517 ir_type *frame_type;
2519 sparc_register_transformers();
2521 node_to_stack = pmap_create();
2523 mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
2524 mode_fp = sparc_reg_classes[CLASS_sparc_fp].mode;
2527 mode_flags = sparc_reg_classes[CLASS_sparc_flags_class].mode;
2528 assert(sparc_reg_classes[CLASS_sparc_fpflags_class].mode == mode_flags);
2537 stackorder = be_collect_stacknodes(irg);
2539 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2540 if (sparc_variadic_fixups(irg, current_cconv)) {
2541 sparc_free_calling_convention(current_cconv);
2543 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2545 sparc_create_stacklayout(irg, current_cconv);
2546 be_add_parameter_entity_stores(irg);
2548 be_transform_graph(irg, NULL);
2550 be_free_stackorder(stackorder);
2551 sparc_free_calling_convention(current_cconv);
2553 frame_type = get_irg_frame_type(irg);
2554 if (get_type_state(frame_type) == layout_undefined)
2555 default_layout_compound_type(frame_type);
2557 pmap_destroy(node_to_stack);
2558 node_to_stack = NULL;
2560 be_add_missing_keeps(irg);
2562 /* do code placement, to optimize the position of constants */
2564 /* backend expects outedges to be always on */
2568 void sparc_init_transform(void)
2570 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");