2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief code selection (transform FIRM into SPARC FIRM)
9 * @author Hannes Rapp, Matthias Braun
17 #include "irgraph_t.h"
23 #include "iroptimize.h"
33 #include "betranshlp.h"
34 #include "beabihelper.h"
35 #include "bearch_sparc_t.h"
37 #include "sparc_nodes_attr.h"
38 #include "sparc_transform.h"
39 #include "sparc_new_nodes.h"
40 #include "gen_sparc_new_nodes.h"
42 #include "gen_sparc_regalloc_if.h"
43 #include "sparc_cconv.h"
47 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
49 typedef struct reg_info_t {
54 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
55 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
56 static calling_convention_t *current_cconv = NULL;
57 static be_stackorder_t *stackorder;
58 static ir_mode *mode_gp;
59 static ir_mode *mode_flags;
60 static ir_mode *mode_fp;
61 static ir_mode *mode_fp2;
62 //static ir_mode *mode_fp4;
63 static pmap *node_to_stack;
64 static reg_info_t start_mem;
65 static reg_info_t start_g0;
66 static reg_info_t start_g7;
67 static reg_info_t start_sp;
68 static reg_info_t start_fp;
69 static ir_node *frame_base;
70 static size_t start_params_offset;
71 static size_t start_callee_saves_offset;
73 static const arch_register_t *const omit_fp_callee_saves[] = {
74 &sparc_registers[REG_L0],
75 &sparc_registers[REG_L1],
76 &sparc_registers[REG_L2],
77 &sparc_registers[REG_L3],
78 &sparc_registers[REG_L4],
79 &sparc_registers[REG_L5],
80 &sparc_registers[REG_L6],
81 &sparc_registers[REG_L7],
82 &sparc_registers[REG_I0],
83 &sparc_registers[REG_I1],
84 &sparc_registers[REG_I2],
85 &sparc_registers[REG_I3],
86 &sparc_registers[REG_I4],
87 &sparc_registers[REG_I5],
90 static inline bool mode_needs_gp_reg(ir_mode *mode)
92 if (mode_is_int(mode) || mode_is_reference(mode)) {
93 /* we should only see 32bit code */
94 assert(get_mode_size_bits(mode) <= 32);
101 * Create an And that will zero out upper bits.
103 * @param dbgi debug info
104 * @param block the basic block
105 * @param op the original node
106 * @param src_bits number of lower bits that will remain
108 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
112 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
113 } else if (src_bits == 16) {
114 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
115 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
118 panic("zero extension only supported for 8 and 16 bits");
123 * Generate code for a sign extension.
125 * @param dbgi debug info
126 * @param block the basic block
127 * @param op the original node
128 * @param src_bits number of lower bits that will remain
130 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
133 int shift_width = 32 - src_bits;
134 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
135 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
140 * Extend a value to 32 bit signed/unsigned depending on its mode.
142 * @param dbgi debug info
143 * @param block the basic block
144 * @param op the original node
145 * @param orig_mode the original mode of op
147 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
150 int bits = get_mode_size_bits(orig_mode);
153 if (mode_is_signed(orig_mode)) {
154 return gen_sign_extension(dbgi, block, op, bits);
156 return gen_zero_extension(dbgi, block, op, bits);
162 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
163 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
164 influence the significant lower bit at
165 all (for cases where mode < 32bit) */
167 ENUM_BITSET(match_flags_t)
169 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
170 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
171 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
172 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
175 * checks if a node's value can be encoded as a immediate
177 static bool is_imm_encodeable(const ir_node *node)
183 value = get_tarval_long(get_Const_tarval(node));
184 return sparc_is_value_imm_encodeable(value);
187 static bool needs_extension(ir_node *op)
189 ir_mode *mode = get_irn_mode(op);
190 unsigned gp_bits = get_mode_size_bits(mode_gp);
191 if (get_mode_size_bits(mode) >= gp_bits)
193 return !be_upper_bits_clean(op, mode);
197 * Check, if a given node is a Down-Conv, i.e. a integer Conv
198 * from a mode with a mode with more bits to a mode with lesser bits.
199 * Moreover, we return only true if the node has not more than 1 user.
201 * @param node the node
202 * @return non-zero if node is a Down-Conv
204 static bool is_downconv(const ir_node *node)
212 src_mode = get_irn_mode(get_Conv_op(node));
213 dest_mode = get_irn_mode(node);
215 mode_needs_gp_reg(src_mode) &&
216 mode_needs_gp_reg(dest_mode) &&
217 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
220 static ir_node *skip_downconv(ir_node *node)
222 while (is_downconv(node)) {
223 node = get_Conv_op(node);
229 * helper function for binop operations
231 * @param new_reg register generation function ptr
232 * @param new_imm immediate generation function ptr
234 static ir_node *gen_helper_binop_args(ir_node *node,
235 ir_node *op1, ir_node *op2,
237 new_binop_reg_func new_reg,
238 new_binop_imm_func new_imm)
240 dbg_info *dbgi = get_irn_dbg_info(node);
241 ir_node *block = be_transform_node(get_nodes_block(node));
247 if (flags & MATCH_MODE_NEUTRAL) {
248 op1 = skip_downconv(op1);
249 op2 = skip_downconv(op2);
251 mode1 = get_irn_mode(op1);
252 mode2 = get_irn_mode(op2);
253 /* we shouldn't see 64bit code */
254 assert(get_mode_size_bits(mode1) <= 32);
255 assert(get_mode_size_bits(mode2) <= 32);
257 if (is_imm_encodeable(op2)) {
258 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
259 new_op1 = be_transform_node(op1);
260 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
261 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
263 return new_imm(dbgi, block, new_op1, NULL, immediate);
265 new_op2 = be_transform_node(op2);
266 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op2)) {
267 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
270 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
271 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
272 return new_imm(dbgi, block, new_op2, NULL, immediate);
275 new_op1 = be_transform_node(op1);
276 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(op1)) {
277 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
279 return new_reg(dbgi, block, new_op1, new_op2);
282 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
283 new_binop_reg_func new_reg,
284 new_binop_imm_func new_imm)
286 ir_node *op1 = get_binop_left(node);
287 ir_node *op2 = get_binop_right(node);
288 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
292 * helper function for FP binop operations
294 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
295 new_binop_fp_func new_func_single,
296 new_binop_fp_func new_func_double,
297 new_binop_fp_func new_func_quad)
299 ir_node *block = be_transform_node(get_nodes_block(node));
300 ir_node *op1 = get_binop_left(node);
301 ir_node *new_op1 = be_transform_node(op1);
302 ir_node *op2 = get_binop_right(node);
303 ir_node *new_op2 = be_transform_node(op2);
304 dbg_info *dbgi = get_irn_dbg_info(node);
305 unsigned bits = get_mode_size_bits(mode);
309 return new_func_single(dbgi, block, new_op1, new_op2, mode);
311 return new_func_double(dbgi, block, new_op1, new_op2, mode);
313 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
317 panic("unsupported mode %+F for float op", mode);
320 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
321 new_unop_fp_func new_func_single,
322 new_unop_fp_func new_func_double,
323 new_unop_fp_func new_func_quad)
325 ir_node *block = be_transform_node(get_nodes_block(node));
326 ir_node *op = get_unop_op(node);
327 ir_node *new_op = be_transform_node(op);
328 dbg_info *dbgi = get_irn_dbg_info(node);
329 unsigned bits = get_mode_size_bits(mode);
333 return new_func_single(dbgi, block, new_op, mode);
335 return new_func_double(dbgi, block, new_op, mode);
337 return new_func_quad(dbgi, block, new_op, mode);
341 panic("unsupported mode %+F for float op", mode);
344 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
345 ir_node *op1, ir_node *flags,
346 ir_entity *imm_entity, int32_t imm);
348 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
349 ir_node *op1, ir_node *op2,
352 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
353 new_binopx_reg_func new_binopx_reg,
354 new_binopx_imm_func new_binopx_imm)
356 dbg_info *dbgi = get_irn_dbg_info(node);
357 ir_node *block = be_transform_node(get_nodes_block(node));
358 ir_node *op1 = get_irn_n(node, 0);
359 ir_node *op2 = get_irn_n(node, 1);
360 ir_node *flags = get_irn_n(node, 2);
361 ir_node *new_flags = be_transform_node(flags);
365 /* only support for mode-neutral implemented so far */
366 assert(match_flags & MATCH_MODE_NEUTRAL);
368 if (is_imm_encodeable(op2)) {
369 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
370 new_op1 = be_transform_node(op1);
371 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
373 new_op2 = be_transform_node(op2);
374 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
375 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
376 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
378 new_op1 = be_transform_node(op1);
379 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
383 static ir_node *get_reg(ir_graph *const irg, reg_info_t *const reg)
386 /* this is already the transformed start node */
387 ir_node *const start = get_irg_start(irg);
388 assert(is_sparc_Start(start));
389 arch_register_class_t const *const cls = arch_get_irn_register_req_out(start, reg->offset)->cls;
390 reg->irn = new_r_Proj(start, cls ? cls->mode : mode_M, reg->offset);
395 static ir_node *get_g0(ir_graph *irg)
397 return get_reg(irg, &start_g0);
400 static ir_node *get_g7(ir_graph *irg)
402 return get_reg(irg, &start_g7);
405 static ir_node *make_tls_offset(dbg_info *dbgi, ir_node *block,
406 ir_entity *entity, int32_t offset)
408 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
409 ir_node *low = new_bd_sparc_Xor_imm(dbgi, block, hi, entity, offset);
413 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
416 if (get_entity_owner(entity) == get_tls_type()) {
417 ir_graph *irg = get_irn_irg(block);
418 ir_node *g7 = get_g7(irg);
419 ir_node *offsetn = make_tls_offset(dbgi, block, entity, offset);
420 ir_node *add = new_bd_sparc_Add_reg(dbgi, block, g7, offsetn);
423 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
424 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
429 typedef struct address_t {
437 * Match a load/store address
439 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
442 ir_node *ptr2 = NULL;
444 ir_entity *entity = NULL;
447 ir_node *add_right = get_Add_right(base);
448 if (is_Const(add_right)) {
449 base = get_Add_left(base);
450 offset += get_tarval_long(get_Const_tarval(add_right));
453 /* Note that we don't match sub(x, Const) or chains of adds/subs
454 * because this should all be normalized by now */
456 /* we only use the symconst if we're the only user otherwise we probably
457 * won't save anything but produce multiple sethi+or combinations with
458 * just different offsets */
459 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
460 ir_entity *sc_entity = get_SymConst_entity(base);
461 dbg_info *dbgi = get_irn_dbg_info(ptr);
462 ir_node *block = get_nodes_block(ptr);
463 ir_node *new_block = be_transform_node(block);
465 if (get_entity_owner(sc_entity) == get_tls_type()) {
469 ptr2 = make_tls_offset(dbgi, new_block, sc_entity, offset);
471 base = get_g7(get_irn_irg(base));
475 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
477 } else if (use_ptr2 && is_Add(base) && offset == 0) {
478 ptr2 = be_transform_node(get_Add_right(base));
479 base = be_transform_node(get_Add_left(base));
482 if (sparc_is_value_imm_encodeable(offset)) {
483 base = be_transform_node(base);
485 base = be_transform_node(ptr);
491 address->ptr2 = ptr2;
492 address->entity = entity;
493 address->offset = offset;
497 * Creates an sparc Add.
499 * @param node FIRM node
500 * @return the created sparc Add node
502 static ir_node *gen_Add(ir_node *node)
504 ir_mode *mode = get_irn_mode(node);
507 if (mode_is_float(mode)) {
508 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
509 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
512 /* special case: + 0x1000 can be represented as - 0x1000 */
513 right = get_Add_right(node);
514 if (is_Const(right)) {
515 ir_node *left = get_Add_left(node);
518 /* is this simple address arithmetic? then we can let the linker do
519 * the calculation. */
520 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
521 dbg_info *dbgi = get_irn_dbg_info(node);
522 ir_node *block = be_transform_node(get_nodes_block(node));
525 /* the value of use_ptr2 shouldn't matter here */
526 match_address(node, &address, false);
527 assert(is_sparc_SetHi(address.ptr));
528 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
529 address.entity, address.offset);
532 tv = get_Const_tarval(right);
533 val = get_tarval_long(tv);
535 dbg_info *dbgi = get_irn_dbg_info(node);
536 ir_node *block = be_transform_node(get_nodes_block(node));
537 ir_node *op = get_Add_left(node);
538 ir_node *new_op = be_transform_node(op);
539 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
543 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
544 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
547 static ir_node *gen_AddCC_t(ir_node *node)
549 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
550 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
553 static ir_node *gen_Proj_AddCC_t(ir_node *node)
555 long pn = get_Proj_proj(node);
556 ir_node *pred = get_Proj_pred(node);
557 ir_node *new_pred = be_transform_node(pred);
560 case pn_sparc_AddCC_t_res:
561 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
562 case pn_sparc_AddCC_t_flags:
563 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
565 panic("Invalid proj found");
569 static ir_node *gen_AddX_t(ir_node *node)
571 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
572 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
576 * Creates an sparc Sub.
578 * @param node FIRM node
579 * @return the created sparc Sub node
581 static ir_node *gen_Sub(ir_node *node)
583 ir_mode *mode = get_irn_mode(node);
585 if (mode_is_float(mode)) {
586 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
587 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
590 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
591 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
594 static ir_node *gen_SubCC_t(ir_node *node)
596 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
597 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
600 static ir_node *gen_Proj_SubCC_t(ir_node *node)
602 long pn = get_Proj_proj(node);
603 ir_node *pred = get_Proj_pred(node);
604 ir_node *new_pred = be_transform_node(pred);
607 case pn_sparc_SubCC_t_res:
608 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
609 case pn_sparc_SubCC_t_flags:
610 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
612 panic("Invalid proj found");
616 static ir_node *gen_SubX_t(ir_node *node)
618 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
619 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
622 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
623 ir_node *mem, ir_mode *mode, ir_entity *entity,
624 long offset, bool is_frame_entity)
626 unsigned bits = get_mode_size_bits(mode);
627 assert(mode_is_float(mode));
629 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
630 offset, is_frame_entity);
631 } else if (bits == 64) {
632 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
633 offset, is_frame_entity);
636 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
637 offset, is_frame_entity);
641 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
642 ir_node *ptr, ir_node *mem, ir_mode *mode,
643 ir_entity *entity, long offset,
644 bool is_frame_entity)
646 unsigned bits = get_mode_size_bits(mode);
647 assert(mode_is_float(mode));
649 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
650 offset, is_frame_entity);
651 } else if (bits == 64) {
652 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
653 offset, is_frame_entity);
656 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
657 offset, is_frame_entity);
664 * @param node the ir Load node
665 * @return the created sparc Load node
667 static ir_node *gen_Load(ir_node *node)
669 dbg_info *dbgi = get_irn_dbg_info(node);
670 ir_mode *mode = get_Load_mode(node);
671 ir_node *block = be_transform_node(get_nodes_block(node));
672 ir_node *ptr = get_Load_ptr(node);
673 ir_node *mem = get_Load_mem(node);
674 ir_node *new_mem = be_transform_node(mem);
675 ir_node *new_load = NULL;
678 if (get_Load_unaligned(node) == align_non_aligned) {
679 panic("transformation of unaligned Loads not implemented yet");
682 if (mode_is_float(mode)) {
683 match_address(ptr, &address, false);
684 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
685 address.entity, address.offset, false);
687 match_address(ptr, &address, true);
688 if (address.ptr2 != NULL) {
689 assert(address.entity == NULL && address.offset == 0);
690 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
691 address.ptr2, new_mem, mode);
693 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
694 mode, address.entity, address.offset,
698 set_irn_pinned(new_load, get_irn_pinned(node));
704 * Transforms a Store.
706 * @param node the ir Store node
707 * @return the created sparc Store node
709 static ir_node *gen_Store(ir_node *node)
711 ir_node *block = be_transform_node(get_nodes_block(node));
712 ir_node *ptr = get_Store_ptr(node);
713 ir_node *mem = get_Store_mem(node);
714 ir_node *new_mem = be_transform_node(mem);
715 ir_node *val = get_Store_value(node);
716 ir_mode *mode = get_irn_mode(val);
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_node *new_store = NULL;
721 if (get_Store_unaligned(node) == align_non_aligned) {
722 panic("transformation of unaligned Stores not implemented yet");
725 if (mode_is_float(mode)) {
726 ir_node *new_val = be_transform_node(val);
727 /* TODO: variants with reg+reg address mode */
728 match_address(ptr, &address, false);
729 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
730 mode, address.entity, address.offset, false);
733 unsigned dest_bits = get_mode_size_bits(mode);
734 while (is_downconv(node)
735 && get_mode_size_bits(get_irn_mode(node)) >= dest_bits) {
736 val = get_Conv_op(val);
738 new_val = be_transform_node(val);
740 assert(dest_bits <= 32);
741 match_address(ptr, &address, true);
742 if (address.ptr2 != NULL) {
743 assert(address.entity == NULL && address.offset == 0);
744 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
745 address.ptr2, new_mem, mode);
747 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
748 new_mem, mode, address.entity,
749 address.offset, false);
752 set_irn_pinned(new_store, get_irn_pinned(node));
758 * Creates an sparc Mul.
759 * returns the lower 32bits of the 64bit multiply result
761 * @return the created sparc Mul node
763 static ir_node *gen_Mul(ir_node *node)
765 ir_mode *mode = get_irn_mode(node);
766 if (mode_is_float(mode)) {
767 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
768 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
771 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
772 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
776 * Creates an sparc Mulh.
777 * Mulh returns the upper 32bits of a mul instruction
779 * @return the created sparc Mulh node
781 static ir_node *gen_Mulh(ir_node *node)
783 ir_mode *mode = get_irn_mode(node);
786 if (mode_is_float(mode))
787 panic("FP not supported yet");
789 if (mode_is_signed(mode)) {
790 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
791 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
793 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
794 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
798 static ir_node *gen_sign_extension_value(ir_node *node)
800 ir_node *block = get_nodes_block(node);
801 ir_node *new_block = be_transform_node(block);
802 ir_node *new_node = be_transform_node(node);
803 /* TODO: we could do some shortcuts for some value types probably.
804 * (For constants or other cases where we know the sign bit in
806 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
810 * Creates an sparc Div.
812 * @return the created sparc Div node
814 static ir_node *gen_Div(ir_node *node)
816 dbg_info *dbgi = get_irn_dbg_info(node);
817 ir_node *block = get_nodes_block(node);
818 ir_node *new_block = be_transform_node(block);
819 ir_mode *mode = get_Div_resmode(node);
820 ir_node *left = get_Div_left(node);
821 ir_node *left_low = be_transform_node(left);
822 ir_node *right = get_Div_right(node);
825 if (mode_is_float(mode)) {
826 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
827 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
830 if (mode_is_signed(mode)) {
831 ir_node *left_high = gen_sign_extension_value(left);
833 if (is_imm_encodeable(right)) {
834 int32_t immediate = get_tarval_long(get_Const_tarval(right));
835 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
838 ir_node *new_right = be_transform_node(right);
839 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
843 ir_graph *irg = get_irn_irg(node);
844 ir_node *left_high = get_g0(irg);
845 if (is_imm_encodeable(right)) {
846 int32_t immediate = get_tarval_long(get_Const_tarval(right));
847 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
850 ir_node *new_right = be_transform_node(right);
851 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
860 * Transforms a Not node.
862 * @return the created sparc Not node
864 static ir_node *gen_Not(ir_node *node)
866 ir_node *op = get_Not_op(node);
867 ir_graph *irg = get_irn_irg(node);
868 ir_node *zero = get_g0(irg);
869 dbg_info *dbgi = get_irn_dbg_info(node);
870 ir_node *block = be_transform_node(get_nodes_block(node));
871 ir_node *new_op = be_transform_node(op);
873 /* Note: Not(Eor()) is normalize in firm localopts already so
874 * we don't match it for xnor here */
876 /* Not can be represented with xnor 0, n */
877 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
880 static ir_node *gen_helper_bitop(ir_node *node,
881 new_binop_reg_func new_reg,
882 new_binop_imm_func new_imm,
883 new_binop_reg_func new_not_reg,
884 new_binop_imm_func new_not_imm,
887 ir_node *op1 = get_binop_left(node);
888 ir_node *op2 = get_binop_right(node);
890 return gen_helper_binop_args(node, op2, get_Not_op(op1),
892 new_not_reg, new_not_imm);
895 return gen_helper_binop_args(node, op1, get_Not_op(op2),
897 new_not_reg, new_not_imm);
899 if (is_Const(op2) && get_irn_n_edges(op2) == 1) {
900 ir_tarval *tv = get_Const_tarval(op2);
901 long value = get_tarval_long(tv);
902 if (!sparc_is_value_imm_encodeable(value)) {
903 long notvalue = ~value;
904 if ((notvalue & 0x3ff) == 0) {
905 ir_node *block = get_nodes_block(node);
906 ir_node *new_block = be_transform_node(block);
907 dbg_info *dbgi = get_irn_dbg_info(node);
909 = new_bd_sparc_SetHi(NULL, new_block, NULL, notvalue);
910 ir_node *new_op1 = be_transform_node(op1);
912 = new_not_reg(dbgi, new_block, new_op1, new_op2);
917 return gen_helper_binop_args(node, op1, op2,
918 flags | MATCH_COMMUTATIVE,
922 static ir_node *gen_And(ir_node *node)
924 return gen_helper_bitop(node,
925 new_bd_sparc_And_reg,
926 new_bd_sparc_And_imm,
927 new_bd_sparc_AndN_reg,
928 new_bd_sparc_AndN_imm,
932 static ir_node *gen_Or(ir_node *node)
934 return gen_helper_bitop(node,
937 new_bd_sparc_OrN_reg,
938 new_bd_sparc_OrN_imm,
942 static ir_node *gen_Eor(ir_node *node)
944 return gen_helper_bitop(node,
945 new_bd_sparc_Xor_reg,
946 new_bd_sparc_Xor_imm,
947 new_bd_sparc_XNor_reg,
948 new_bd_sparc_XNor_imm,
952 static ir_node *gen_Shl(ir_node *node)
954 ir_mode *mode = get_irn_mode(node);
955 if (get_mode_modulo_shift(mode) != 32)
956 panic("modulo_shift!=32 not supported");
957 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
960 static ir_node *gen_Shr(ir_node *node)
962 ir_mode *mode = get_irn_mode(node);
963 if (get_mode_modulo_shift(mode) != 32)
964 panic("modulo_shift!=32 not supported");
965 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
968 static ir_node *gen_Shrs(ir_node *node)
970 ir_mode *mode = get_irn_mode(node);
971 if (get_mode_modulo_shift(mode) != 32)
972 panic("modulo_shift!=32 not supported");
973 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
977 * Transforms a Minus node.
979 static ir_node *gen_Minus(ir_node *node)
981 ir_mode *mode = get_irn_mode(node);
988 if (mode_is_float(mode)) {
989 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
990 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
992 block = be_transform_node(get_nodes_block(node));
993 dbgi = get_irn_dbg_info(node);
994 op = get_Minus_op(node);
995 new_op = be_transform_node(op);
996 zero = get_g0(get_irn_irg(node));
997 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
1001 * Create an entity for a given (floating point) tarval
1003 static ir_entity *create_float_const_entity(ir_graph *const irg, ir_tarval *const tv)
1005 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1006 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
1007 ir_entity *entity = pmap_get(ir_entity, isa->constants, tv);
1008 ir_initializer_t *initializer;
1016 mode = get_tarval_mode(tv);
1017 type = get_type_for_mode(mode);
1018 glob = get_glob_type();
1019 entity = new_entity(glob, id_unique("C%u"), type);
1020 set_entity_visibility(entity, ir_visibility_private);
1021 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1023 initializer = create_initializer_tarval(tv);
1024 set_entity_initializer(entity, initializer);
1026 pmap_insert(isa->constants, tv, entity);
1030 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
1032 ir_graph *irg = get_Block_irg(block);
1033 ir_entity *entity = create_float_const_entity(irg, tv);
1034 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
1035 ir_node *mem = get_irg_no_mem(irg);
1036 ir_mode *mode = get_tarval_mode(tv);
1038 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
1039 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
1041 set_irn_pinned(new_op, op_pin_state_floats);
1045 static ir_node *create_int_const(ir_node *block, int32_t value)
1048 ir_graph *irg = get_irn_irg(block);
1050 } else if (sparc_is_value_imm_encodeable(value)) {
1051 ir_graph *irg = get_irn_irg(block);
1052 return new_bd_sparc_Or_imm(NULL, block, get_g0(irg), NULL, value);
1054 ir_node *hi = new_bd_sparc_SetHi(NULL, block, NULL, value);
1055 if ((value & 0x3ff) != 0) {
1056 return new_bd_sparc_Or_imm(NULL, block, hi, NULL, value & 0x3ff);
1063 static ir_node *gen_Const(ir_node *node)
1065 ir_node *block = be_transform_node(get_nodes_block(node));
1066 ir_mode *mode = get_irn_mode(node);
1067 dbg_info *dbgi = get_irn_dbg_info(node);
1068 ir_tarval *tv = get_Const_tarval(node);
1071 if (mode_is_float(mode)) {
1072 return gen_float_const(dbgi, block, tv);
1075 assert(get_mode_size_bits(get_tarval_mode(tv)) <= 32);
1076 val = (int32_t)get_tarval_long(tv);
1077 return create_int_const(block, val);
1080 static ir_node *gen_Switch(ir_node *node)
1082 dbg_info *dbgi = get_irn_dbg_info(node);
1083 ir_node *block = get_nodes_block(node);
1084 ir_node *new_block = be_transform_node(block);
1085 ir_graph *irg = get_irn_irg(block);
1086 ir_node *selector = get_Switch_selector(node);
1087 ir_node *new_selector = be_transform_node(selector);
1088 const ir_switch_table *table = get_Switch_table(node);
1089 unsigned n_outs = get_Switch_n_outs(node);
1090 ir_node *table_address;
1095 table = ir_switch_table_duplicate(irg, table);
1097 /* switch with smaller mode not implemented yet */
1098 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1100 ir_type *const utype = get_unknown_type();
1101 ir_entity *const entity = new_entity(utype, id_unique("TBL%u"), utype);
1102 set_entity_visibility(entity, ir_visibility_private);
1103 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1105 /* construct base address */
1106 table_address = make_address(dbgi, new_block, entity, 0);
1108 idx = new_bd_sparc_Sll_imm(dbgi, new_block, new_selector, NULL, 2);
1109 /* load from jumptable */
1110 load = new_bd_sparc_Ld_reg(dbgi, new_block, table_address, idx,
1111 get_irg_no_mem(irg),
1113 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1115 return new_bd_sparc_SwitchJmp(dbgi, new_block, address, n_outs, table, entity);
1118 static ir_node *gen_Cond(ir_node *node)
1120 ir_node *selector = get_Cond_selector(node);
1125 ir_relation relation;
1128 /* note: after lower_mode_b we are guaranteed to have a Cmp input */
1129 block = be_transform_node(get_nodes_block(node));
1130 dbgi = get_irn_dbg_info(node);
1131 cmp_left = get_Cmp_left(selector);
1132 cmp_mode = get_irn_mode(cmp_left);
1133 flag_node = be_transform_node(selector);
1134 relation = get_Cmp_relation(selector);
1135 if (mode_is_float(cmp_mode)) {
1136 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1138 bool is_unsigned = !mode_is_signed(cmp_mode);
1139 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1146 static ir_node *gen_Cmp(ir_node *node)
1148 ir_node *op1 = get_Cmp_left(node);
1149 ir_node *op2 = get_Cmp_right(node);
1150 ir_mode *cmp_mode = get_irn_mode(op1);
1151 assert(get_irn_mode(op2) == cmp_mode);
1153 if (mode_is_float(cmp_mode)) {
1154 ir_node *block = be_transform_node(get_nodes_block(node));
1155 dbg_info *dbgi = get_irn_dbg_info(node);
1156 ir_node *new_op1 = be_transform_node(op1);
1157 ir_node *new_op2 = be_transform_node(op2);
1158 unsigned bits = get_mode_size_bits(cmp_mode);
1160 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1161 } else if (bits == 64) {
1162 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1164 assert(bits == 128);
1165 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1169 /* when we compare a bitop like and,or,... with 0 then we can directly use
1170 * the bitopcc variant.
1171 * Currently we only do this when we're the only user of the node...
1173 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1175 return gen_helper_bitop(op1,
1176 new_bd_sparc_AndCCZero_reg,
1177 new_bd_sparc_AndCCZero_imm,
1178 new_bd_sparc_AndNCCZero_reg,
1179 new_bd_sparc_AndNCCZero_imm,
1181 } else if (is_Or(op1)) {
1182 return gen_helper_bitop(op1,
1183 new_bd_sparc_OrCCZero_reg,
1184 new_bd_sparc_OrCCZero_imm,
1185 new_bd_sparc_OrNCCZero_reg,
1186 new_bd_sparc_OrNCCZero_imm,
1188 } else if (is_Eor(op1)) {
1189 return gen_helper_bitop(op1,
1190 new_bd_sparc_XorCCZero_reg,
1191 new_bd_sparc_XorCCZero_imm,
1192 new_bd_sparc_XNorCCZero_reg,
1193 new_bd_sparc_XNorCCZero_imm,
1195 } else if (is_Add(op1)) {
1196 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1197 new_bd_sparc_AddCCZero_reg,
1198 new_bd_sparc_AddCCZero_imm);
1199 } else if (is_Sub(op1)) {
1200 return gen_helper_binop(op1, MATCH_NONE,
1201 new_bd_sparc_SubCCZero_reg,
1202 new_bd_sparc_SubCCZero_imm);
1203 } else if (is_Mul(op1)) {
1204 return gen_helper_binop(op1, MATCH_COMMUTATIVE,
1205 new_bd_sparc_MulCCZero_reg,
1206 new_bd_sparc_MulCCZero_imm);
1210 /* integer compare */
1211 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1212 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1216 * Transforms a SymConst node.
1218 static ir_node *gen_SymConst(ir_node *node)
1220 ir_entity *entity = get_SymConst_entity(node);
1221 dbg_info *dbgi = get_irn_dbg_info(node);
1222 ir_node *block = get_nodes_block(node);
1223 ir_node *new_block = be_transform_node(block);
1224 return make_address(dbgi, new_block, entity, 0);
1227 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1228 ir_mode *src_mode, ir_mode *dst_mode)
1230 unsigned src_bits = get_mode_size_bits(src_mode);
1231 unsigned dst_bits = get_mode_size_bits(dst_mode);
1232 if (src_bits == 32) {
1233 if (dst_bits == 64) {
1234 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1236 assert(dst_bits == 128);
1237 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1239 } else if (src_bits == 64) {
1240 if (dst_bits == 32) {
1241 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1243 assert(dst_bits == 128);
1244 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1247 assert(src_bits == 128);
1248 if (dst_bits == 32) {
1249 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1251 assert(dst_bits == 64);
1252 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1257 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1261 unsigned bits = get_mode_size_bits(src_mode);
1263 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1264 } else if (bits == 64) {
1265 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1267 assert(bits == 128);
1268 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1272 ir_graph *irg = get_irn_irg(block);
1273 ir_node *sp = get_irg_frame(irg);
1274 ir_node *nomem = get_irg_no_mem(irg);
1275 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, mode_fp,
1277 arch_add_irn_flags(stf, arch_irn_flags_spill);
1278 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1280 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1281 set_irn_pinned(stf, op_pin_state_floats);
1282 set_irn_pinned(ld, op_pin_state_floats);
1287 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1290 ir_graph *irg = get_irn_irg(block);
1291 ir_node *sp = get_irg_frame(irg);
1292 ir_node *nomem = get_irg_no_mem(irg);
1293 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1294 mode_gp, NULL, 0, true);
1295 arch_add_irn_flags(st, arch_irn_flags_spill);
1296 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1298 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1299 unsigned bits = get_mode_size_bits(dst_mode);
1300 set_irn_pinned(st, op_pin_state_floats);
1301 set_irn_pinned(ldf, op_pin_state_floats);
1304 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1305 } else if (bits == 64) {
1306 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1308 assert(bits == 128);
1309 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1313 static ir_node *gen_Conv(ir_node *node)
1315 ir_node *block = be_transform_node(get_nodes_block(node));
1316 ir_node *op = get_Conv_op(node);
1317 ir_mode *src_mode = get_irn_mode(op);
1318 ir_mode *dst_mode = get_irn_mode(node);
1319 dbg_info *dbgi = get_irn_dbg_info(node);
1322 int src_bits = get_mode_size_bits(src_mode);
1323 int dst_bits = get_mode_size_bits(dst_mode);
1325 if (src_mode == mode_b)
1326 panic("ConvB not lowered %+F", node);
1328 if (src_mode == dst_mode)
1329 return be_transform_node(op);
1331 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1332 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1334 new_op = be_transform_node(op);
1335 if (mode_is_float(src_mode)) {
1336 if (mode_is_float(dst_mode)) {
1337 /* float -> float conv */
1338 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1340 /* float -> int conv */
1341 if (!mode_is_signed(dst_mode))
1342 panic("float to unsigned not lowered");
1343 return create_ftoi(dbgi, block, new_op, src_mode);
1346 /* int -> float conv */
1347 if (src_bits < 32) {
1348 new_op = gen_extension(dbgi, block, new_op, src_mode);
1349 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1350 panic("unsigned to float not lowered!");
1352 return create_itof(dbgi, block, new_op, dst_mode);
1354 } else { /* complete in gp registers */
1355 if (src_bits >= dst_bits || dst_mode == mode_b) {
1356 /* kill unnecessary conv */
1357 return be_transform_node(op);
1360 if (be_upper_bits_clean(op, src_mode)) {
1361 return be_transform_node(op);
1363 new_op = be_transform_node(op);
1365 if (mode_is_signed(src_mode)) {
1366 return gen_sign_extension(dbgi, block, new_op, src_bits);
1368 return gen_zero_extension(dbgi, block, new_op, src_bits);
1373 static ir_node *gen_Unknown(ir_node *node)
1375 /* just produce a 0 */
1376 ir_mode *mode = get_irn_mode(node);
1377 if (mode_is_float(mode)) {
1378 ir_node *block = be_transform_node(get_nodes_block(node));
1379 return gen_float_const(NULL, block, get_mode_null(mode));
1380 } else if (mode_needs_gp_reg(mode)) {
1381 ir_graph *irg = get_irn_irg(node);
1385 panic("Unexpected Unknown mode");
1388 static void make_start_out(reg_info_t *const info, struct obstack *const obst, ir_node *const start, size_t const offset, arch_register_t const *const reg, arch_register_req_type_t const flags)
1390 info->offset = offset;
1392 arch_register_req_t const *const req = be_create_reg_req(obst, reg, arch_register_req_type_ignore | flags);
1393 arch_set_irn_register_req_out(start, offset, req);
1394 arch_set_irn_register_out(start, offset, reg);
1398 * transform the start node to the prolog code
1400 static ir_node *gen_Start(ir_node *node)
1402 ir_graph *irg = get_irn_irg(node);
1403 ir_entity *entity = get_irg_entity(irg);
1404 ir_type *function_type = get_entity_type(entity);
1405 ir_node *block = get_nodes_block(node);
1406 ir_node *new_block = be_transform_node(block);
1407 dbg_info *dbgi = get_irn_dbg_info(node);
1408 struct obstack *obst = be_get_be_obst(irg);
1413 /* start building list of start constraints */
1415 /* calculate number of outputs */
1416 n_outs = 4; /* memory, g0, g7, sp */
1417 if (!current_cconv->omit_fp)
1418 ++n_outs; /* framepointer */
1419 /* function parameters */
1420 n_outs += current_cconv->n_param_regs;
1422 if (current_cconv->omit_fp) {
1423 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1426 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1430 /* first output is memory */
1431 start_mem.offset = o;
1432 start_mem.irn = NULL;
1433 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1436 /* the zero register */
1437 make_start_out(&start_g0, obst, start, o++, &sparc_registers[REG_G0], arch_register_req_type_none);
1439 /* g7 is used for TLS data */
1440 make_start_out(&start_g7, obst, start, o++, &sparc_registers[REG_G7], arch_register_req_type_none);
1442 /* we need an output for the stackpointer */
1443 make_start_out(&start_sp, obst, start, o++, sp_reg, arch_register_req_type_produces_sp);
1445 if (!current_cconv->omit_fp) {
1446 make_start_out(&start_fp, obst, start, o++, fp_reg, arch_register_req_type_none);
1449 /* function parameters in registers */
1450 start_params_offset = o;
1451 for (i = 0; i < get_method_n_params(function_type); ++i) {
1452 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1453 const arch_register_t *reg0 = param->reg0;
1454 const arch_register_t *reg1 = param->reg1;
1456 arch_set_irn_register_req_out(start, o, reg0->single_req);
1457 arch_set_irn_register_out(start, o, reg0);
1461 arch_set_irn_register_req_out(start, o, reg1->single_req);
1462 arch_set_irn_register_out(start, o, reg1);
1466 /* we need the values of the callee saves (Note: non omit-fp mode has no
1468 start_callee_saves_offset = o;
1469 if (current_cconv->omit_fp) {
1470 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1472 for (c = 0; c < n_callee_saves; ++c) {
1473 const arch_register_t *reg = omit_fp_callee_saves[c];
1474 arch_set_irn_register_req_out(start, o, reg->single_req);
1475 arch_set_irn_register_out(start, o, reg);
1479 assert(n_outs == o);
1484 static ir_node *get_initial_sp(ir_graph *irg)
1486 return get_reg(irg, &start_sp);
1489 static ir_node *get_initial_fp(ir_graph *irg)
1491 return get_reg(irg, &start_fp);
1494 static ir_node *get_initial_mem(ir_graph *irg)
1496 return get_reg(irg, &start_mem);
1499 static ir_node *get_stack_pointer_for(ir_node *node)
1501 /* get predecessor in stack_order list */
1502 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1505 if (stack_pred == NULL) {
1506 /* first stack user in the current block. We can simply use the
1507 * initial sp_proj for it */
1508 ir_graph *irg = get_irn_irg(node);
1509 return get_initial_sp(irg);
1512 be_transform_node(stack_pred);
1513 stack = pmap_get(ir_node, node_to_stack, stack_pred);
1514 if (stack == NULL) {
1515 return get_stack_pointer_for(stack_pred);
1522 * transform a Return node into epilogue code + return statement
1524 static ir_node *gen_Return(ir_node *node)
1526 ir_node *block = get_nodes_block(node);
1527 ir_graph *irg = get_irn_irg(node);
1528 ir_node *new_block = be_transform_node(block);
1529 dbg_info *dbgi = get_irn_dbg_info(node);
1530 ir_node *mem = get_Return_mem(node);
1531 ir_node *new_mem = be_transform_node(mem);
1532 ir_node *sp = get_stack_pointer_for(node);
1533 size_t n_res = get_Return_n_ress(node);
1534 struct obstack *be_obst = be_get_be_obst(irg);
1537 const arch_register_req_t **reqs;
1542 /* estimate number of return values */
1543 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1544 if (current_cconv->omit_fp)
1545 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1547 in = ALLOCAN(ir_node*, n_ins);
1548 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1552 reqs[p] = arch_no_register_req;
1556 reqs[p] = sp_reg->single_req;
1560 for (i = 0; i < n_res; ++i) {
1561 ir_node *res_value = get_Return_res(node, i);
1562 ir_node *new_res_value = be_transform_node(res_value);
1563 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1564 assert(slot->req1 == NULL);
1565 in[p] = new_res_value;
1566 reqs[p] = slot->req0;
1570 if (current_cconv->omit_fp) {
1571 ir_node *start = get_irg_start(irg);
1572 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1573 for (i = 0; i < n_callee_saves; ++i) {
1574 const arch_register_t *reg = omit_fp_callee_saves[i];
1575 ir_mode *mode = reg->reg_class->mode;
1577 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1579 reqs[p] = reg->single_req;
1585 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1586 arch_set_irn_register_reqs_in(bereturn, reqs);
1591 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1592 ir_node *value0, ir_node *value1)
1594 ir_graph *irg = get_Block_irg(block);
1595 ir_node *sp = get_irg_frame(irg);
1596 ir_node *nomem = get_irg_no_mem(irg);
1597 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1598 mode_gp, NULL, 0, true);
1602 arch_add_irn_flags(st, arch_irn_flags_spill);
1603 set_irn_pinned(st, op_pin_state_floats);
1605 if (value1 != NULL) {
1606 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1607 mode_gp, NULL, 4, true);
1608 arch_add_irn_flags(st1, arch_irn_flags_spill);
1609 ir_node *in[2] = { st, st1 };
1610 ir_node *sync = new_r_Sync(block, 2, in);
1611 set_irn_pinned(st1, op_pin_state_floats);
1619 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1620 set_irn_pinned(ldf, op_pin_state_floats);
1622 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1625 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1626 ir_node *value, ir_mode *float_mode,
1629 int bits = get_mode_size_bits(float_mode);
1630 if (is_Const(value)) {
1631 ir_tarval *tv = get_Const_tarval(value);
1632 int32_t val = get_tarval_sub_bits(tv, 0) |
1633 (get_tarval_sub_bits(tv, 1) << 8) |
1634 (get_tarval_sub_bits(tv, 2) << 16) |
1635 (get_tarval_sub_bits(tv, 3) << 24);
1636 ir_node *valc = create_int_const(block, val);
1638 int32_t val2 = get_tarval_sub_bits(tv, 4) |
1639 (get_tarval_sub_bits(tv, 5) << 8) |
1640 (get_tarval_sub_bits(tv, 6) << 16) |
1641 (get_tarval_sub_bits(tv, 7) << 24);
1642 ir_node *valc2 = create_int_const(block, val2);
1651 ir_graph *irg = get_Block_irg(block);
1652 ir_node *stack = get_irg_frame(irg);
1653 ir_node *nomem = get_irg_no_mem(irg);
1654 ir_node *new_value = be_transform_node(value);
1655 ir_node *stf = create_stf(dbgi, block, new_value, stack, nomem,
1656 float_mode, NULL, 0, true);
1658 arch_add_irn_flags(stf, arch_irn_flags_spill);
1659 set_irn_pinned(stf, op_pin_state_floats);
1661 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1662 set_irn_pinned(ld, op_pin_state_floats);
1663 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1666 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1668 set_irn_pinned(ld, op_pin_state_floats);
1669 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1671 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1672 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1680 static ir_node *gen_Call(ir_node *node)
1682 ir_graph *irg = get_irn_irg(node);
1683 ir_node *callee = get_Call_ptr(node);
1684 ir_node *block = get_nodes_block(node);
1685 ir_node *new_block = be_transform_node(block);
1686 ir_node *mem = get_Call_mem(node);
1687 ir_node *new_mem = be_transform_node(mem);
1688 dbg_info *dbgi = get_irn_dbg_info(node);
1689 ir_type *type = get_Call_type(node);
1690 size_t n_params = get_Call_n_params(node);
1691 size_t n_ress = get_method_n_ress(type);
1692 /* max inputs: memory, callee, register arguments */
1693 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1694 struct obstack *obst = be_get_be_obst(irg);
1695 calling_convention_t *cconv
1696 = sparc_decide_calling_convention(type, NULL);
1697 size_t n_param_regs = cconv->n_param_regs;
1698 /* param-regs + mem + stackpointer + callee */
1699 unsigned max_inputs = 3 + n_param_regs;
1700 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1701 const arch_register_req_t **in_req
1702 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1706 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1707 ir_entity *entity = NULL;
1708 ir_node *new_frame = get_stack_pointer_for(node);
1709 bool aggregate_return
1710 = get_method_calling_convention(type) & cc_compound_ret;
1720 assert(n_params == get_method_n_params(type));
1722 /* construct arguments */
1725 in_req[in_arity] = arch_no_register_req;
1729 /* stack pointer input */
1730 /* construct an IncSP -> we have to always be sure that the stack is
1731 * aligned even if we don't push arguments on it */
1732 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1733 cconv->param_stack_size, 1);
1734 in_req[in_arity] = sp_reg->single_req;
1735 in[in_arity] = incsp;
1739 for (p = 0; p < n_params; ++p) {
1740 ir_node *value = get_Call_param(node, p);
1741 const reg_or_stackslot_t *param = &cconv->parameters[p];
1742 ir_type *param_type = get_method_param_type(type, p);
1743 ir_mode *mode = get_type_mode(param_type);
1744 ir_node *partial_value;
1745 ir_node *new_values[2];
1749 if (mode_is_float(mode) && param->reg0 != NULL) {
1750 unsigned size_bits = get_mode_size_bits(mode);
1751 assert(size_bits <= 64);
1752 bitcast_float_to_int(dbgi, new_block, value, mode, new_values);
1754 ir_node *new_value = be_transform_node(value);
1755 new_values[0] = new_value;
1756 new_values[1] = NULL;
1759 /* put value into registers */
1760 if (param->reg0 != NULL) {
1761 in[in_arity] = new_values[0];
1762 in_req[in_arity] = param->reg0->single_req;
1764 if (new_values[1] == NULL)
1767 if (param->reg1 != NULL) {
1768 assert(new_values[1] != NULL);
1769 in[in_arity] = new_values[1];
1770 in_req[in_arity] = param->reg1->single_req;
1775 /* we need a store if we're here */
1776 if (new_values[1] != NULL) {
1777 partial_value = new_values[1];
1780 partial_value = new_values[0];
1783 /* we need to skip over our save area when constructing the call
1784 * arguments on stack */
1785 offset = param->offset + SPARC_MIN_STACKSIZE;
1787 if (mode_is_float(mode)) {
1788 str = create_stf(dbgi, new_block, partial_value, incsp, new_mem,
1789 mode, NULL, offset, true);
1791 str = new_bd_sparc_St_imm(dbgi, new_block, partial_value, incsp,
1792 new_mem, mode, NULL, offset, true);
1794 set_irn_pinned(str, op_pin_state_floats);
1795 sync_ins[sync_arity++] = str;
1798 /* construct memory input */
1799 if (sync_arity == 0) {
1800 in[mem_pos] = new_mem;
1801 } else if (sync_arity == 1) {
1802 in[mem_pos] = sync_ins[0];
1804 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1807 if (is_SymConst(callee)) {
1808 entity = get_SymConst_entity(callee);
1810 in[in_arity] = be_transform_node(callee);
1811 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1814 assert(in_arity <= (int)max_inputs);
1821 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1823 /* create call node */
1824 if (entity != NULL) {
1825 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1826 entity, 0, aggregate_return);
1828 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1831 arch_set_irn_register_reqs_in(res, in_req);
1833 /* create output register reqs */
1835 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1836 /* add register requirements for the result regs */
1837 for (r = 0; r < n_ress; ++r) {
1838 const reg_or_stackslot_t *result_info = &cconv->results[r];
1839 const arch_register_req_t *req = result_info->req0;
1841 arch_set_irn_register_req_out(res, o++, req);
1843 assert(result_info->req1 == NULL);
1845 const unsigned *allocatable_regs = be_birg_from_irg(irg)->allocatable_regs;
1846 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1847 const arch_register_t *reg;
1848 if (!rbitset_is_set(cconv->caller_saves, i))
1850 reg = &sparc_registers[i];
1851 arch_set_irn_register_req_out(res, o, reg->single_req);
1852 if (!rbitset_is_set(allocatable_regs, reg->global_index))
1853 arch_set_irn_register_out(res, o, reg);
1856 assert(o == out_arity);
1858 /* copy pinned attribute */
1859 set_irn_pinned(res, get_irn_pinned(node));
1861 /* IncSP to destroy the call stackframe */
1862 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1863 /* if we are the last IncSP producer in a block then we have to keep
1865 * Note: This here keeps all producers which is more than necessary */
1866 add_irn_dep(incsp, res);
1869 pmap_insert(node_to_stack, node, incsp);
1871 sparc_free_calling_convention(cconv);
1875 static ir_node *gen_Sel(ir_node *node)
1877 dbg_info *dbgi = get_irn_dbg_info(node);
1878 ir_node *block = get_nodes_block(node);
1879 ir_node *new_block = be_transform_node(block);
1880 ir_node *ptr = get_Sel_ptr(node);
1881 ir_node *new_ptr = be_transform_node(ptr);
1882 ir_entity *entity = get_Sel_entity(node);
1884 /* must be the frame pointer all other sels must have been lowered
1886 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1888 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1891 static ir_node *gen_Alloc(ir_node *node)
1893 dbg_info *dbgi = get_irn_dbg_info(node);
1894 ir_node *block = get_nodes_block(node);
1895 ir_node *new_block = be_transform_node(block);
1896 ir_type *type = get_Alloc_type(node);
1897 ir_node *size = get_Alloc_count(node);
1898 ir_node *stack_pred = get_stack_pointer_for(node);
1899 ir_node *mem = get_Alloc_mem(node);
1900 ir_node *new_mem = be_transform_node(mem);
1903 if (get_Alloc_where(node) != stack_alloc)
1904 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1905 /* lowerer should have transformed all allocas to byte size */
1906 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
1907 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1909 if (is_Const(size)) {
1910 ir_tarval *tv = get_Const_tarval(size);
1911 long sizel = get_tarval_long(tv);
1913 assert((sizel & (SPARC_STACK_ALIGNMENT - 1)) == 0 && "Found Alloc with misaligned constant");
1914 subsp = new_bd_sparc_SubSP_imm(dbgi, new_block, stack_pred, new_mem, NULL, sizel);
1916 ir_node *new_size = be_transform_node(size);
1917 subsp = new_bd_sparc_SubSP_reg(dbgi, new_block, stack_pred, new_size, new_mem);
1920 ir_node *stack_proj = new_r_Proj(subsp, mode_gp, pn_sparc_SubSP_stack);
1921 arch_set_irn_register(stack_proj, sp_reg);
1922 /* If we are the last stack producer in a block, we have to keep the
1923 * stack value. This keeps all producers, which is more than necessary. */
1924 keep_alive(stack_proj);
1926 pmap_insert(node_to_stack, node, stack_proj);
1931 static ir_node *gen_Proj_Alloc(ir_node *node)
1933 ir_node *alloc = get_Proj_pred(node);
1934 ir_node *new_alloc = be_transform_node(alloc);
1935 long pn = get_Proj_proj(node);
1937 switch ((pn_Alloc)pn) {
1938 case pn_Alloc_M: return new_r_Proj(new_alloc, mode_M, pn_sparc_SubSP_M);
1939 case pn_Alloc_res: return new_r_Proj(new_alloc, mode_gp, pn_sparc_SubSP_addr);
1941 case pn_Alloc_X_regular:
1942 case pn_Alloc_X_except:
1943 panic("exception output of alloc not supported (at %+F)",
1946 panic("invalid Proj->Alloc");
1949 static ir_node *gen_Free(ir_node *node)
1951 dbg_info *dbgi = get_irn_dbg_info(node);
1952 ir_node *block = get_nodes_block(node);
1953 ir_node *new_block = be_transform_node(block);
1954 ir_type *type = get_Free_type(node);
1955 ir_node *size = get_Free_count(node);
1956 ir_node *mem = get_Free_mem(node);
1957 ir_node *new_mem = be_transform_node(mem);
1958 ir_node *stack_pred = get_stack_pointer_for(node);
1960 if (get_Alloc_where(node) != stack_alloc)
1961 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1962 /* lowerer should have transformed all allocas to byte size */
1963 if (!is_unknown_type(type) && get_type_size_bytes(type) != 1)
1964 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1966 if (is_Const(size)) {
1967 ir_tarval *tv = get_Const_tarval(size);
1968 long sizel = get_tarval_long(tv);
1969 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
1970 set_irn_dbg_info(addsp, dbgi);
1972 ir_node *new_size = be_transform_node(size);
1973 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
1974 arch_set_irn_register(addsp, sp_reg);
1977 /* if we are the last IncSP producer in a block then we have to keep
1979 * Note: This here keeps all producers which is more than necessary */
1982 pmap_insert(node_to_stack, node, addsp);
1983 /* the "result" is the unmodified sp value */
1987 static const arch_register_req_t float1_req = {
1988 arch_register_req_type_normal,
1989 &sparc_reg_classes[CLASS_sparc_fp],
1995 static const arch_register_req_t float2_req = {
1996 arch_register_req_type_normal | arch_register_req_type_aligned,
1997 &sparc_reg_classes[CLASS_sparc_fp],
2003 static const arch_register_req_t float4_req = {
2004 arch_register_req_type_normal | arch_register_req_type_aligned,
2005 &sparc_reg_classes[CLASS_sparc_fp],
2013 static const arch_register_req_t *get_float_req(ir_mode *mode)
2015 assert(mode_is_float(mode));
2016 switch (get_mode_size_bits(mode)) {
2017 case 32: return &float1_req;
2018 case 64: return &float2_req;
2019 case 128: return &float4_req;
2020 default: panic("invalid float mode");
2024 static ir_node *gen_Phi(ir_node *node)
2026 ir_mode *mode = get_irn_mode(node);
2027 const arch_register_req_t *req;
2028 if (mode_needs_gp_reg(mode)) {
2029 /* we shouldn't have any 64bit stuff around anymore */
2030 assert(get_mode_size_bits(mode) <= 32);
2031 /* all integer operations are on 32bit registers now */
2033 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2034 } else if (mode_is_float(mode)) {
2035 req = get_float_req(mode);
2037 req = arch_no_register_req;
2040 return be_transform_phi(node, req);
2044 * Transform a Proj from a Load.
2046 static ir_node *gen_Proj_Load(ir_node *node)
2048 ir_node *load = get_Proj_pred(node);
2049 ir_node *new_load = be_transform_node(load);
2050 dbg_info *dbgi = get_irn_dbg_info(node);
2051 long pn = get_Proj_proj(node);
2053 /* renumber the proj */
2054 switch (get_sparc_irn_opcode(new_load)) {
2056 /* handle all gp loads equal: they have the same proj numbers. */
2057 if (pn == pn_Load_res) {
2058 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2059 } else if (pn == pn_Load_M) {
2060 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2064 if (pn == pn_Load_res) {
2065 const sparc_load_store_attr_t *attr
2066 = get_sparc_load_store_attr_const(new_load);
2067 ir_mode *mode = attr->load_store_mode;
2068 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2069 } else if (pn == pn_Load_M) {
2070 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2076 panic("Unsupported Proj from Load");
2079 static ir_node *gen_Proj_Store(ir_node *node)
2081 ir_node *store = get_Proj_pred(node);
2082 ir_node *new_store = be_transform_node(store);
2083 long pn = get_Proj_proj(node);
2085 /* renumber the proj */
2086 switch (get_sparc_irn_opcode(new_store)) {
2088 if (pn == pn_Store_M) {
2093 if (pn == pn_Store_M) {
2100 panic("Unsupported Proj from Store");
2104 * transform Projs from a Div
2106 static ir_node *gen_Proj_Div(ir_node *node)
2108 ir_node *pred = get_Proj_pred(node);
2109 ir_node *new_pred = be_transform_node(pred);
2110 long pn = get_Proj_proj(node);
2113 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2115 } else if (is_sparc_fdiv(new_pred)) {
2116 res_mode = get_Div_resmode(pred);
2118 panic("Div transformed to something unexpected: %+F",
2121 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2122 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2123 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2124 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2127 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2129 return new_r_Proj(new_pred, mode_M, pn_sparc_SDiv_M);
2133 panic("Unsupported Proj from Div");
2136 static ir_node *get_frame_base(ir_graph *irg)
2138 if (frame_base == NULL) {
2139 if (current_cconv->omit_fp) {
2140 frame_base = get_initial_sp(irg);
2142 frame_base = get_initial_fp(irg);
2148 static ir_node *gen_Proj_Start(ir_node *node)
2150 ir_node *block = get_nodes_block(node);
2151 ir_node *new_block = be_transform_node(block);
2152 long pn = get_Proj_proj(node);
2153 /* make sure prolog is constructed */
2154 be_transform_node(get_Proj_pred(node));
2156 switch ((pn_Start) pn) {
2157 case pn_Start_X_initial_exec:
2158 /* exchange ProjX with a jump */
2159 return new_bd_sparc_Ba(NULL, new_block);
2161 ir_graph *irg = get_irn_irg(node);
2162 return get_initial_mem(irg);
2164 case pn_Start_T_args:
2165 return new_r_Bad(get_irn_irg(block), mode_T);
2166 case pn_Start_P_frame_base:
2167 return get_frame_base(get_irn_irg(block));
2169 panic("Unexpected start proj: %ld\n", pn);
2172 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2174 long pn = get_Proj_proj(node);
2175 ir_node *block = get_nodes_block(node);
2176 ir_graph *irg = get_irn_irg(node);
2177 ir_node *new_block = be_transform_node(block);
2178 ir_node *args = get_Proj_pred(node);
2179 ir_node *start = get_Proj_pred(args);
2180 ir_node *new_start = be_transform_node(start);
2181 const reg_or_stackslot_t *param;
2183 /* Proj->Proj->Start must be a method argument */
2184 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2186 param = ¤t_cconv->parameters[pn];
2188 if (param->reg0 != NULL) {
2189 /* argument transmitted in register */
2190 const arch_register_t *reg = param->reg0;
2191 ir_mode *reg_mode = reg->reg_class->mode;
2192 long new_pn = param->reg_offset + start_params_offset;
2193 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2194 bool is_float = false;
2197 ir_entity *entity = get_irg_entity(irg);
2198 ir_type *method_type = get_entity_type(entity);
2199 if (pn < (long)get_method_n_params(method_type)) {
2200 ir_type *param_type = get_method_param_type(method_type, pn);
2201 ir_mode *mode = get_type_mode(param_type);
2202 is_float = mode_is_float(mode);
2207 const arch_register_t *reg1 = param->reg1;
2208 ir_node *value1 = NULL;
2211 ir_mode *reg1_mode = reg1->reg_class->mode;
2212 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2213 } else if (param->entity != NULL) {
2214 ir_node *fp = get_initial_fp(irg);
2215 ir_node *mem = get_initial_mem(irg);
2216 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2217 mode_gp, param->entity,
2219 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2222 /* convert integer value to float */
2223 value = bitcast_int_to_float(NULL, new_block, value, value1);
2227 /* argument transmitted on stack */
2228 ir_node *mem = get_initial_mem(irg);
2229 ir_mode *mode = get_type_mode(param->type);
2230 ir_node *base = get_frame_base(irg);
2234 if (mode_is_float(mode)) {
2235 load = create_ldf(NULL, new_block, base, mem, mode,
2236 param->entity, 0, true);
2237 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2239 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2240 param->entity, 0, true);
2241 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2243 set_irn_pinned(load, op_pin_state_floats);
2249 static ir_node *gen_Proj_Call(ir_node *node)
2251 long pn = get_Proj_proj(node);
2252 ir_node *call = get_Proj_pred(node);
2253 ir_node *new_call = be_transform_node(call);
2255 switch ((pn_Call) pn) {
2257 return new_r_Proj(new_call, mode_M, 0);
2258 case pn_Call_X_regular:
2259 case pn_Call_X_except:
2260 case pn_Call_T_result:
2263 panic("Unexpected Call proj %ld\n", pn);
2266 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2268 long pn = get_Proj_proj(node);
2269 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2270 ir_node *new_call = be_transform_node(call);
2271 ir_type *function_type = get_Call_type(call);
2272 calling_convention_t *cconv
2273 = sparc_decide_calling_convention(function_type, NULL);
2274 const reg_or_stackslot_t *res = &cconv->results[pn];
2275 ir_mode *mode = get_irn_mode(node);
2276 long new_pn = 1 + res->reg_offset;
2278 assert(res->req0 != NULL && res->req1 == NULL);
2279 if (mode_needs_gp_reg(mode)) {
2282 sparc_free_calling_convention(cconv);
2284 return new_r_Proj(new_call, mode, new_pn);
2288 * Transform a Proj node.
2290 static ir_node *gen_Proj(ir_node *node)
2292 ir_node *pred = get_Proj_pred(node);
2294 switch (get_irn_opcode(pred)) {
2296 return gen_Proj_Alloc(node);
2298 return gen_Proj_Store(node);
2300 return gen_Proj_Load(node);
2302 return gen_Proj_Call(node);
2305 return be_duplicate_node(node);
2307 return gen_Proj_Div(node);
2309 return gen_Proj_Start(node);
2311 ir_node *pred_pred = get_Proj_pred(pred);
2312 if (is_Call(pred_pred)) {
2313 return gen_Proj_Proj_Call(node);
2314 } else if (is_Start(pred_pred)) {
2315 return gen_Proj_Proj_Start(node);
2320 if (is_sparc_AddCC_t(pred)) {
2321 return gen_Proj_AddCC_t(node);
2322 } else if (is_sparc_SubCC_t(pred)) {
2323 return gen_Proj_SubCC_t(node);
2325 panic("code selection didn't expect Proj after %+F\n", pred);
2332 static ir_node *gen_Jmp(ir_node *node)
2334 ir_node *block = get_nodes_block(node);
2335 ir_node *new_block = be_transform_node(block);
2336 dbg_info *dbgi = get_irn_dbg_info(node);
2338 return new_bd_sparc_Ba(dbgi, new_block);
2342 * configure transformation callbacks
2344 static void sparc_register_transformers(void)
2346 be_start_transform_setup();
2348 be_set_transform_function(op_Add, gen_Add);
2349 be_set_transform_function(op_Alloc, gen_Alloc);
2350 be_set_transform_function(op_And, gen_And);
2351 be_set_transform_function(op_Call, gen_Call);
2352 be_set_transform_function(op_Cmp, gen_Cmp);
2353 be_set_transform_function(op_Cond, gen_Cond);
2354 be_set_transform_function(op_Const, gen_Const);
2355 be_set_transform_function(op_Conv, gen_Conv);
2356 be_set_transform_function(op_Div, gen_Div);
2357 be_set_transform_function(op_Eor, gen_Eor);
2358 be_set_transform_function(op_Free, gen_Free);
2359 be_set_transform_function(op_Jmp, gen_Jmp);
2360 be_set_transform_function(op_Load, gen_Load);
2361 be_set_transform_function(op_Minus, gen_Minus);
2362 be_set_transform_function(op_Mul, gen_Mul);
2363 be_set_transform_function(op_Mulh, gen_Mulh);
2364 be_set_transform_function(op_Not, gen_Not);
2365 be_set_transform_function(op_Or, gen_Or);
2366 be_set_transform_function(op_Phi, gen_Phi);
2367 be_set_transform_function(op_Proj, gen_Proj);
2368 be_set_transform_function(op_Return, gen_Return);
2369 be_set_transform_function(op_Sel, gen_Sel);
2370 be_set_transform_function(op_Shl, gen_Shl);
2371 be_set_transform_function(op_Shr, gen_Shr);
2372 be_set_transform_function(op_Shrs, gen_Shrs);
2373 be_set_transform_function(op_Start, gen_Start);
2374 be_set_transform_function(op_Store, gen_Store);
2375 be_set_transform_function(op_Sub, gen_Sub);
2376 be_set_transform_function(op_Switch, gen_Switch);
2377 be_set_transform_function(op_SymConst, gen_SymConst);
2378 be_set_transform_function(op_Unknown, gen_Unknown);
2380 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2381 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2382 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2383 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2384 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2388 * Transform a Firm graph into a SPARC graph.
2390 void sparc_transform_graph(ir_graph *irg)
2392 ir_entity *entity = get_irg_entity(irg);
2393 ir_type *frame_type;
2395 sparc_register_transformers();
2397 node_to_stack = pmap_create();
2399 mode_gp = sparc_reg_classes[CLASS_sparc_gp].mode;
2400 mode_fp = sparc_reg_classes[CLASS_sparc_fp].mode;
2403 mode_flags = sparc_reg_classes[CLASS_sparc_flags_class].mode;
2404 assert(sparc_reg_classes[CLASS_sparc_fpflags_class].mode == mode_flags);
2408 stackorder = be_collect_stacknodes(irg);
2410 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2411 if (sparc_variadic_fixups(irg, current_cconv)) {
2412 sparc_free_calling_convention(current_cconv);
2414 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2416 sparc_create_stacklayout(irg, current_cconv);
2417 be_add_parameter_entity_stores(irg);
2419 be_transform_graph(irg, NULL);
2421 be_free_stackorder(stackorder);
2422 sparc_free_calling_convention(current_cconv);
2424 frame_type = get_irg_frame_type(irg);
2425 if (get_type_state(frame_type) == layout_undefined)
2426 default_layout_compound_type(frame_type);
2428 pmap_destroy(node_to_stack);
2429 node_to_stack = NULL;
2431 be_add_missing_keeps(irg);
2433 /* do code placement, to optimize the position of constants */
2435 /* backend expects outedges to be always on */
2439 void sparc_init_transform(void)
2441 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");