2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
32 #include "irgraph_t.h"
38 #include "iroptimize.h"
45 #include "../benode.h"
47 #include "../beutil.h"
48 #include "../betranshlp.h"
49 #include "../beabihelper.h"
50 #include "bearch_sparc_t.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_transform.h"
54 #include "sparc_new_nodes.h"
55 #include "gen_sparc_new_nodes.h"
57 #include "gen_sparc_regalloc_if.h"
58 #include "sparc_cconv.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *current_cconv = NULL;
67 static be_stackorder_t *stackorder;
68 static ir_mode *mode_gp;
69 static ir_mode *mode_flags;
70 static ir_mode *mode_fp;
71 static ir_mode *mode_fp2;
72 //static ir_mode *mode_fp4;
73 static pmap *node_to_stack;
74 static size_t start_mem_offset;
75 static ir_node *start_mem;
76 static size_t start_g0_offset;
77 static ir_node *start_g0;
78 static size_t start_sp_offset;
79 static ir_node *start_sp;
80 static size_t start_fp_offset;
81 static ir_node *start_fp;
82 static ir_node *frame_base;
83 static size_t start_params_offset;
84 static size_t start_callee_saves_offset;
86 static const arch_register_t *const omit_fp_callee_saves[] = {
87 &sparc_registers[REG_L0],
88 &sparc_registers[REG_L1],
89 &sparc_registers[REG_L2],
90 &sparc_registers[REG_L3],
91 &sparc_registers[REG_L4],
92 &sparc_registers[REG_L5],
93 &sparc_registers[REG_L6],
94 &sparc_registers[REG_L7],
95 &sparc_registers[REG_I0],
96 &sparc_registers[REG_I1],
97 &sparc_registers[REG_I2],
98 &sparc_registers[REG_I3],
99 &sparc_registers[REG_I4],
100 &sparc_registers[REG_I5],
103 static inline bool mode_needs_gp_reg(ir_mode *mode)
105 if (mode_is_int(mode) || mode_is_reference(mode)) {
106 /* we should only see 32bit code */
107 assert(get_mode_size_bits(mode) <= 32);
114 * Create an And that will zero out upper bits.
116 * @param dbgi debug info
117 * @param block the basic block
118 * @param op the original node
119 * @param src_bits number of lower bits that will remain
121 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
125 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
126 } else if (src_bits == 16) {
127 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
128 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
131 panic("zero extension only supported for 8 and 16 bits");
136 * Generate code for a sign extension.
138 * @param dbgi debug info
139 * @param block the basic block
140 * @param op the original node
141 * @param src_bits number of lower bits that will remain
143 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
146 int shift_width = 32 - src_bits;
147 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
148 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
153 * returns true if it is assured, that the upper bits of a node are "clean"
154 * which means for a 16 or 8 bit value, that the upper bits in the register
155 * are 0 for unsigned and a copy of the last significant bit for signed
158 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
160 (void) transformed_node;
167 * Extend a value to 32 bit signed/unsigned depending on its mode.
169 * @param dbgi debug info
170 * @param block the basic block
171 * @param op the original node
172 * @param orig_mode the original mode of op
174 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
177 int bits = get_mode_size_bits(orig_mode);
181 if (mode_is_signed(orig_mode)) {
182 return gen_sign_extension(dbgi, block, op, bits);
184 return gen_zero_extension(dbgi, block, op, bits);
190 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
191 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
192 influence the significant lower bit at
193 all (for cases where mode < 32bit) */
195 ENUM_BITSET(match_flags_t)
197 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
198 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
199 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
200 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
203 * checks if a node's value can be encoded as a immediate
205 static bool is_imm_encodeable(const ir_node *node)
211 value = get_tarval_long(get_Const_tarval(node));
212 return sparc_is_value_imm_encodeable(value);
215 static bool needs_extension(ir_mode *mode)
217 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
221 * Check, if a given node is a Down-Conv, ie. a integer Conv
222 * from a mode with a mode with more bits to a mode with lesser bits.
223 * Moreover, we return only true if the node has not more than 1 user.
225 * @param node the node
226 * @return non-zero if node is a Down-Conv
228 static bool is_downconv(const ir_node *node)
236 src_mode = get_irn_mode(get_Conv_op(node));
237 dest_mode = get_irn_mode(node);
239 mode_needs_gp_reg(src_mode) &&
240 mode_needs_gp_reg(dest_mode) &&
241 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
244 static ir_node *sparc_skip_downconv(ir_node *node)
246 while (is_downconv(node)) {
247 node = get_Conv_op(node);
253 * helper function for binop operations
255 * @param new_reg register generation function ptr
256 * @param new_imm immediate generation function ptr
258 static ir_node *gen_helper_binop_args(ir_node *node,
259 ir_node *op1, ir_node *op2,
261 new_binop_reg_func new_reg,
262 new_binop_imm_func new_imm)
264 dbg_info *dbgi = get_irn_dbg_info(node);
265 ir_node *block = be_transform_node(get_nodes_block(node));
271 if (flags & MATCH_MODE_NEUTRAL) {
272 op1 = sparc_skip_downconv(op1);
273 op2 = sparc_skip_downconv(op2);
275 mode1 = get_irn_mode(op1);
276 mode2 = get_irn_mode(op2);
277 /* we shouldn't see 64bit code */
278 assert(get_mode_size_bits(mode1) <= 32);
279 assert(get_mode_size_bits(mode2) <= 32);
281 if (is_imm_encodeable(op2)) {
282 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
283 new_op1 = be_transform_node(op1);
284 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
285 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
287 return new_imm(dbgi, block, new_op1, NULL, immediate);
289 new_op2 = be_transform_node(op2);
290 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
291 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
294 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
295 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
296 return new_imm(dbgi, block, new_op2, NULL, immediate);
299 new_op1 = be_transform_node(op1);
300 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
301 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
303 return new_reg(dbgi, block, new_op1, new_op2);
306 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
307 new_binop_reg_func new_reg,
308 new_binop_imm_func new_imm)
310 ir_node *op1 = get_binop_left(node);
311 ir_node *op2 = get_binop_right(node);
312 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
316 * helper function for FP binop operations
318 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
319 new_binop_fp_func new_func_single,
320 new_binop_fp_func new_func_double,
321 new_binop_fp_func new_func_quad)
323 ir_node *block = be_transform_node(get_nodes_block(node));
324 ir_node *op1 = get_binop_left(node);
325 ir_node *new_op1 = be_transform_node(op1);
326 ir_node *op2 = get_binop_right(node);
327 ir_node *new_op2 = be_transform_node(op2);
328 dbg_info *dbgi = get_irn_dbg_info(node);
329 unsigned bits = get_mode_size_bits(mode);
333 return new_func_single(dbgi, block, new_op1, new_op2, mode);
335 return new_func_double(dbgi, block, new_op1, new_op2, mode);
337 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
341 panic("unsupported mode %+F for float op", mode);
344 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
345 new_unop_fp_func new_func_single,
346 new_unop_fp_func new_func_double,
347 new_unop_fp_func new_func_quad)
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 ir_node *op = get_unop_op(node);
351 ir_node *new_op = be_transform_node(op);
352 dbg_info *dbgi = get_irn_dbg_info(node);
353 unsigned bits = get_mode_size_bits(mode);
357 return new_func_single(dbgi, block, new_op, mode);
359 return new_func_double(dbgi, block, new_op, mode);
361 return new_func_quad(dbgi, block, new_op, mode);
365 panic("unsupported mode %+F for float op", mode);
368 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
369 ir_node *op1, ir_node *flags,
370 ir_entity *imm_entity, int32_t imm);
372 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
373 ir_node *op1, ir_node *op2,
376 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
377 new_binopx_reg_func new_binopx_reg,
378 new_binopx_imm_func new_binopx_imm)
380 dbg_info *dbgi = get_irn_dbg_info(node);
381 ir_node *block = be_transform_node(get_nodes_block(node));
382 ir_node *op1 = get_irn_n(node, 0);
383 ir_node *op2 = get_irn_n(node, 1);
384 ir_node *flags = get_irn_n(node, 2);
385 ir_node *new_flags = be_transform_node(flags);
389 /* only support for mode-neutral implemented so far */
390 assert(match_flags & MATCH_MODE_NEUTRAL);
392 if (is_imm_encodeable(op2)) {
393 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
394 new_op1 = be_transform_node(op1);
395 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
397 new_op2 = be_transform_node(op2);
398 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
399 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
400 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
402 new_op1 = be_transform_node(op1);
403 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
407 static ir_node *get_g0(ir_graph *irg)
409 if (start_g0 == NULL) {
410 /* this is already the transformed start node */
411 ir_node *start = get_irg_start(irg);
412 assert(is_sparc_Start(start));
413 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
418 typedef struct address_t {
426 * Match a load/store address
428 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
431 ir_node *ptr2 = NULL;
433 ir_entity *entity = NULL;
436 ir_node *add_right = get_Add_right(base);
437 if (is_Const(add_right)) {
438 base = get_Add_left(base);
439 offset += get_tarval_long(get_Const_tarval(add_right));
442 /* Note that we don't match sub(x, Const) or chains of adds/subs
443 * because this should all be normalized by now */
445 /* we only use the symconst if we're the only user otherwise we probably
446 * won't save anything but produce multiple sethi+or combinations with
447 * just different offsets */
448 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
449 dbg_info *dbgi = get_irn_dbg_info(ptr);
450 ir_node *block = get_nodes_block(ptr);
451 ir_node *new_block = be_transform_node(block);
452 entity = get_SymConst_entity(base);
453 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
454 } else if (use_ptr2 && is_Add(base) && entity == NULL && offset == 0) {
455 ptr2 = be_transform_node(get_Add_right(base));
456 base = be_transform_node(get_Add_left(base));
458 if (sparc_is_value_imm_encodeable(offset)) {
459 base = be_transform_node(base);
461 base = be_transform_node(ptr);
467 address->ptr2 = ptr2;
468 address->entity = entity;
469 address->offset = offset;
473 * Creates an sparc Add.
475 * @param node FIRM node
476 * @return the created sparc Add node
478 static ir_node *gen_Add(ir_node *node)
480 ir_mode *mode = get_irn_mode(node);
483 if (mode_is_float(mode)) {
484 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
485 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
488 /* special case: + 0x1000 can be represented as - 0x1000 */
489 right = get_Add_right(node);
490 if (is_Const(right)) {
491 ir_node *left = get_Add_left(node);
494 /* is this simple address arithmetic? then we can let the linker do
495 * the calculation. */
496 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
497 dbg_info *dbgi = get_irn_dbg_info(node);
498 ir_node *block = be_transform_node(get_nodes_block(node));
501 /* the value of use_ptr2 shouldn't matter here */
502 match_address(node, &address, false);
503 assert(is_sparc_SetHi(address.ptr));
504 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
505 address.entity, address.offset);
508 tv = get_Const_tarval(right);
509 val = get_tarval_long(tv);
511 dbg_info *dbgi = get_irn_dbg_info(node);
512 ir_node *block = be_transform_node(get_nodes_block(node));
513 ir_node *op = get_Add_left(node);
514 ir_node *new_op = be_transform_node(op);
515 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
519 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
520 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
523 static ir_node *gen_AddCC_t(ir_node *node)
525 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
526 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
529 static ir_node *gen_Proj_AddCC_t(ir_node *node)
531 long pn = get_Proj_proj(node);
532 ir_node *pred = get_Proj_pred(node);
533 ir_node *new_pred = be_transform_node(pred);
536 case pn_sparc_AddCC_t_res:
537 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
538 case pn_sparc_AddCC_t_flags:
539 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
541 panic("Invalid AddCC_t proj found");
545 static ir_node *gen_AddX_t(ir_node *node)
547 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
548 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
552 * Creates an sparc Sub.
554 * @param node FIRM node
555 * @return the created sparc Sub node
557 static ir_node *gen_Sub(ir_node *node)
559 ir_mode *mode = get_irn_mode(node);
561 if (mode_is_float(mode)) {
562 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
563 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
566 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
567 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
570 static ir_node *gen_SubCC_t(ir_node *node)
572 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
573 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
576 static ir_node *gen_Proj_SubCC_t(ir_node *node)
578 long pn = get_Proj_proj(node);
579 ir_node *pred = get_Proj_pred(node);
580 ir_node *new_pred = be_transform_node(pred);
583 case pn_sparc_SubCC_t_res:
584 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
585 case pn_sparc_SubCC_t_flags:
586 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
588 panic("Invalid SubCC_t proj found");
592 static ir_node *gen_SubX_t(ir_node *node)
594 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
595 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
598 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
599 ir_node *mem, ir_mode *mode, ir_entity *entity,
600 long offset, bool is_frame_entity)
602 unsigned bits = get_mode_size_bits(mode);
603 assert(mode_is_float(mode));
605 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
606 offset, is_frame_entity);
607 } else if (bits == 64) {
608 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
609 offset, is_frame_entity);
612 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
613 offset, is_frame_entity);
617 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
618 ir_node *ptr, ir_node *mem, ir_mode *mode,
619 ir_entity *entity, long offset,
620 bool is_frame_entity)
622 unsigned bits = get_mode_size_bits(mode);
623 assert(mode_is_float(mode));
625 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
626 offset, is_frame_entity);
627 } else if (bits == 64) {
628 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
629 offset, is_frame_entity);
632 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
633 offset, is_frame_entity);
640 * @param node the ir Load node
641 * @return the created sparc Load node
643 static ir_node *gen_Load(ir_node *node)
645 dbg_info *dbgi = get_irn_dbg_info(node);
646 ir_mode *mode = get_Load_mode(node);
647 ir_node *block = be_transform_node(get_nodes_block(node));
648 ir_node *ptr = get_Load_ptr(node);
649 ir_node *mem = get_Load_mem(node);
650 ir_node *new_mem = be_transform_node(mem);
651 ir_node *new_load = NULL;
654 if (get_Load_unaligned(node) == align_non_aligned) {
655 panic("sparc: transformation of unaligned Loads not implemented yet");
658 if (mode_is_float(mode)) {
659 match_address(ptr, &address, false);
660 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
661 address.entity, address.offset, false);
663 match_address(ptr, &address, true);
664 if (address.ptr2 != NULL) {
665 assert(address.entity == NULL && address.offset == 0);
666 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
667 address.ptr2, new_mem, mode);
669 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
670 mode, address.entity, address.offset,
674 set_irn_pinned(new_load, get_irn_pinned(node));
680 * Transforms a Store.
682 * @param node the ir Store node
683 * @return the created sparc Store node
685 static ir_node *gen_Store(ir_node *node)
687 ir_node *block = be_transform_node(get_nodes_block(node));
688 ir_node *ptr = get_Store_ptr(node);
689 ir_node *mem = get_Store_mem(node);
690 ir_node *new_mem = be_transform_node(mem);
691 ir_node *val = get_Store_value(node);
692 ir_node *new_val = be_transform_node(val);
693 ir_mode *mode = get_irn_mode(val);
694 dbg_info *dbgi = get_irn_dbg_info(node);
695 ir_node *new_store = NULL;
698 if (get_Store_unaligned(node) == align_non_aligned) {
699 panic("sparc: transformation of unaligned Stores not implemented yet");
702 if (mode_is_float(mode)) {
703 /* TODO: variants with reg+reg address mode */
704 match_address(ptr, &address, false);
705 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
706 mode, address.entity, address.offset, false);
708 assert(get_mode_size_bits(mode) <= 32);
709 match_address(ptr, &address, true);
710 if (address.ptr2 != NULL) {
711 assert(address.entity == NULL && address.offset == 0);
712 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
713 address.ptr2, new_mem, mode);
715 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
716 new_mem, mode, address.entity,
717 address.offset, false);
720 set_irn_pinned(new_store, get_irn_pinned(node));
726 * Creates an sparc Mul.
727 * returns the lower 32bits of the 64bit multiply result
729 * @return the created sparc Mul node
731 static ir_node *gen_Mul(ir_node *node)
733 ir_mode *mode = get_irn_mode(node);
734 if (mode_is_float(mode)) {
735 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
736 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
739 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
740 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
744 * Creates an sparc Mulh.
745 * Mulh returns the upper 32bits of a mul instruction
747 * @return the created sparc Mulh node
749 static ir_node *gen_Mulh(ir_node *node)
751 ir_mode *mode = get_irn_mode(node);
754 if (mode_is_float(mode))
755 panic("FP not supported yet");
757 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_Mulh_reg, new_bd_sparc_Mulh_imm);
758 return new_r_Proj(mul, mode_gp, pn_sparc_Mulh_low);
761 static ir_node *gen_sign_extension_value(ir_node *node)
763 ir_node *block = get_nodes_block(node);
764 ir_node *new_block = be_transform_node(block);
765 ir_node *new_node = be_transform_node(node);
766 /* TODO: we could do some shortcuts for some value types probably.
767 * (For constants or other cases where we know the sign bit in
769 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
773 * Creates an sparc Div.
775 * @return the created sparc Div node
777 static ir_node *gen_Div(ir_node *node)
779 dbg_info *dbgi = get_irn_dbg_info(node);
780 ir_node *block = get_nodes_block(node);
781 ir_node *new_block = be_transform_node(block);
782 ir_mode *mode = get_Div_resmode(node);
783 ir_node *left = get_Div_left(node);
784 ir_node *left_low = be_transform_node(left);
785 ir_node *right = get_Div_right(node);
788 if (mode_is_float(mode)) {
789 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
790 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
793 if (mode_is_signed(mode)) {
794 ir_node *left_high = gen_sign_extension_value(left);
796 if (is_imm_encodeable(right)) {
797 int32_t immediate = get_tarval_long(get_Const_tarval(right));
798 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
801 ir_node *new_right = be_transform_node(right);
802 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
806 ir_graph *irg = get_irn_irg(node);
807 ir_node *left_high = get_g0(irg);
808 if (is_imm_encodeable(right)) {
809 int32_t immediate = get_tarval_long(get_Const_tarval(right));
810 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
813 ir_node *new_right = be_transform_node(right);
814 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
823 * Transforms a Not node.
825 * @return the created sparc Not node
827 static ir_node *gen_Not(ir_node *node)
829 ir_node *op = get_Not_op(node);
830 ir_graph *irg = get_irn_irg(node);
831 ir_node *zero = get_g0(irg);
832 dbg_info *dbgi = get_irn_dbg_info(node);
833 ir_node *block = be_transform_node(get_nodes_block(node));
834 ir_node *new_op = be_transform_node(op);
836 /* Note: Not(Eor()) is normalize in firm localopts already so
837 * we don't match it for xnor here */
839 /* Not can be represented with xnor 0, n */
840 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
843 static ir_node *gen_helper_bitop(ir_node *node,
844 new_binop_reg_func new_reg,
845 new_binop_imm_func new_imm,
846 new_binop_reg_func new_not_reg,
847 new_binop_imm_func new_not_imm)
849 ir_node *op1 = get_binop_left(node);
850 ir_node *op2 = get_binop_right(node);
852 return gen_helper_binop_args(node, op2, get_Not_op(op1),
854 new_not_reg, new_not_imm);
857 return gen_helper_binop_args(node, op1, get_Not_op(op2),
859 new_not_reg, new_not_imm);
861 return gen_helper_binop_args(node, op1, op2,
862 MATCH_MODE_NEUTRAL | MATCH_COMMUTATIVE,
866 static ir_node *gen_And(ir_node *node)
868 return gen_helper_bitop(node,
869 new_bd_sparc_And_reg,
870 new_bd_sparc_And_imm,
871 new_bd_sparc_AndN_reg,
872 new_bd_sparc_AndN_imm);
875 static ir_node *gen_Or(ir_node *node)
877 return gen_helper_bitop(node,
880 new_bd_sparc_OrN_reg,
881 new_bd_sparc_OrN_imm);
884 static ir_node *gen_Eor(ir_node *node)
886 return gen_helper_bitop(node,
887 new_bd_sparc_Xor_reg,
888 new_bd_sparc_Xor_imm,
889 new_bd_sparc_XNor_reg,
890 new_bd_sparc_XNor_imm);
893 static ir_node *gen_Shl(ir_node *node)
895 ir_mode *mode = get_irn_mode(node);
896 if (get_mode_modulo_shift(mode) != 32)
897 panic("modulo_shift!=32 not supported by sparc backend");
898 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
901 static ir_node *gen_Shr(ir_node *node)
903 ir_mode *mode = get_irn_mode(node);
904 if (get_mode_modulo_shift(mode) != 32)
905 panic("modulo_shift!=32 not supported by sparc backend");
906 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
909 static ir_node *gen_Shrs(ir_node *node)
911 ir_mode *mode = get_irn_mode(node);
912 if (get_mode_modulo_shift(mode) != 32)
913 panic("modulo_shift!=32 not supported by sparc backend");
914 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
918 * Transforms a Minus node.
920 static ir_node *gen_Minus(ir_node *node)
922 ir_mode *mode = get_irn_mode(node);
929 if (mode_is_float(mode)) {
930 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
931 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
933 block = be_transform_node(get_nodes_block(node));
934 dbgi = get_irn_dbg_info(node);
935 op = get_Minus_op(node);
936 new_op = be_transform_node(op);
937 zero = get_g0(get_irn_irg(node));
938 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
942 * Create an entity for a given (floating point) tarval
944 static ir_entity *create_float_const_entity(ir_tarval *tv)
946 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
947 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
948 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
949 ir_initializer_t *initializer;
957 mode = get_tarval_mode(tv);
958 type = get_type_for_mode(mode);
959 glob = get_glob_type();
960 entity = new_entity(glob, id_unique("C%u"), type);
961 set_entity_visibility(entity, ir_visibility_private);
962 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
964 initializer = create_initializer_tarval(tv);
965 set_entity_initializer(entity, initializer);
967 pmap_insert(isa->constants, tv, entity);
971 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
973 ir_entity *entity = create_float_const_entity(tv);
974 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
975 ir_node *mem = get_irg_no_mem(current_ir_graph);
976 ir_mode *mode = get_tarval_mode(tv);
978 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
979 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
981 set_irn_pinned(new_op, op_pin_state_floats);
985 static ir_node *gen_Const(ir_node *node)
987 ir_node *block = be_transform_node(get_nodes_block(node));
988 ir_mode *mode = get_irn_mode(node);
989 dbg_info *dbgi = get_irn_dbg_info(node);
990 ir_tarval *tv = get_Const_tarval(node);
993 if (mode_is_float(mode)) {
994 return gen_float_const(dbgi, block, tv);
997 value = get_tarval_long(tv);
999 return get_g0(get_irn_irg(node));
1000 } else if (sparc_is_value_imm_encodeable(value)) {
1001 ir_graph *irg = get_irn_irg(node);
1002 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1004 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1005 if ((value & 0x3ff) != 0) {
1006 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1013 static ir_mode *get_cmp_mode(ir_node *b_value)
1017 if (!is_Cmp(b_value))
1018 panic("can't determine cond signednes (no cmp)");
1019 op = get_Cmp_left(b_value);
1020 return get_irn_mode(op);
1023 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
1026 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
1027 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
1029 if (get_entity_owner(entity) == get_tls_type())
1030 panic("thread local storage not supported yet in sparc backend");
1034 static ir_node *gen_SwitchJmp(ir_node *node)
1036 dbg_info *dbgi = get_irn_dbg_info(node);
1037 ir_node *block = be_transform_node(get_nodes_block(node));
1038 ir_node *selector = get_Cond_selector(node);
1039 ir_node *new_selector = be_transform_node(selector);
1040 long default_pn = get_Cond_default_proj(node);
1042 ir_node *table_address;
1047 /* switch with smaller mode not implemented yet */
1048 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1050 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1051 set_entity_visibility(entity, ir_visibility_private);
1052 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1054 /* construct base address */
1055 table_address = make_address(dbgi, block, entity, 0);
1057 idx = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
1058 /* load from jumptable */
1059 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, idx,
1060 get_irg_no_mem(current_ir_graph),
1062 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1064 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
1067 static ir_node *gen_Cond(ir_node *node)
1069 ir_node *selector = get_Cond_selector(node);
1070 ir_mode *mode = get_irn_mode(selector);
1075 ir_relation relation;
1078 // switch/case jumps
1079 if (mode != mode_b) {
1080 return gen_SwitchJmp(node);
1083 // regular if/else jumps
1084 assert(is_Cmp(selector));
1086 cmp_mode = get_cmp_mode(selector);
1088 block = be_transform_node(get_nodes_block(node));
1089 dbgi = get_irn_dbg_info(node);
1090 flag_node = be_transform_node(selector);
1091 relation = get_Cmp_relation(selector);
1092 is_unsigned = !mode_is_signed(cmp_mode);
1093 if (mode_is_float(cmp_mode)) {
1094 assert(!is_unsigned);
1095 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1097 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1104 static ir_node *gen_Cmp(ir_node *node)
1106 ir_node *op1 = get_Cmp_left(node);
1107 ir_node *op2 = get_Cmp_right(node);
1108 ir_mode *cmp_mode = get_irn_mode(op1);
1109 assert(get_irn_mode(op2) == cmp_mode);
1111 if (mode_is_float(cmp_mode)) {
1112 ir_node *block = be_transform_node(get_nodes_block(node));
1113 dbg_info *dbgi = get_irn_dbg_info(node);
1114 ir_node *new_op1 = be_transform_node(op1);
1115 ir_node *new_op2 = be_transform_node(op2);
1116 unsigned bits = get_mode_size_bits(cmp_mode);
1118 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1119 } else if (bits == 64) {
1120 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1122 assert(bits == 128);
1123 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1127 /* when we compare a bitop like and,or,... with 0 then we can directly use
1128 * the bitopcc variant.
1129 * Currently we only do this when we're the only user of the node...
1131 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1133 return gen_helper_bitop(op1,
1134 new_bd_sparc_AndCCZero_reg,
1135 new_bd_sparc_AndCCZero_imm,
1136 new_bd_sparc_AndNCCZero_reg,
1137 new_bd_sparc_AndNCCZero_imm);
1138 } else if (is_Or(op1)) {
1139 return gen_helper_bitop(op1,
1140 new_bd_sparc_OrCCZero_reg,
1141 new_bd_sparc_OrCCZero_imm,
1142 new_bd_sparc_OrNCCZero_reg,
1143 new_bd_sparc_OrNCCZero_imm);
1144 } else if (is_Eor(op1)) {
1145 return gen_helper_bitop(op1,
1146 new_bd_sparc_XorCCZero_reg,
1147 new_bd_sparc_XorCCZero_imm,
1148 new_bd_sparc_XNorCCZero_reg,
1149 new_bd_sparc_XNorCCZero_imm);
1153 /* integer compare */
1154 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1155 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1159 * Transforms a SymConst node.
1161 static ir_node *gen_SymConst(ir_node *node)
1163 ir_entity *entity = get_SymConst_entity(node);
1164 dbg_info *dbgi = get_irn_dbg_info(node);
1165 ir_node *block = get_nodes_block(node);
1166 ir_node *new_block = be_transform_node(block);
1167 return make_address(dbgi, new_block, entity, 0);
1170 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1171 ir_mode *src_mode, ir_mode *dst_mode)
1173 unsigned src_bits = get_mode_size_bits(src_mode);
1174 unsigned dst_bits = get_mode_size_bits(dst_mode);
1175 if (src_bits == 32) {
1176 if (dst_bits == 64) {
1177 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1179 assert(dst_bits == 128);
1180 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1182 } else if (src_bits == 64) {
1183 if (dst_bits == 32) {
1184 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1186 assert(dst_bits == 128);
1187 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1190 assert(src_bits == 128);
1191 if (dst_bits == 32) {
1192 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1194 assert(dst_bits == 64);
1195 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1200 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1204 unsigned bits = get_mode_size_bits(src_mode);
1206 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1207 } else if (bits == 64) {
1208 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1210 assert(bits == 128);
1211 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1215 ir_graph *irg = get_irn_irg(block);
1216 ir_node *sp = get_irg_frame(irg);
1217 ir_node *nomem = get_irg_no_mem(irg);
1218 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1220 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1222 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1223 set_irn_pinned(stf, op_pin_state_floats);
1224 set_irn_pinned(ld, op_pin_state_floats);
1229 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1232 ir_graph *irg = get_irn_irg(block);
1233 ir_node *sp = get_irg_frame(irg);
1234 ir_node *nomem = get_irg_no_mem(irg);
1235 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1236 mode_gp, NULL, 0, true);
1237 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1239 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1240 unsigned bits = get_mode_size_bits(dst_mode);
1241 set_irn_pinned(st, op_pin_state_floats);
1242 set_irn_pinned(ldf, op_pin_state_floats);
1245 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1246 } else if (bits == 64) {
1247 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1249 assert(bits == 128);
1250 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1254 static ir_node *gen_Conv(ir_node *node)
1256 ir_node *block = be_transform_node(get_nodes_block(node));
1257 ir_node *op = get_Conv_op(node);
1258 ir_mode *src_mode = get_irn_mode(op);
1259 ir_mode *dst_mode = get_irn_mode(node);
1260 dbg_info *dbgi = get_irn_dbg_info(node);
1263 int src_bits = get_mode_size_bits(src_mode);
1264 int dst_bits = get_mode_size_bits(dst_mode);
1266 if (src_mode == mode_b)
1267 panic("ConvB not lowered %+F", node);
1269 new_op = be_transform_node(op);
1270 if (src_mode == dst_mode)
1273 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1274 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1276 if (mode_is_float(src_mode)) {
1277 if (mode_is_float(dst_mode)) {
1278 /* float -> float conv */
1279 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1281 /* float -> int conv */
1282 if (!mode_is_signed(dst_mode))
1283 panic("float to unsigned not implemented yet");
1284 return create_ftoi(dbgi, block, new_op, src_mode);
1287 /* int -> float conv */
1288 if (src_bits < 32) {
1289 new_op = gen_extension(dbgi, block, new_op, src_mode);
1290 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1291 panic("unsigned to float not lowered!");
1293 return create_itof(dbgi, block, new_op, dst_mode);
1295 } else if (src_mode == mode_b) {
1296 panic("ConvB not lowered %+F", node);
1297 } else { /* complete in gp registers */
1301 if (src_bits == dst_bits) {
1302 /* kill unnecessary conv */
1306 if (src_bits < dst_bits) {
1307 min_bits = src_bits;
1308 min_mode = src_mode;
1310 min_bits = dst_bits;
1311 min_mode = dst_mode;
1314 if (upper_bits_clean(new_op, min_mode)) {
1318 if (mode_is_signed(min_mode)) {
1319 return gen_sign_extension(dbgi, block, new_op, min_bits);
1321 return gen_zero_extension(dbgi, block, new_op, min_bits);
1326 static ir_node *gen_Unknown(ir_node *node)
1328 /* just produce a 0 */
1329 ir_mode *mode = get_irn_mode(node);
1330 if (mode_is_float(mode)) {
1331 ir_node *block = be_transform_node(get_nodes_block(node));
1332 return gen_float_const(NULL, block, get_mode_null(mode));
1333 } else if (mode_needs_gp_reg(mode)) {
1334 ir_graph *irg = get_irn_irg(node);
1338 panic("Unexpected Unknown mode");
1342 * transform the start node to the prolog code
1344 static ir_node *gen_Start(ir_node *node)
1346 ir_graph *irg = get_irn_irg(node);
1347 ir_entity *entity = get_irg_entity(irg);
1348 ir_type *function_type = get_entity_type(entity);
1349 ir_node *block = get_nodes_block(node);
1350 ir_node *new_block = be_transform_node(block);
1351 dbg_info *dbgi = get_irn_dbg_info(node);
1352 struct obstack *obst = be_get_be_obst(irg);
1353 const arch_register_req_t *req;
1359 /* start building list of start constraints */
1360 assert(obstack_object_size(obst) == 0);
1362 /* calculate number of outputs */
1363 n_outs = 3; /* memory, zero, sp */
1364 if (!current_cconv->omit_fp)
1365 ++n_outs; /* framepointer */
1366 /* function parameters */
1367 n_outs += current_cconv->n_param_regs;
1369 if (current_cconv->omit_fp) {
1370 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1373 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1377 /* first output is memory */
1378 start_mem_offset = o;
1379 arch_set_out_register_req(start, o, arch_no_register_req);
1382 /* the zero register */
1383 start_g0_offset = o;
1384 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1385 arch_register_req_type_ignore);
1386 arch_set_out_register_req(start, o, req);
1387 arch_irn_set_register(start, o, &sparc_registers[REG_G0]);
1390 /* we need an output for the stackpointer */
1391 start_sp_offset = o;
1392 req = be_create_reg_req(obst, sp_reg,
1393 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1394 arch_set_out_register_req(start, o, req);
1395 arch_irn_set_register(start, o, sp_reg);
1398 if (!current_cconv->omit_fp) {
1399 start_fp_offset = o;
1400 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1401 arch_set_out_register_req(start, o, req);
1402 arch_irn_set_register(start, o, fp_reg);
1406 /* function parameters in registers */
1407 start_params_offset = o;
1408 for (i = 0; i < get_method_n_params(function_type); ++i) {
1409 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1410 const arch_register_t *reg0 = param->reg0;
1411 const arch_register_t *reg1 = param->reg1;
1413 arch_set_out_register_req(start, o, reg0->single_req);
1414 arch_irn_set_register(start, o, reg0);
1418 arch_set_out_register_req(start, o, reg1->single_req);
1419 arch_irn_set_register(start, o, reg1);
1423 /* we need the values of the callee saves (Note: non omit-fp mode has no
1425 start_callee_saves_offset = o;
1426 if (current_cconv->omit_fp) {
1427 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1429 for (c = 0; c < n_callee_saves; ++c) {
1430 const arch_register_t *reg = omit_fp_callee_saves[c];
1431 arch_set_out_register_req(start, o, reg->single_req);
1432 arch_irn_set_register(start, o, reg);
1436 assert(n_outs == o);
1441 static ir_node *get_initial_sp(ir_graph *irg)
1443 if (start_sp == NULL) {
1444 ir_node *start = get_irg_start(irg);
1445 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1450 static ir_node *get_initial_fp(ir_graph *irg)
1452 if (start_fp == NULL) {
1453 ir_node *start = get_irg_start(irg);
1454 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1459 static ir_node *get_initial_mem(ir_graph *irg)
1461 if (start_mem == NULL) {
1462 ir_node *start = get_irg_start(irg);
1463 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1468 static ir_node *get_stack_pointer_for(ir_node *node)
1470 /* get predecessor in stack_order list */
1471 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1474 if (stack_pred == NULL) {
1475 /* first stack user in the current block. We can simply use the
1476 * initial sp_proj for it */
1477 ir_graph *irg = get_irn_irg(node);
1478 return get_initial_sp(irg);
1481 be_transform_node(stack_pred);
1482 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1483 if (stack == NULL) {
1484 return get_stack_pointer_for(stack_pred);
1491 * transform a Return node into epilogue code + return statement
1493 static ir_node *gen_Return(ir_node *node)
1495 ir_node *block = get_nodes_block(node);
1496 ir_graph *irg = get_irn_irg(node);
1497 ir_node *new_block = be_transform_node(block);
1498 dbg_info *dbgi = get_irn_dbg_info(node);
1499 ir_node *mem = get_Return_mem(node);
1500 ir_node *new_mem = be_transform_node(mem);
1501 ir_node *sp = get_stack_pointer_for(node);
1502 size_t n_res = get_Return_n_ress(node);
1503 struct obstack *be_obst = be_get_be_obst(irg);
1506 const arch_register_req_t **reqs;
1511 /* estimate number of return values */
1512 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1513 if (current_cconv->omit_fp)
1514 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1516 in = ALLOCAN(ir_node*, n_ins);
1517 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1521 reqs[p] = arch_no_register_req;
1525 reqs[p] = sp_reg->single_req;
1529 for (i = 0; i < n_res; ++i) {
1530 ir_node *res_value = get_Return_res(node, i);
1531 ir_node *new_res_value = be_transform_node(res_value);
1532 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1533 assert(slot->req1 == NULL);
1534 in[p] = new_res_value;
1535 reqs[p] = slot->req0;
1539 if (current_cconv->omit_fp) {
1540 ir_node *start = get_irg_start(irg);
1541 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1542 for (i = 0; i < n_callee_saves; ++i) {
1543 const arch_register_t *reg = omit_fp_callee_saves[i];
1544 ir_mode *mode = reg->reg_class->mode;
1546 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1548 reqs[p] = reg->single_req;
1554 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1555 arch_set_in_register_reqs(bereturn, reqs);
1560 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1561 ir_node *value0, ir_node *value1)
1563 ir_graph *irg = current_ir_graph;
1564 ir_node *sp = get_irg_frame(irg);
1565 ir_node *nomem = get_irg_no_mem(irg);
1566 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1567 mode_gp, NULL, 0, true);
1571 set_irn_pinned(st, op_pin_state_floats);
1573 if (value1 != NULL) {
1574 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1575 mode_gp, NULL, 4, true);
1576 ir_node *in[2] = { st, st1 };
1577 ir_node *sync = new_r_Sync(block, 2, in);
1578 set_irn_pinned(st1, op_pin_state_floats);
1586 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1587 set_irn_pinned(ldf, op_pin_state_floats);
1589 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1592 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1593 ir_node *node, ir_mode *float_mode,
1596 ir_graph *irg = current_ir_graph;
1597 ir_node *stack = get_irg_frame(irg);
1598 ir_node *nomem = get_irg_no_mem(irg);
1599 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1601 int bits = get_mode_size_bits(float_mode);
1603 set_irn_pinned(stf, op_pin_state_floats);
1605 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1606 set_irn_pinned(ld, op_pin_state_floats);
1607 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1610 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1612 set_irn_pinned(ld, op_pin_state_floats);
1613 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1615 arch_irn_add_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1616 arch_irn_add_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1623 static ir_node *gen_Call(ir_node *node)
1625 ir_graph *irg = get_irn_irg(node);
1626 ir_node *callee = get_Call_ptr(node);
1627 ir_node *block = get_nodes_block(node);
1628 ir_node *new_block = be_transform_node(block);
1629 ir_node *mem = get_Call_mem(node);
1630 ir_node *new_mem = be_transform_node(mem);
1631 dbg_info *dbgi = get_irn_dbg_info(node);
1632 ir_type *type = get_Call_type(node);
1633 size_t n_params = get_Call_n_params(node);
1634 size_t n_ress = get_method_n_ress(type);
1635 /* max inputs: memory, callee, register arguments */
1636 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1637 struct obstack *obst = be_get_be_obst(irg);
1638 calling_convention_t *cconv
1639 = sparc_decide_calling_convention(type, NULL);
1640 size_t n_param_regs = cconv->n_param_regs;
1641 /* param-regs + mem + stackpointer + callee */
1642 unsigned max_inputs = 3 + n_param_regs;
1643 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1644 const arch_register_req_t **in_req
1645 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1649 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1650 ir_entity *entity = NULL;
1651 ir_node *new_frame = get_stack_pointer_for(node);
1652 bool aggregate_return
1653 = type->attr.ma.has_compound_ret_parameter;
1663 assert(n_params == get_method_n_params(type));
1665 /* construct arguments */
1668 in_req[in_arity] = arch_no_register_req;
1672 /* stack pointer input */
1673 /* construct an IncSP -> we have to always be sure that the stack is
1674 * aligned even if we don't push arguments on it */
1675 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1676 cconv->param_stack_size, 1);
1677 in_req[in_arity] = sp_reg->single_req;
1678 in[in_arity] = incsp;
1682 for (p = 0; p < n_params; ++p) {
1683 ir_node *value = get_Call_param(node, p);
1684 ir_node *new_value = be_transform_node(value);
1685 const reg_or_stackslot_t *param = &cconv->parameters[p];
1686 ir_type *param_type = get_method_param_type(type, p);
1687 ir_mode *mode = get_type_mode(param_type);
1688 ir_node *new_values[2];
1692 if (mode_is_float(mode) && param->reg0 != NULL) {
1693 unsigned size_bits = get_mode_size_bits(mode);
1694 assert(size_bits <= 64);
1695 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1697 new_values[0] = new_value;
1698 new_values[1] = NULL;
1701 /* put value into registers */
1702 if (param->reg0 != NULL) {
1703 in[in_arity] = new_values[0];
1704 in_req[in_arity] = param->reg0->single_req;
1706 if (new_values[1] == NULL)
1709 if (param->reg1 != NULL) {
1710 assert(new_values[1] != NULL);
1711 in[in_arity] = new_values[1];
1712 in_req[in_arity] = param->reg1->single_req;
1717 /* we need a store if we're here */
1718 if (new_values[1] != NULL) {
1719 new_value = new_values[1];
1723 /* we need to skip over our save area when constructing the call
1724 * arguments on stack */
1725 offset = param->offset + SPARC_MIN_STACKSIZE;
1727 if (mode_is_float(mode)) {
1728 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1729 mode, NULL, offset, true);
1731 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1732 new_mem, mode, NULL, offset, true);
1734 set_irn_pinned(str, op_pin_state_floats);
1735 sync_ins[sync_arity++] = str;
1738 /* construct memory input */
1739 if (sync_arity == 0) {
1740 in[mem_pos] = new_mem;
1741 } else if (sync_arity == 1) {
1742 in[mem_pos] = sync_ins[0];
1744 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1747 if (is_SymConst(callee)) {
1748 entity = get_SymConst_entity(callee);
1750 in[in_arity] = be_transform_node(callee);
1751 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1754 assert(in_arity <= (int)max_inputs);
1761 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1763 /* create call node */
1764 if (entity != NULL) {
1765 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1766 entity, 0, aggregate_return);
1768 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1771 arch_set_in_register_reqs(res, in_req);
1773 /* create output register reqs */
1775 arch_set_out_register_req(res, o++, arch_no_register_req);
1776 /* add register requirements for the result regs */
1777 for (r = 0; r < n_ress; ++r) {
1778 const reg_or_stackslot_t *result_info = &cconv->results[r];
1779 const arch_register_req_t *req = result_info->req0;
1781 arch_set_out_register_req(res, o++, req);
1783 assert(result_info->req1 == NULL);
1785 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1786 const arch_register_t *reg;
1787 if (!rbitset_is_set(cconv->caller_saves, i))
1789 reg = &sparc_registers[i];
1790 arch_set_out_register_req(res, o++, reg->single_req);
1792 assert(o == out_arity);
1794 /* copy pinned attribute */
1795 set_irn_pinned(res, get_irn_pinned(node));
1797 /* IncSP to destroy the call stackframe */
1798 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1799 /* if we are the last IncSP producer in a block then we have to keep
1801 * Note: This here keeps all producers which is more than necessary */
1802 add_irn_dep(incsp, res);
1805 pmap_insert(node_to_stack, node, incsp);
1807 sparc_free_calling_convention(cconv);
1811 static ir_node *gen_Sel(ir_node *node)
1813 dbg_info *dbgi = get_irn_dbg_info(node);
1814 ir_node *block = get_nodes_block(node);
1815 ir_node *new_block = be_transform_node(block);
1816 ir_node *ptr = get_Sel_ptr(node);
1817 ir_node *new_ptr = be_transform_node(ptr);
1818 ir_entity *entity = get_Sel_entity(node);
1820 /* must be the frame pointer all other sels must have been lowered
1822 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1824 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1827 static const arch_register_req_t float1_req = {
1828 arch_register_req_type_normal,
1829 &sparc_reg_classes[CLASS_sparc_fp],
1835 static const arch_register_req_t float2_req = {
1836 arch_register_req_type_normal | arch_register_req_type_aligned,
1837 &sparc_reg_classes[CLASS_sparc_fp],
1843 static const arch_register_req_t float4_req = {
1844 arch_register_req_type_normal | arch_register_req_type_aligned,
1845 &sparc_reg_classes[CLASS_sparc_fp],
1853 static const arch_register_req_t *get_float_req(ir_mode *mode)
1855 unsigned bits = get_mode_size_bits(mode);
1857 assert(mode_is_float(mode));
1860 } else if (bits == 64) {
1863 assert(bits == 128);
1869 * Transform some Phi nodes
1871 static ir_node *gen_Phi(ir_node *node)
1873 const arch_register_req_t *req;
1874 ir_node *block = be_transform_node(get_nodes_block(node));
1875 ir_graph *irg = current_ir_graph;
1876 dbg_info *dbgi = get_irn_dbg_info(node);
1877 ir_mode *mode = get_irn_mode(node);
1880 if (mode_needs_gp_reg(mode)) {
1881 /* we shouldn't have any 64bit stuff around anymore */
1882 assert(get_mode_size_bits(mode) <= 32);
1883 /* all integer operations are on 32bit registers now */
1885 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
1886 } else if (mode_is_float(mode)) {
1888 req = get_float_req(mode);
1890 req = arch_no_register_req;
1893 /* phi nodes allow loops, so we use the old arguments for now
1894 * and fix this later */
1895 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
1896 copy_node_attr(irg, node, phi);
1897 be_duplicate_deps(node, phi);
1898 arch_set_out_register_req(phi, 0, req);
1899 be_enqueue_preds(node);
1904 * Transform a Proj from a Load.
1906 static ir_node *gen_Proj_Load(ir_node *node)
1908 ir_node *load = get_Proj_pred(node);
1909 ir_node *new_load = be_transform_node(load);
1910 dbg_info *dbgi = get_irn_dbg_info(node);
1911 long pn = get_Proj_proj(node);
1913 /* renumber the proj */
1914 switch (get_sparc_irn_opcode(new_load)) {
1916 /* handle all gp loads equal: they have the same proj numbers. */
1917 if (pn == pn_Load_res) {
1918 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
1919 } else if (pn == pn_Load_M) {
1920 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1924 if (pn == pn_Load_res) {
1925 return new_rd_Proj(dbgi, new_load, mode_fp, pn_sparc_Ldf_res);
1926 } else if (pn == pn_Load_M) {
1927 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
1933 panic("Unsupported Proj from Load");
1936 static ir_node *gen_Proj_Store(ir_node *node)
1938 ir_node *store = get_Proj_pred(node);
1939 ir_node *new_store = be_transform_node(store);
1940 long pn = get_Proj_proj(node);
1942 /* renumber the proj */
1943 switch (get_sparc_irn_opcode(new_store)) {
1945 if (pn == pn_Store_M) {
1950 if (pn == pn_Store_M) {
1957 panic("Unsupported Proj from Store");
1961 * Transform the Projs from a Cmp.
1963 static ir_node *gen_Proj_Cmp(ir_node *node)
1966 panic("not implemented");
1970 * transform Projs from a Div
1972 static ir_node *gen_Proj_Div(ir_node *node)
1974 ir_node *pred = get_Proj_pred(node);
1975 ir_node *new_pred = be_transform_node(pred);
1976 long pn = get_Proj_proj(node);
1979 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
1981 } else if (is_sparc_fdiv(new_pred)) {
1982 res_mode = get_Div_resmode(pred);
1984 panic("sparc backend: Div transformed to something unexpected: %+F",
1987 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
1988 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
1989 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
1990 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
1993 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
1995 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
1999 panic("Unsupported Proj from Div");
2002 static ir_node *get_frame_base(ir_graph *irg)
2004 if (frame_base == NULL) {
2005 if (current_cconv->omit_fp) {
2006 frame_base = get_initial_sp(irg);
2008 frame_base = get_initial_fp(irg);
2014 static ir_node *gen_Proj_Start(ir_node *node)
2016 ir_node *block = get_nodes_block(node);
2017 ir_node *new_block = be_transform_node(block);
2018 long pn = get_Proj_proj(node);
2019 /* make sure prolog is constructed */
2020 be_transform_node(get_Proj_pred(node));
2022 switch ((pn_Start) pn) {
2023 case pn_Start_X_initial_exec:
2024 /* exchange ProjX with a jump */
2025 return new_bd_sparc_Ba(NULL, new_block);
2027 ir_graph *irg = get_irn_irg(node);
2028 return get_initial_mem(irg);
2030 case pn_Start_T_args:
2031 return new_r_Bad(get_irn_irg(block), mode_T);
2032 case pn_Start_P_frame_base:
2033 return get_frame_base(get_irn_irg(block));
2035 panic("Unexpected start proj: %ld\n", pn);
2038 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2040 long pn = get_Proj_proj(node);
2041 ir_node *block = get_nodes_block(node);
2042 ir_graph *irg = get_irn_irg(node);
2043 ir_node *new_block = be_transform_node(block);
2044 ir_entity *entity = get_irg_entity(irg);
2045 ir_type *method_type = get_entity_type(entity);
2046 ir_type *param_type = get_method_param_type(method_type, pn);
2047 ir_node *args = get_Proj_pred(node);
2048 ir_node *start = get_Proj_pred(args);
2049 ir_node *new_start = be_transform_node(start);
2050 const reg_or_stackslot_t *param;
2052 /* Proj->Proj->Start must be a method argument */
2053 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2055 param = ¤t_cconv->parameters[pn];
2057 if (param->reg0 != NULL) {
2058 /* argument transmitted in register */
2059 ir_mode *mode = get_type_mode(param_type);
2060 const arch_register_t *reg = param->reg0;
2061 ir_mode *reg_mode = reg->reg_class->mode;
2062 long pn = param->reg_offset + start_params_offset;
2063 ir_node *value = new_r_Proj(new_start, reg_mode, pn);
2065 if (mode_is_float(mode)) {
2066 const arch_register_t *reg1 = param->reg1;
2067 ir_node *value1 = NULL;
2070 ir_mode *reg1_mode = reg1->reg_class->mode;
2071 value1 = new_r_Proj(new_start, reg1_mode, pn+1);
2072 } else if (param->entity != NULL) {
2073 ir_node *fp = get_initial_fp(irg);
2074 ir_node *mem = get_initial_mem(irg);
2075 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2076 mode_gp, param->entity,
2078 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2081 /* convert integer value to float */
2082 value = bitcast_int_to_float(NULL, new_block, value, value1);
2086 /* argument transmitted on stack */
2087 ir_node *mem = get_initial_mem(irg);
2088 ir_mode *mode = get_type_mode(param->type);
2089 ir_node *base = get_frame_base(irg);
2093 if (mode_is_float(mode)) {
2094 load = create_ldf(NULL, new_block, base, mem, mode,
2095 param->entity, 0, true);
2096 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2098 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2099 param->entity, 0, true);
2100 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2102 set_irn_pinned(load, op_pin_state_floats);
2108 static ir_node *gen_Proj_Call(ir_node *node)
2110 long pn = get_Proj_proj(node);
2111 ir_node *call = get_Proj_pred(node);
2112 ir_node *new_call = be_transform_node(call);
2114 switch ((pn_Call) pn) {
2116 return new_r_Proj(new_call, mode_M, 0);
2117 case pn_Call_X_regular:
2118 case pn_Call_X_except:
2119 case pn_Call_T_result:
2122 panic("Unexpected Call proj %ld\n", pn);
2125 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2127 long pn = get_Proj_proj(node);
2128 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2129 ir_node *new_call = be_transform_node(call);
2130 ir_type *function_type = get_Call_type(call);
2131 calling_convention_t *cconv
2132 = sparc_decide_calling_convention(function_type, NULL);
2133 const reg_or_stackslot_t *res = &cconv->results[pn];
2135 long new_pn = 1 + res->reg_offset;
2137 assert(res->req0 != NULL && res->req1 == NULL);
2138 mode = res->req0->cls->mode;
2139 sparc_free_calling_convention(cconv);
2141 return new_r_Proj(new_call, mode, new_pn);
2145 * Transform a Proj node.
2147 static ir_node *gen_Proj(ir_node *node)
2149 ir_node *pred = get_Proj_pred(node);
2151 switch (get_irn_opcode(pred)) {
2153 return gen_Proj_Store(node);
2155 return gen_Proj_Load(node);
2157 return gen_Proj_Call(node);
2159 return gen_Proj_Cmp(node);
2161 return be_duplicate_node(node);
2163 return gen_Proj_Div(node);
2165 return gen_Proj_Start(node);
2167 ir_node *pred_pred = get_Proj_pred(pred);
2168 if (is_Call(pred_pred)) {
2169 return gen_Proj_Proj_Call(node);
2170 } else if (is_Start(pred_pred)) {
2171 return gen_Proj_Proj_Start(node);
2176 if (is_sparc_AddCC_t(pred)) {
2177 return gen_Proj_AddCC_t(node);
2178 } else if (is_sparc_SubCC_t(pred)) {
2179 return gen_Proj_SubCC_t(node);
2181 panic("code selection didn't expect Proj after %+F\n", pred);
2188 static ir_node *gen_Jmp(ir_node *node)
2190 ir_node *block = get_nodes_block(node);
2191 ir_node *new_block = be_transform_node(block);
2192 dbg_info *dbgi = get_irn_dbg_info(node);
2194 return new_bd_sparc_Ba(dbgi, new_block);
2198 * configure transformation callbacks
2200 static void sparc_register_transformers(void)
2202 be_start_transform_setup();
2204 be_set_transform_function(op_Add, gen_Add);
2205 be_set_transform_function(op_And, gen_And);
2206 be_set_transform_function(op_Call, gen_Call);
2207 be_set_transform_function(op_Cmp, gen_Cmp);
2208 be_set_transform_function(op_Cond, gen_Cond);
2209 be_set_transform_function(op_Const, gen_Const);
2210 be_set_transform_function(op_Conv, gen_Conv);
2211 be_set_transform_function(op_Div, gen_Div);
2212 be_set_transform_function(op_Eor, gen_Eor);
2213 be_set_transform_function(op_Jmp, gen_Jmp);
2214 be_set_transform_function(op_Load, gen_Load);
2215 be_set_transform_function(op_Minus, gen_Minus);
2216 be_set_transform_function(op_Mul, gen_Mul);
2217 be_set_transform_function(op_Mulh, gen_Mulh);
2218 be_set_transform_function(op_Not, gen_Not);
2219 be_set_transform_function(op_Or, gen_Or);
2220 be_set_transform_function(op_Phi, gen_Phi);
2221 be_set_transform_function(op_Proj, gen_Proj);
2222 be_set_transform_function(op_Return, gen_Return);
2223 be_set_transform_function(op_Sel, gen_Sel);
2224 be_set_transform_function(op_Shl, gen_Shl);
2225 be_set_transform_function(op_Shr, gen_Shr);
2226 be_set_transform_function(op_Shrs, gen_Shrs);
2227 be_set_transform_function(op_Start, gen_Start);
2228 be_set_transform_function(op_Store, gen_Store);
2229 be_set_transform_function(op_Sub, gen_Sub);
2230 be_set_transform_function(op_SymConst, gen_SymConst);
2231 be_set_transform_function(op_Unknown, gen_Unknown);
2233 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2234 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2235 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2236 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2237 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2241 * Transform a Firm graph into a SPARC graph.
2243 void sparc_transform_graph(ir_graph *irg)
2245 ir_entity *entity = get_irg_entity(irg);
2246 ir_type *frame_type;
2248 sparc_register_transformers();
2250 node_to_stack = pmap_create();
2255 mode_flags = mode_Bu;
2264 stackorder = be_collect_stacknodes(irg);
2266 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2267 sparc_create_stacklayout(irg, current_cconv);
2268 be_add_parameter_entity_stores(irg);
2270 be_transform_graph(irg, NULL);
2272 be_free_stackorder(stackorder);
2273 sparc_free_calling_convention(current_cconv);
2275 frame_type = get_irg_frame_type(irg);
2276 if (get_type_state(frame_type) == layout_undefined)
2277 default_layout_compound_type(frame_type);
2279 pmap_destroy(node_to_stack);
2280 node_to_stack = NULL;
2282 be_add_missing_keeps(irg);
2284 /* do code placement, to optimize the position of constants */
2288 void sparc_init_transform(void)
2290 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");