2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into SPARC FIRM)
23 * @author Hannes Rapp, Matthias Braun
32 #include "irgraph_t.h"
38 #include "iroptimize.h"
45 #include "../benode.h"
47 #include "../beutil.h"
48 #include "../betranshlp.h"
49 #include "../beabihelper.h"
50 #include "bearch_sparc_t.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_transform.h"
54 #include "sparc_new_nodes.h"
55 #include "gen_sparc_new_nodes.h"
57 #include "gen_sparc_regalloc_if.h"
58 #include "sparc_cconv.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 static const arch_register_t *sp_reg = &sparc_registers[REG_SP];
65 static const arch_register_t *fp_reg = &sparc_registers[REG_FRAME_POINTER];
66 static calling_convention_t *current_cconv = NULL;
67 static be_stackorder_t *stackorder;
68 static ir_mode *mode_gp;
69 static ir_mode *mode_flags;
70 static ir_mode *mode_fp;
71 static ir_mode *mode_fp2;
72 //static ir_mode *mode_fp4;
73 static pmap *node_to_stack;
74 static size_t start_mem_offset;
75 static ir_node *start_mem;
76 static size_t start_g0_offset;
77 static ir_node *start_g0;
78 static size_t start_sp_offset;
79 static ir_node *start_sp;
80 static size_t start_fp_offset;
81 static ir_node *start_fp;
82 static ir_node *frame_base;
83 static size_t start_params_offset;
84 static size_t start_callee_saves_offset;
86 static const arch_register_t *const omit_fp_callee_saves[] = {
87 &sparc_registers[REG_L0],
88 &sparc_registers[REG_L1],
89 &sparc_registers[REG_L2],
90 &sparc_registers[REG_L3],
91 &sparc_registers[REG_L4],
92 &sparc_registers[REG_L5],
93 &sparc_registers[REG_L6],
94 &sparc_registers[REG_L7],
95 &sparc_registers[REG_I0],
96 &sparc_registers[REG_I1],
97 &sparc_registers[REG_I2],
98 &sparc_registers[REG_I3],
99 &sparc_registers[REG_I4],
100 &sparc_registers[REG_I5],
103 static inline bool mode_needs_gp_reg(ir_mode *mode)
105 if (mode_is_int(mode) || mode_is_reference(mode)) {
106 /* we should only see 32bit code */
107 assert(get_mode_size_bits(mode) <= 32);
114 * Create an And that will zero out upper bits.
116 * @param dbgi debug info
117 * @param block the basic block
118 * @param op the original node
119 * @param src_bits number of lower bits that will remain
121 static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
125 return new_bd_sparc_And_imm(dbgi, block, op, NULL, 0xFF);
126 } else if (src_bits == 16) {
127 ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, 16);
128 ir_node *rshift = new_bd_sparc_Srl_imm(dbgi, block, lshift, NULL, 16);
131 panic("zero extension only supported for 8 and 16 bits");
136 * Generate code for a sign extension.
138 * @param dbgi debug info
139 * @param block the basic block
140 * @param op the original node
141 * @param src_bits number of lower bits that will remain
143 static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
146 int shift_width = 32 - src_bits;
147 ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, NULL, shift_width);
148 ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, NULL, shift_width);
153 * returns true if it is assured, that the upper bits of a node are "clean"
154 * which means for a 16 or 8 bit value, that the upper bits in the register
155 * are 0 for unsigned and a copy of the last significant bit for signed
158 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
160 (void) transformed_node;
167 * Extend a value to 32 bit signed/unsigned depending on its mode.
169 * @param dbgi debug info
170 * @param block the basic block
171 * @param op the original node
172 * @param orig_mode the original mode of op
174 static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
177 int bits = get_mode_size_bits(orig_mode);
181 if (mode_is_signed(orig_mode)) {
182 return gen_sign_extension(dbgi, block, op, bits);
184 return gen_zero_extension(dbgi, block, op, bits);
190 MATCH_COMMUTATIVE = 1U << 0, /**< commutative operation. */
191 MATCH_MODE_NEUTRAL = 1U << 1, /**< the higher bits of the inputs don't
192 influence the significant lower bit at
193 all (for cases where mode < 32bit) */
195 ENUM_BITSET(match_flags_t)
197 typedef ir_node* (*new_binop_reg_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2);
198 typedef ir_node* (*new_binop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_node *op2, ir_mode *mode);
199 typedef ir_node* (*new_binop_imm_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_entity *entity, int32_t immediate);
200 typedef ir_node* (*new_unop_fp_func) (dbg_info *dbgi, ir_node *block, ir_node *op1, ir_mode *mode);
203 * checks if a node's value can be encoded as a immediate
205 static bool is_imm_encodeable(const ir_node *node)
211 value = get_tarval_long(get_Const_tarval(node));
212 return sparc_is_value_imm_encodeable(value);
215 static bool needs_extension(ir_mode *mode)
217 return get_mode_size_bits(mode) < get_mode_size_bits(mode_gp);
221 * Check, if a given node is a Down-Conv, ie. a integer Conv
222 * from a mode with a mode with more bits to a mode with lesser bits.
223 * Moreover, we return only true if the node has not more than 1 user.
225 * @param node the node
226 * @return non-zero if node is a Down-Conv
228 static bool is_downconv(const ir_node *node)
236 src_mode = get_irn_mode(get_Conv_op(node));
237 dest_mode = get_irn_mode(node);
239 mode_needs_gp_reg(src_mode) &&
240 mode_needs_gp_reg(dest_mode) &&
241 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
244 static ir_node *sparc_skip_downconv(ir_node *node)
246 while (is_downconv(node)) {
247 node = get_Conv_op(node);
253 * helper function for binop operations
255 * @param new_reg register generation function ptr
256 * @param new_imm immediate generation function ptr
258 static ir_node *gen_helper_binop_args(ir_node *node,
259 ir_node *op1, ir_node *op2,
261 new_binop_reg_func new_reg,
262 new_binop_imm_func new_imm)
264 dbg_info *dbgi = get_irn_dbg_info(node);
265 ir_node *block = be_transform_node(get_nodes_block(node));
271 if (flags & MATCH_MODE_NEUTRAL) {
272 op1 = sparc_skip_downconv(op1);
273 op2 = sparc_skip_downconv(op2);
275 mode1 = get_irn_mode(op1);
276 mode2 = get_irn_mode(op2);
277 /* we shouldn't see 64bit code */
278 assert(get_mode_size_bits(mode1) <= 32);
279 assert(get_mode_size_bits(mode2) <= 32);
281 if (is_imm_encodeable(op2)) {
282 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
283 new_op1 = be_transform_node(op1);
284 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
285 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
287 return new_imm(dbgi, block, new_op1, NULL, immediate);
289 new_op2 = be_transform_node(op2);
290 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode2)) {
291 new_op2 = gen_extension(dbgi, block, new_op2, mode2);
294 if ((flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
295 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
296 return new_imm(dbgi, block, new_op2, NULL, immediate);
299 new_op1 = be_transform_node(op1);
300 if (! (flags & MATCH_MODE_NEUTRAL) && needs_extension(mode1)) {
301 new_op1 = gen_extension(dbgi, block, new_op1, mode1);
303 return new_reg(dbgi, block, new_op1, new_op2);
306 static ir_node *gen_helper_binop(ir_node *node, match_flags_t flags,
307 new_binop_reg_func new_reg,
308 new_binop_imm_func new_imm)
310 ir_node *op1 = get_binop_left(node);
311 ir_node *op2 = get_binop_right(node);
312 return gen_helper_binop_args(node, op1, op2, flags, new_reg, new_imm);
316 * helper function for FP binop operations
318 static ir_node *gen_helper_binfpop(ir_node *node, ir_mode *mode,
319 new_binop_fp_func new_func_single,
320 new_binop_fp_func new_func_double,
321 new_binop_fp_func new_func_quad)
323 ir_node *block = be_transform_node(get_nodes_block(node));
324 ir_node *op1 = get_binop_left(node);
325 ir_node *new_op1 = be_transform_node(op1);
326 ir_node *op2 = get_binop_right(node);
327 ir_node *new_op2 = be_transform_node(op2);
328 dbg_info *dbgi = get_irn_dbg_info(node);
329 unsigned bits = get_mode_size_bits(mode);
333 return new_func_single(dbgi, block, new_op1, new_op2, mode);
335 return new_func_double(dbgi, block, new_op1, new_op2, mode);
337 return new_func_quad(dbgi, block, new_op1, new_op2, mode);
341 panic("unsupported mode %+F for float op", mode);
344 static ir_node *gen_helper_unfpop(ir_node *node, ir_mode *mode,
345 new_unop_fp_func new_func_single,
346 new_unop_fp_func new_func_double,
347 new_unop_fp_func new_func_quad)
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 ir_node *op = get_unop_op(node);
351 ir_node *new_op = be_transform_node(op);
352 dbg_info *dbgi = get_irn_dbg_info(node);
353 unsigned bits = get_mode_size_bits(mode);
357 return new_func_single(dbgi, block, new_op, mode);
359 return new_func_double(dbgi, block, new_op, mode);
361 return new_func_quad(dbgi, block, new_op, mode);
365 panic("unsupported mode %+F for float op", mode);
368 typedef ir_node* (*new_binopx_imm_func)(dbg_info *dbgi, ir_node *block,
369 ir_node *op1, ir_node *flags,
370 ir_entity *imm_entity, int32_t imm);
372 typedef ir_node* (*new_binopx_reg_func)(dbg_info *dbgi, ir_node *block,
373 ir_node *op1, ir_node *op2,
376 static ir_node *gen_helper_binopx(ir_node *node, match_flags_t match_flags,
377 new_binopx_reg_func new_binopx_reg,
378 new_binopx_imm_func new_binopx_imm)
380 dbg_info *dbgi = get_irn_dbg_info(node);
381 ir_node *block = be_transform_node(get_nodes_block(node));
382 ir_node *op1 = get_irn_n(node, 0);
383 ir_node *op2 = get_irn_n(node, 1);
384 ir_node *flags = get_irn_n(node, 2);
385 ir_node *new_flags = be_transform_node(flags);
389 /* only support for mode-neutral implemented so far */
390 assert(match_flags & MATCH_MODE_NEUTRAL);
392 if (is_imm_encodeable(op2)) {
393 int32_t immediate = get_tarval_long(get_Const_tarval(op2));
394 new_op1 = be_transform_node(op1);
395 return new_binopx_imm(dbgi, block, new_op1, new_flags, NULL, immediate);
397 new_op2 = be_transform_node(op2);
398 if ((match_flags & MATCH_COMMUTATIVE) && is_imm_encodeable(op1)) {
399 int32_t immediate = get_tarval_long(get_Const_tarval(op1));
400 return new_binopx_imm(dbgi, block, new_op2, new_flags, NULL, immediate);
402 new_op1 = be_transform_node(op1);
403 return new_binopx_reg(dbgi, block, new_op1, new_op2, new_flags);
407 static ir_node *get_g0(ir_graph *irg)
409 if (start_g0 == NULL) {
410 /* this is already the transformed start node */
411 ir_node *start = get_irg_start(irg);
412 assert(is_sparc_Start(start));
413 start_g0 = new_r_Proj(start, mode_gp, start_g0_offset);
418 typedef struct address_t {
426 * Match a load/store address
428 static void match_address(ir_node *ptr, address_t *address, bool use_ptr2)
431 ir_node *ptr2 = NULL;
433 ir_entity *entity = NULL;
436 ir_node *add_right = get_Add_right(base);
437 if (is_Const(add_right)) {
438 base = get_Add_left(base);
439 offset += get_tarval_long(get_Const_tarval(add_right));
442 /* Note that we don't match sub(x, Const) or chains of adds/subs
443 * because this should all be normalized by now */
445 /* we only use the symconst if we're the only user otherwise we probably
446 * won't save anything but produce multiple sethi+or combinations with
447 * just different offsets */
448 if (is_SymConst(base) && get_irn_n_edges(base) == 1) {
449 dbg_info *dbgi = get_irn_dbg_info(ptr);
450 ir_node *block = get_nodes_block(ptr);
451 ir_node *new_block = be_transform_node(block);
452 entity = get_SymConst_entity(base);
453 base = new_bd_sparc_SetHi(dbgi, new_block, entity, offset);
454 } else if (use_ptr2 && is_Add(base) && entity == NULL && offset == 0) {
455 ptr2 = be_transform_node(get_Add_right(base));
456 base = be_transform_node(get_Add_left(base));
458 if (sparc_is_value_imm_encodeable(offset)) {
459 base = be_transform_node(base);
461 base = be_transform_node(ptr);
467 address->ptr2 = ptr2;
468 address->entity = entity;
469 address->offset = offset;
473 * Creates an sparc Add.
475 * @param node FIRM node
476 * @return the created sparc Add node
478 static ir_node *gen_Add(ir_node *node)
480 ir_mode *mode = get_irn_mode(node);
483 if (mode_is_float(mode)) {
484 return gen_helper_binfpop(node, mode, new_bd_sparc_fadd_s,
485 new_bd_sparc_fadd_d, new_bd_sparc_fadd_q);
488 /* special case: + 0x1000 can be represented as - 0x1000 */
489 right = get_Add_right(node);
490 if (is_Const(right)) {
491 ir_node *left = get_Add_left(node);
494 /* is this simple address arithmetic? then we can let the linker do
495 * the calculation. */
496 if (is_SymConst(left) && get_irn_n_edges(left) == 1) {
497 dbg_info *dbgi = get_irn_dbg_info(node);
498 ir_node *block = be_transform_node(get_nodes_block(node));
501 /* the value of use_ptr2 shouldn't matter here */
502 match_address(node, &address, false);
503 assert(is_sparc_SetHi(address.ptr));
504 return new_bd_sparc_Or_imm(dbgi, block, address.ptr,
505 address.entity, address.offset);
508 tv = get_Const_tarval(right);
509 val = get_tarval_long(tv);
511 dbg_info *dbgi = get_irn_dbg_info(node);
512 ir_node *block = be_transform_node(get_nodes_block(node));
513 ir_node *op = get_Add_left(node);
514 ir_node *new_op = be_transform_node(op);
515 return new_bd_sparc_Sub_imm(dbgi, block, new_op, NULL, -0x1000);
519 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
520 new_bd_sparc_Add_reg, new_bd_sparc_Add_imm);
523 static ir_node *gen_AddCC_t(ir_node *node)
525 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
526 new_bd_sparc_AddCC_reg, new_bd_sparc_AddCC_imm);
529 static ir_node *gen_Proj_AddCC_t(ir_node *node)
531 long pn = get_Proj_proj(node);
532 ir_node *pred = get_Proj_pred(node);
533 ir_node *new_pred = be_transform_node(pred);
536 case pn_sparc_AddCC_t_res:
537 return new_r_Proj(new_pred, mode_gp, pn_sparc_AddCC_res);
538 case pn_sparc_AddCC_t_flags:
539 return new_r_Proj(new_pred, mode_flags, pn_sparc_AddCC_flags);
541 panic("Invalid AddCC_t proj found");
545 static ir_node *gen_AddX_t(ir_node *node)
547 return gen_helper_binopx(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
548 new_bd_sparc_AddX_reg, new_bd_sparc_AddX_imm);
552 * Creates an sparc Sub.
554 * @param node FIRM node
555 * @return the created sparc Sub node
557 static ir_node *gen_Sub(ir_node *node)
559 ir_mode *mode = get_irn_mode(node);
561 if (mode_is_float(mode)) {
562 return gen_helper_binfpop(node, mode, new_bd_sparc_fsub_s,
563 new_bd_sparc_fsub_d, new_bd_sparc_fsub_q);
566 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
567 new_bd_sparc_Sub_reg, new_bd_sparc_Sub_imm);
570 static ir_node *gen_SubCC_t(ir_node *node)
572 return gen_helper_binop(node, MATCH_MODE_NEUTRAL,
573 new_bd_sparc_SubCC_reg, new_bd_sparc_SubCC_imm);
576 static ir_node *gen_Proj_SubCC_t(ir_node *node)
578 long pn = get_Proj_proj(node);
579 ir_node *pred = get_Proj_pred(node);
580 ir_node *new_pred = be_transform_node(pred);
583 case pn_sparc_SubCC_t_res:
584 return new_r_Proj(new_pred, mode_gp, pn_sparc_SubCC_res);
585 case pn_sparc_SubCC_t_flags:
586 return new_r_Proj(new_pred, mode_flags, pn_sparc_SubCC_flags);
588 panic("Invalid SubCC_t proj found");
592 static ir_node *gen_SubX_t(ir_node *node)
594 return gen_helper_binopx(node, MATCH_MODE_NEUTRAL,
595 new_bd_sparc_SubX_reg, new_bd_sparc_SubX_imm);
598 ir_node *create_ldf(dbg_info *dbgi, ir_node *block, ir_node *ptr,
599 ir_node *mem, ir_mode *mode, ir_entity *entity,
600 long offset, bool is_frame_entity)
602 unsigned bits = get_mode_size_bits(mode);
603 assert(mode_is_float(mode));
605 return new_bd_sparc_Ldf_s(dbgi, block, ptr, mem, mode, entity,
606 offset, is_frame_entity);
607 } else if (bits == 64) {
608 return new_bd_sparc_Ldf_d(dbgi, block, ptr, mem, mode, entity,
609 offset, is_frame_entity);
612 return new_bd_sparc_Ldf_q(dbgi, block, ptr, mem, mode, entity,
613 offset, is_frame_entity);
617 ir_node *create_stf(dbg_info *dbgi, ir_node *block, ir_node *value,
618 ir_node *ptr, ir_node *mem, ir_mode *mode,
619 ir_entity *entity, long offset,
620 bool is_frame_entity)
622 unsigned bits = get_mode_size_bits(mode);
623 assert(mode_is_float(mode));
625 return new_bd_sparc_Stf_s(dbgi, block, value, ptr, mem, mode, entity,
626 offset, is_frame_entity);
627 } else if (bits == 64) {
628 return new_bd_sparc_Stf_d(dbgi, block, value, ptr, mem, mode, entity,
629 offset, is_frame_entity);
632 return new_bd_sparc_Stf_q(dbgi, block, value, ptr, mem, mode, entity,
633 offset, is_frame_entity);
640 * @param node the ir Load node
641 * @return the created sparc Load node
643 static ir_node *gen_Load(ir_node *node)
645 dbg_info *dbgi = get_irn_dbg_info(node);
646 ir_mode *mode = get_Load_mode(node);
647 ir_node *block = be_transform_node(get_nodes_block(node));
648 ir_node *ptr = get_Load_ptr(node);
649 ir_node *mem = get_Load_mem(node);
650 ir_node *new_mem = be_transform_node(mem);
651 ir_node *new_load = NULL;
654 if (get_Load_unaligned(node) == align_non_aligned) {
655 panic("sparc: transformation of unaligned Loads not implemented yet");
658 if (mode_is_float(mode)) {
659 match_address(ptr, &address, false);
660 new_load = create_ldf(dbgi, block, address.ptr, new_mem, mode,
661 address.entity, address.offset, false);
663 match_address(ptr, &address, true);
664 if (address.ptr2 != NULL) {
665 assert(address.entity == NULL && address.offset == 0);
666 new_load = new_bd_sparc_Ld_reg(dbgi, block, address.ptr,
667 address.ptr2, new_mem, mode);
669 new_load = new_bd_sparc_Ld_imm(dbgi, block, address.ptr, new_mem,
670 mode, address.entity, address.offset,
674 set_irn_pinned(new_load, get_irn_pinned(node));
680 * Transforms a Store.
682 * @param node the ir Store node
683 * @return the created sparc Store node
685 static ir_node *gen_Store(ir_node *node)
687 ir_node *block = be_transform_node(get_nodes_block(node));
688 ir_node *ptr = get_Store_ptr(node);
689 ir_node *mem = get_Store_mem(node);
690 ir_node *new_mem = be_transform_node(mem);
691 ir_node *val = get_Store_value(node);
692 ir_node *new_val = be_transform_node(val);
693 ir_mode *mode = get_irn_mode(val);
694 dbg_info *dbgi = get_irn_dbg_info(node);
695 ir_node *new_store = NULL;
698 if (get_Store_unaligned(node) == align_non_aligned) {
699 panic("sparc: transformation of unaligned Stores not implemented yet");
702 if (mode_is_float(mode)) {
703 /* TODO: variants with reg+reg address mode */
704 match_address(ptr, &address, false);
705 new_store = create_stf(dbgi, block, new_val, address.ptr, new_mem,
706 mode, address.entity, address.offset, false);
708 assert(get_mode_size_bits(mode) <= 32);
709 match_address(ptr, &address, true);
710 if (address.ptr2 != NULL) {
711 assert(address.entity == NULL && address.offset == 0);
712 new_store = new_bd_sparc_St_reg(dbgi, block, new_val, address.ptr,
713 address.ptr2, new_mem, mode);
715 new_store = new_bd_sparc_St_imm(dbgi, block, new_val, address.ptr,
716 new_mem, mode, address.entity,
717 address.offset, false);
720 set_irn_pinned(new_store, get_irn_pinned(node));
726 * Creates an sparc Mul.
727 * returns the lower 32bits of the 64bit multiply result
729 * @return the created sparc Mul node
731 static ir_node *gen_Mul(ir_node *node)
733 ir_mode *mode = get_irn_mode(node);
734 if (mode_is_float(mode)) {
735 return gen_helper_binfpop(node, mode, new_bd_sparc_fmul_s,
736 new_bd_sparc_fmul_d, new_bd_sparc_fmul_q);
739 return gen_helper_binop(node, MATCH_COMMUTATIVE | MATCH_MODE_NEUTRAL,
740 new_bd_sparc_Mul_reg, new_bd_sparc_Mul_imm);
744 * Creates an sparc Mulh.
745 * Mulh returns the upper 32bits of a mul instruction
747 * @return the created sparc Mulh node
749 static ir_node *gen_Mulh(ir_node *node)
751 ir_mode *mode = get_irn_mode(node);
754 if (mode_is_float(mode))
755 panic("FP not supported yet");
757 if (mode_is_signed(mode)) {
758 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_SMulh_reg, new_bd_sparc_SMulh_imm);
759 return new_r_Proj(mul, mode_gp, pn_sparc_SMulh_low);
761 mul = gen_helper_binop(node, MATCH_COMMUTATIVE, new_bd_sparc_UMulh_reg, new_bd_sparc_UMulh_imm);
762 return new_r_Proj(mul, mode_gp, pn_sparc_UMulh_low);
766 static ir_node *gen_sign_extension_value(ir_node *node)
768 ir_node *block = get_nodes_block(node);
769 ir_node *new_block = be_transform_node(block);
770 ir_node *new_node = be_transform_node(node);
771 /* TODO: we could do some shortcuts for some value types probably.
772 * (For constants or other cases where we know the sign bit in
774 return new_bd_sparc_Sra_imm(NULL, new_block, new_node, NULL, 31);
778 * Creates an sparc Div.
780 * @return the created sparc Div node
782 static ir_node *gen_Div(ir_node *node)
784 dbg_info *dbgi = get_irn_dbg_info(node);
785 ir_node *block = get_nodes_block(node);
786 ir_node *new_block = be_transform_node(block);
787 ir_mode *mode = get_Div_resmode(node);
788 ir_node *left = get_Div_left(node);
789 ir_node *left_low = be_transform_node(left);
790 ir_node *right = get_Div_right(node);
793 if (mode_is_float(mode)) {
794 return gen_helper_binfpop(node, mode, new_bd_sparc_fdiv_s,
795 new_bd_sparc_fdiv_d, new_bd_sparc_fdiv_q);
798 if (mode_is_signed(mode)) {
799 ir_node *left_high = gen_sign_extension_value(left);
801 if (is_imm_encodeable(right)) {
802 int32_t immediate = get_tarval_long(get_Const_tarval(right));
803 res = new_bd_sparc_SDiv_imm(dbgi, new_block, left_high, left_low,
806 ir_node *new_right = be_transform_node(right);
807 res = new_bd_sparc_SDiv_reg(dbgi, new_block, left_high, left_low,
811 ir_graph *irg = get_irn_irg(node);
812 ir_node *left_high = get_g0(irg);
813 if (is_imm_encodeable(right)) {
814 int32_t immediate = get_tarval_long(get_Const_tarval(right));
815 res = new_bd_sparc_UDiv_imm(dbgi, new_block, left_high, left_low,
818 ir_node *new_right = be_transform_node(right);
819 res = new_bd_sparc_UDiv_reg(dbgi, new_block, left_high, left_low,
828 * Transforms a Not node.
830 * @return the created sparc Not node
832 static ir_node *gen_Not(ir_node *node)
834 ir_node *op = get_Not_op(node);
835 ir_graph *irg = get_irn_irg(node);
836 ir_node *zero = get_g0(irg);
837 dbg_info *dbgi = get_irn_dbg_info(node);
838 ir_node *block = be_transform_node(get_nodes_block(node));
839 ir_node *new_op = be_transform_node(op);
841 /* Note: Not(Eor()) is normalize in firm localopts already so
842 * we don't match it for xnor here */
844 /* Not can be represented with xnor 0, n */
845 return new_bd_sparc_XNor_reg(dbgi, block, zero, new_op);
848 static ir_node *gen_helper_bitop(ir_node *node,
849 new_binop_reg_func new_reg,
850 new_binop_imm_func new_imm,
851 new_binop_reg_func new_not_reg,
852 new_binop_imm_func new_not_imm,
855 ir_node *op1 = get_binop_left(node);
856 ir_node *op2 = get_binop_right(node);
858 return gen_helper_binop_args(node, op2, get_Not_op(op1),
860 new_not_reg, new_not_imm);
863 return gen_helper_binop_args(node, op1, get_Not_op(op2),
865 new_not_reg, new_not_imm);
867 return gen_helper_binop_args(node, op1, op2,
868 flags | MATCH_COMMUTATIVE,
872 static ir_node *gen_And(ir_node *node)
874 return gen_helper_bitop(node,
875 new_bd_sparc_And_reg,
876 new_bd_sparc_And_imm,
877 new_bd_sparc_AndN_reg,
878 new_bd_sparc_AndN_imm,
882 static ir_node *gen_Or(ir_node *node)
884 return gen_helper_bitop(node,
887 new_bd_sparc_OrN_reg,
888 new_bd_sparc_OrN_imm,
892 static ir_node *gen_Eor(ir_node *node)
894 return gen_helper_bitop(node,
895 new_bd_sparc_Xor_reg,
896 new_bd_sparc_Xor_imm,
897 new_bd_sparc_XNor_reg,
898 new_bd_sparc_XNor_imm,
902 static ir_node *gen_Shl(ir_node *node)
904 ir_mode *mode = get_irn_mode(node);
905 if (get_mode_modulo_shift(mode) != 32)
906 panic("modulo_shift!=32 not supported by sparc backend");
907 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
910 static ir_node *gen_Shr(ir_node *node)
912 ir_mode *mode = get_irn_mode(node);
913 if (get_mode_modulo_shift(mode) != 32)
914 panic("modulo_shift!=32 not supported by sparc backend");
915 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Srl_reg, new_bd_sparc_Srl_imm);
918 static ir_node *gen_Shrs(ir_node *node)
920 ir_mode *mode = get_irn_mode(node);
921 if (get_mode_modulo_shift(mode) != 32)
922 panic("modulo_shift!=32 not supported by sparc backend");
923 return gen_helper_binop(node, MATCH_NONE, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
927 * Transforms a Minus node.
929 static ir_node *gen_Minus(ir_node *node)
931 ir_mode *mode = get_irn_mode(node);
938 if (mode_is_float(mode)) {
939 return gen_helper_unfpop(node, mode, new_bd_sparc_fneg_s,
940 new_bd_sparc_fneg_d, new_bd_sparc_fneg_q);
942 block = be_transform_node(get_nodes_block(node));
943 dbgi = get_irn_dbg_info(node);
944 op = get_Minus_op(node);
945 new_op = be_transform_node(op);
946 zero = get_g0(get_irn_irg(node));
947 return new_bd_sparc_Sub_reg(dbgi, block, zero, new_op);
951 * Create an entity for a given (floating point) tarval
953 static ir_entity *create_float_const_entity(ir_tarval *tv)
955 const arch_env_t *arch_env = be_get_irg_arch_env(current_ir_graph);
956 sparc_isa_t *isa = (sparc_isa_t*) arch_env;
957 ir_entity *entity = (ir_entity*) pmap_get(isa->constants, tv);
958 ir_initializer_t *initializer;
966 mode = get_tarval_mode(tv);
967 type = get_type_for_mode(mode);
968 glob = get_glob_type();
969 entity = new_entity(glob, id_unique("C%u"), type);
970 set_entity_visibility(entity, ir_visibility_private);
971 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
973 initializer = create_initializer_tarval(tv);
974 set_entity_initializer(entity, initializer);
976 pmap_insert(isa->constants, tv, entity);
980 static ir_node *gen_float_const(dbg_info *dbgi, ir_node *block, ir_tarval *tv)
982 ir_entity *entity = create_float_const_entity(tv);
983 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, 0);
984 ir_node *mem = get_irg_no_mem(current_ir_graph);
985 ir_mode *mode = get_tarval_mode(tv);
987 = create_ldf(dbgi, block, hi, mem, mode, entity, 0, false);
988 ir_node *proj = new_r_Proj(new_op, mode, pn_sparc_Ldf_res);
990 set_irn_pinned(new_op, op_pin_state_floats);
994 static ir_node *gen_Const(ir_node *node)
996 ir_node *block = be_transform_node(get_nodes_block(node));
997 ir_mode *mode = get_irn_mode(node);
998 dbg_info *dbgi = get_irn_dbg_info(node);
999 ir_tarval *tv = get_Const_tarval(node);
1002 if (mode_is_float(mode)) {
1003 return gen_float_const(dbgi, block, tv);
1006 value = get_tarval_long(tv);
1008 return get_g0(get_irn_irg(node));
1009 } else if (sparc_is_value_imm_encodeable(value)) {
1010 ir_graph *irg = get_irn_irg(node);
1011 return new_bd_sparc_Or_imm(dbgi, block, get_g0(irg), NULL, value);
1013 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, NULL, value);
1014 if ((value & 0x3ff) != 0) {
1015 return new_bd_sparc_Or_imm(dbgi, block, hi, NULL, value & 0x3ff);
1022 static ir_mode *get_cmp_mode(ir_node *b_value)
1026 if (!is_Cmp(b_value))
1027 panic("can't determine cond signednes (no cmp)");
1028 op = get_Cmp_left(b_value);
1029 return get_irn_mode(op);
1032 static ir_node *make_address(dbg_info *dbgi, ir_node *block, ir_entity *entity,
1035 ir_node *hi = new_bd_sparc_SetHi(dbgi, block, entity, offset);
1036 ir_node *low = new_bd_sparc_Or_imm(dbgi, block, hi, entity, offset);
1038 if (get_entity_owner(entity) == get_tls_type())
1039 panic("thread local storage not supported yet in sparc backend");
1043 static ir_node *gen_SwitchJmp(ir_node *node)
1045 dbg_info *dbgi = get_irn_dbg_info(node);
1046 ir_node *block = be_transform_node(get_nodes_block(node));
1047 ir_node *selector = get_Cond_selector(node);
1048 ir_node *new_selector = be_transform_node(selector);
1049 long default_pn = get_Cond_default_proj(node);
1051 ir_node *table_address;
1056 /* switch with smaller mode not implemented yet */
1057 assert(get_mode_size_bits(get_irn_mode(selector)) == 32);
1059 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
1060 set_entity_visibility(entity, ir_visibility_private);
1061 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
1063 /* construct base address */
1064 table_address = make_address(dbgi, block, entity, 0);
1066 idx = new_bd_sparc_Sll_imm(dbgi, block, new_selector, NULL, 2);
1067 /* load from jumptable */
1068 load = new_bd_sparc_Ld_reg(dbgi, block, table_address, idx,
1069 get_irg_no_mem(current_ir_graph),
1071 address = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
1073 return new_bd_sparc_SwitchJmp(dbgi, block, address, default_pn, entity);
1076 static ir_node *gen_Cond(ir_node *node)
1078 ir_node *selector = get_Cond_selector(node);
1079 ir_mode *mode = get_irn_mode(selector);
1083 ir_relation relation;
1086 /* switch/case jumps */
1087 if (mode != mode_b) {
1088 return gen_SwitchJmp(node);
1091 block = be_transform_node(get_nodes_block(node));
1092 dbgi = get_irn_dbg_info(node);
1094 /* regular if/else jumps */
1095 if (is_Cmp(selector)) {
1098 cmp_mode = get_cmp_mode(selector);
1099 flag_node = be_transform_node(selector);
1100 relation = get_Cmp_relation(selector);
1101 is_unsigned = !mode_is_signed(cmp_mode);
1102 if (mode_is_float(cmp_mode)) {
1103 assert(!is_unsigned);
1104 return new_bd_sparc_fbfcc(dbgi, block, flag_node, relation);
1106 return new_bd_sparc_Bicc(dbgi, block, flag_node, relation, is_unsigned);
1109 /* in this case, the selector must already deliver a mode_b value.
1110 * this happens, for example, when the Cond is connected to a Conv
1111 * which converts its argument to mode_b. */
1114 assert(mode == mode_b);
1116 block = be_transform_node(get_nodes_block(node));
1117 irg = get_irn_irg(block);
1118 dbgi = get_irn_dbg_info(node);
1119 new_op = be_transform_node(selector);
1120 /* follow the SPARC architecture manual and use orcc for tst */
1121 flag_node = new_bd_sparc_OrCCZero_reg(dbgi, block, new_op, get_g0(irg));
1122 return new_bd_sparc_Bicc(dbgi, block, flag_node, ir_relation_less_greater, true);
1129 static ir_node *gen_Cmp(ir_node *node)
1131 ir_node *op1 = get_Cmp_left(node);
1132 ir_node *op2 = get_Cmp_right(node);
1133 ir_mode *cmp_mode = get_irn_mode(op1);
1134 assert(get_irn_mode(op2) == cmp_mode);
1136 if (mode_is_float(cmp_mode)) {
1137 ir_node *block = be_transform_node(get_nodes_block(node));
1138 dbg_info *dbgi = get_irn_dbg_info(node);
1139 ir_node *new_op1 = be_transform_node(op1);
1140 ir_node *new_op2 = be_transform_node(op2);
1141 unsigned bits = get_mode_size_bits(cmp_mode);
1143 return new_bd_sparc_fcmp_s(dbgi, block, new_op1, new_op2, cmp_mode);
1144 } else if (bits == 64) {
1145 return new_bd_sparc_fcmp_d(dbgi, block, new_op1, new_op2, cmp_mode);
1147 assert(bits == 128);
1148 return new_bd_sparc_fcmp_q(dbgi, block, new_op1, new_op2, cmp_mode);
1152 /* when we compare a bitop like and,or,... with 0 then we can directly use
1153 * the bitopcc variant.
1154 * Currently we only do this when we're the only user of the node...
1156 if (is_Const(op2) && is_Const_null(op2) && get_irn_n_edges(op1) == 1) {
1158 return gen_helper_bitop(op1,
1159 new_bd_sparc_AndCCZero_reg,
1160 new_bd_sparc_AndCCZero_imm,
1161 new_bd_sparc_AndNCCZero_reg,
1162 new_bd_sparc_AndNCCZero_imm,
1164 } else if (is_Or(op1)) {
1165 return gen_helper_bitop(op1,
1166 new_bd_sparc_OrCCZero_reg,
1167 new_bd_sparc_OrCCZero_imm,
1168 new_bd_sparc_OrNCCZero_reg,
1169 new_bd_sparc_OrNCCZero_imm,
1171 } else if (is_Eor(op1)) {
1172 return gen_helper_bitop(op1,
1173 new_bd_sparc_XorCCZero_reg,
1174 new_bd_sparc_XorCCZero_imm,
1175 new_bd_sparc_XNorCCZero_reg,
1176 new_bd_sparc_XNorCCZero_imm,
1181 /* integer compare */
1182 return gen_helper_binop_args(node, op1, op2, MATCH_NONE,
1183 new_bd_sparc_Cmp_reg, new_bd_sparc_Cmp_imm);
1187 * Transforms a SymConst node.
1189 static ir_node *gen_SymConst(ir_node *node)
1191 ir_entity *entity = get_SymConst_entity(node);
1192 dbg_info *dbgi = get_irn_dbg_info(node);
1193 ir_node *block = get_nodes_block(node);
1194 ir_node *new_block = be_transform_node(block);
1195 return make_address(dbgi, new_block, entity, 0);
1198 static ir_node *create_fftof(dbg_info *dbgi, ir_node *block, ir_node *op,
1199 ir_mode *src_mode, ir_mode *dst_mode)
1201 unsigned src_bits = get_mode_size_bits(src_mode);
1202 unsigned dst_bits = get_mode_size_bits(dst_mode);
1203 if (src_bits == 32) {
1204 if (dst_bits == 64) {
1205 return new_bd_sparc_fftof_s_d(dbgi, block, op, src_mode, dst_mode);
1207 assert(dst_bits == 128);
1208 return new_bd_sparc_fftof_s_q(dbgi, block, op, src_mode, dst_mode);
1210 } else if (src_bits == 64) {
1211 if (dst_bits == 32) {
1212 return new_bd_sparc_fftof_d_s(dbgi, block, op, src_mode, dst_mode);
1214 assert(dst_bits == 128);
1215 return new_bd_sparc_fftof_d_q(dbgi, block, op, src_mode, dst_mode);
1218 assert(src_bits == 128);
1219 if (dst_bits == 32) {
1220 return new_bd_sparc_fftof_q_s(dbgi, block, op, src_mode, dst_mode);
1222 assert(dst_bits == 64);
1223 return new_bd_sparc_fftof_q_d(dbgi, block, op, src_mode, dst_mode);
1228 static ir_node *create_ftoi(dbg_info *dbgi, ir_node *block, ir_node *op,
1232 unsigned bits = get_mode_size_bits(src_mode);
1234 ftoi = new_bd_sparc_fftoi_s(dbgi, block, op, src_mode);
1235 } else if (bits == 64) {
1236 ftoi = new_bd_sparc_fftoi_d(dbgi, block, op, src_mode);
1238 assert(bits == 128);
1239 ftoi = new_bd_sparc_fftoi_q(dbgi, block, op, src_mode);
1243 ir_graph *irg = get_irn_irg(block);
1244 ir_node *sp = get_irg_frame(irg);
1245 ir_node *nomem = get_irg_no_mem(irg);
1246 ir_node *stf = create_stf(dbgi, block, ftoi, sp, nomem, src_mode,
1248 ir_node *ld = new_bd_sparc_Ld_imm(dbgi, block, sp, stf, mode_gp,
1250 ir_node *res = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1251 set_irn_pinned(stf, op_pin_state_floats);
1252 set_irn_pinned(ld, op_pin_state_floats);
1257 static ir_node *create_itof(dbg_info *dbgi, ir_node *block, ir_node *op,
1260 ir_graph *irg = get_irn_irg(block);
1261 ir_node *sp = get_irg_frame(irg);
1262 ir_node *nomem = get_irg_no_mem(irg);
1263 ir_node *st = new_bd_sparc_St_imm(dbgi, block, op, sp, nomem,
1264 mode_gp, NULL, 0, true);
1265 ir_node *ldf = new_bd_sparc_Ldf_s(dbgi, block, sp, st, mode_fp,
1267 ir_node *res = new_r_Proj(ldf, mode_fp, pn_sparc_Ldf_res);
1268 unsigned bits = get_mode_size_bits(dst_mode);
1269 set_irn_pinned(st, op_pin_state_floats);
1270 set_irn_pinned(ldf, op_pin_state_floats);
1273 return new_bd_sparc_fitof_s(dbgi, block, res, dst_mode);
1274 } else if (bits == 64) {
1275 return new_bd_sparc_fitof_d(dbgi, block, res, dst_mode);
1277 assert(bits == 128);
1278 return new_bd_sparc_fitof_q(dbgi, block, res, dst_mode);
1282 static ir_node *gen_Conv(ir_node *node)
1284 ir_node *block = be_transform_node(get_nodes_block(node));
1285 ir_node *op = get_Conv_op(node);
1286 ir_mode *src_mode = get_irn_mode(op);
1287 ir_mode *dst_mode = get_irn_mode(node);
1288 dbg_info *dbgi = get_irn_dbg_info(node);
1291 int src_bits = get_mode_size_bits(src_mode);
1292 int dst_bits = get_mode_size_bits(dst_mode);
1294 if (src_mode == mode_b)
1295 panic("ConvB not lowered %+F", node);
1297 new_op = be_transform_node(op);
1298 if (src_mode == dst_mode)
1301 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
1302 assert((src_bits <= 64 && dst_bits <= 64) && "quad FP not implemented");
1304 if (mode_is_float(src_mode)) {
1305 if (mode_is_float(dst_mode)) {
1306 /* float -> float conv */
1307 return create_fftof(dbgi, block, new_op, src_mode, dst_mode);
1309 /* float -> int conv */
1310 if (!mode_is_signed(dst_mode))
1311 panic("float to unsigned not implemented yet");
1312 return create_ftoi(dbgi, block, new_op, src_mode);
1315 /* int -> float conv */
1316 if (src_bits < 32) {
1317 new_op = gen_extension(dbgi, block, new_op, src_mode);
1318 } else if (src_bits == 32 && !mode_is_signed(src_mode)) {
1319 panic("unsigned to float not lowered!");
1321 return create_itof(dbgi, block, new_op, dst_mode);
1323 } else if (src_mode == mode_b) {
1324 panic("ConvB not lowered %+F", node);
1325 } else { /* complete in gp registers */
1329 if (src_bits == dst_bits) {
1330 /* kill unnecessary conv */
1334 if (dst_mode == mode_b) {
1335 /* mode_b lowering already took care that we only have 0/1 values */
1339 if (src_bits < dst_bits) {
1340 min_bits = src_bits;
1341 min_mode = src_mode;
1343 min_bits = dst_bits;
1344 min_mode = dst_mode;
1347 if (upper_bits_clean(new_op, min_mode)) {
1351 if (mode_is_signed(min_mode)) {
1352 return gen_sign_extension(dbgi, block, new_op, min_bits);
1354 return gen_zero_extension(dbgi, block, new_op, min_bits);
1359 static ir_node *gen_Unknown(ir_node *node)
1361 /* just produce a 0 */
1362 ir_mode *mode = get_irn_mode(node);
1363 if (mode_is_float(mode)) {
1364 ir_node *block = be_transform_node(get_nodes_block(node));
1365 return gen_float_const(NULL, block, get_mode_null(mode));
1366 } else if (mode_needs_gp_reg(mode)) {
1367 ir_graph *irg = get_irn_irg(node);
1371 panic("Unexpected Unknown mode");
1375 * transform the start node to the prolog code
1377 static ir_node *gen_Start(ir_node *node)
1379 ir_graph *irg = get_irn_irg(node);
1380 ir_entity *entity = get_irg_entity(irg);
1381 ir_type *function_type = get_entity_type(entity);
1382 ir_node *block = get_nodes_block(node);
1383 ir_node *new_block = be_transform_node(block);
1384 dbg_info *dbgi = get_irn_dbg_info(node);
1385 struct obstack *obst = be_get_be_obst(irg);
1386 const arch_register_req_t *req;
1392 /* start building list of start constraints */
1393 assert(obstack_object_size(obst) == 0);
1395 /* calculate number of outputs */
1396 n_outs = 3; /* memory, zero, sp */
1397 if (!current_cconv->omit_fp)
1398 ++n_outs; /* framepointer */
1399 /* function parameters */
1400 n_outs += current_cconv->n_param_regs;
1402 if (current_cconv->omit_fp) {
1403 n_outs += ARRAY_SIZE(omit_fp_callee_saves);
1406 start = new_bd_sparc_Start(dbgi, new_block, n_outs);
1410 /* first output is memory */
1411 start_mem_offset = o;
1412 arch_set_irn_register_req_out(start, o, arch_no_register_req);
1415 /* the zero register */
1416 start_g0_offset = o;
1417 req = be_create_reg_req(obst, &sparc_registers[REG_G0],
1418 arch_register_req_type_ignore);
1419 arch_set_irn_register_req_out(start, o, req);
1420 arch_set_irn_register_out(start, o, &sparc_registers[REG_G0]);
1423 /* we need an output for the stackpointer */
1424 start_sp_offset = o;
1425 req = be_create_reg_req(obst, sp_reg,
1426 arch_register_req_type_produces_sp | arch_register_req_type_ignore);
1427 arch_set_irn_register_req_out(start, o, req);
1428 arch_set_irn_register_out(start, o, sp_reg);
1431 if (!current_cconv->omit_fp) {
1432 start_fp_offset = o;
1433 req = be_create_reg_req(obst, fp_reg, arch_register_req_type_ignore);
1434 arch_set_irn_register_req_out(start, o, req);
1435 arch_set_irn_register_out(start, o, fp_reg);
1439 /* function parameters in registers */
1440 start_params_offset = o;
1441 for (i = 0; i < get_method_n_params(function_type); ++i) {
1442 const reg_or_stackslot_t *param = ¤t_cconv->parameters[i];
1443 const arch_register_t *reg0 = param->reg0;
1444 const arch_register_t *reg1 = param->reg1;
1446 arch_set_irn_register_req_out(start, o, reg0->single_req);
1447 arch_set_irn_register_out(start, o, reg0);
1451 arch_set_irn_register_req_out(start, o, reg1->single_req);
1452 arch_set_irn_register_out(start, o, reg1);
1456 /* we need the values of the callee saves (Note: non omit-fp mode has no
1458 start_callee_saves_offset = o;
1459 if (current_cconv->omit_fp) {
1460 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1462 for (c = 0; c < n_callee_saves; ++c) {
1463 const arch_register_t *reg = omit_fp_callee_saves[c];
1464 arch_set_irn_register_req_out(start, o, reg->single_req);
1465 arch_set_irn_register_out(start, o, reg);
1469 assert(n_outs == o);
1474 static ir_node *get_initial_sp(ir_graph *irg)
1476 if (start_sp == NULL) {
1477 ir_node *start = get_irg_start(irg);
1478 start_sp = new_r_Proj(start, mode_gp, start_sp_offset);
1483 static ir_node *get_initial_fp(ir_graph *irg)
1485 if (start_fp == NULL) {
1486 ir_node *start = get_irg_start(irg);
1487 start_fp = new_r_Proj(start, mode_gp, start_fp_offset);
1492 static ir_node *get_initial_mem(ir_graph *irg)
1494 if (start_mem == NULL) {
1495 ir_node *start = get_irg_start(irg);
1496 start_mem = new_r_Proj(start, mode_M, start_mem_offset);
1501 static ir_node *get_stack_pointer_for(ir_node *node)
1503 /* get predecessor in stack_order list */
1504 ir_node *stack_pred = be_get_stack_pred(stackorder, node);
1507 if (stack_pred == NULL) {
1508 /* first stack user in the current block. We can simply use the
1509 * initial sp_proj for it */
1510 ir_graph *irg = get_irn_irg(node);
1511 return get_initial_sp(irg);
1514 be_transform_node(stack_pred);
1515 stack = (ir_node*)pmap_get(node_to_stack, stack_pred);
1516 if (stack == NULL) {
1517 return get_stack_pointer_for(stack_pred);
1524 * transform a Return node into epilogue code + return statement
1526 static ir_node *gen_Return(ir_node *node)
1528 ir_node *block = get_nodes_block(node);
1529 ir_graph *irg = get_irn_irg(node);
1530 ir_node *new_block = be_transform_node(block);
1531 dbg_info *dbgi = get_irn_dbg_info(node);
1532 ir_node *mem = get_Return_mem(node);
1533 ir_node *new_mem = be_transform_node(mem);
1534 ir_node *sp = get_stack_pointer_for(node);
1535 size_t n_res = get_Return_n_ress(node);
1536 struct obstack *be_obst = be_get_be_obst(irg);
1539 const arch_register_req_t **reqs;
1544 /* estimate number of return values */
1545 n_ins = 2 + n_res; /* memory + stackpointer, return values */
1546 if (current_cconv->omit_fp)
1547 n_ins += ARRAY_SIZE(omit_fp_callee_saves);
1549 in = ALLOCAN(ir_node*, n_ins);
1550 reqs = OALLOCN(be_obst, const arch_register_req_t*, n_ins);
1554 reqs[p] = arch_no_register_req;
1558 reqs[p] = sp_reg->single_req;
1562 for (i = 0; i < n_res; ++i) {
1563 ir_node *res_value = get_Return_res(node, i);
1564 ir_node *new_res_value = be_transform_node(res_value);
1565 const reg_or_stackslot_t *slot = ¤t_cconv->results[i];
1566 assert(slot->req1 == NULL);
1567 in[p] = new_res_value;
1568 reqs[p] = slot->req0;
1572 if (current_cconv->omit_fp) {
1573 ir_node *start = get_irg_start(irg);
1574 size_t n_callee_saves = ARRAY_SIZE(omit_fp_callee_saves);
1575 for (i = 0; i < n_callee_saves; ++i) {
1576 const arch_register_t *reg = omit_fp_callee_saves[i];
1577 ir_mode *mode = reg->reg_class->mode;
1579 = new_r_Proj(start, mode, i + start_callee_saves_offset);
1581 reqs[p] = reg->single_req;
1587 bereturn = new_bd_sparc_Return_reg(dbgi, new_block, n_ins, in);
1588 arch_set_irn_register_reqs_in(bereturn, reqs);
1593 static ir_node *bitcast_int_to_float(dbg_info *dbgi, ir_node *block,
1594 ir_node *value0, ir_node *value1)
1596 ir_graph *irg = current_ir_graph;
1597 ir_node *sp = get_irg_frame(irg);
1598 ir_node *nomem = get_irg_no_mem(irg);
1599 ir_node *st = new_bd_sparc_St_imm(dbgi, block, value0, sp, nomem,
1600 mode_gp, NULL, 0, true);
1604 set_irn_pinned(st, op_pin_state_floats);
1606 if (value1 != NULL) {
1607 ir_node *st1 = new_bd_sparc_St_imm(dbgi, block, value1, sp, nomem,
1608 mode_gp, NULL, 4, true);
1609 ir_node *in[2] = { st, st1 };
1610 ir_node *sync = new_r_Sync(block, 2, in);
1611 set_irn_pinned(st1, op_pin_state_floats);
1619 ldf = create_ldf(dbgi, block, sp, mem, mode, NULL, 0, true);
1620 set_irn_pinned(ldf, op_pin_state_floats);
1622 return new_r_Proj(ldf, mode, pn_sparc_Ldf_res);
1625 static void bitcast_float_to_int(dbg_info *dbgi, ir_node *block,
1626 ir_node *node, ir_mode *float_mode,
1629 ir_graph *irg = current_ir_graph;
1630 ir_node *stack = get_irg_frame(irg);
1631 ir_node *nomem = get_irg_no_mem(irg);
1632 ir_node *stf = create_stf(dbgi, block, node, stack, nomem, float_mode,
1634 int bits = get_mode_size_bits(float_mode);
1636 set_irn_pinned(stf, op_pin_state_floats);
1638 ld = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp, NULL, 0, true);
1639 set_irn_pinned(ld, op_pin_state_floats);
1640 result[0] = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
1643 ir_node *ld2 = new_bd_sparc_Ld_imm(dbgi, block, stack, stf, mode_gp,
1645 set_irn_pinned(ld, op_pin_state_floats);
1646 result[1] = new_r_Proj(ld2, mode_gp, pn_sparc_Ld_res);
1648 arch_add_irn_flags(ld, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1649 arch_add_irn_flags(ld2, (arch_irn_flags_t)sparc_arch_irn_flag_needs_64bit_spillslot);
1656 static ir_node *gen_Call(ir_node *node)
1658 ir_graph *irg = get_irn_irg(node);
1659 ir_node *callee = get_Call_ptr(node);
1660 ir_node *block = get_nodes_block(node);
1661 ir_node *new_block = be_transform_node(block);
1662 ir_node *mem = get_Call_mem(node);
1663 ir_node *new_mem = be_transform_node(mem);
1664 dbg_info *dbgi = get_irn_dbg_info(node);
1665 ir_type *type = get_Call_type(node);
1666 size_t n_params = get_Call_n_params(node);
1667 size_t n_ress = get_method_n_ress(type);
1668 /* max inputs: memory, callee, register arguments */
1669 ir_node **sync_ins = ALLOCAN(ir_node*, n_params);
1670 struct obstack *obst = be_get_be_obst(irg);
1671 calling_convention_t *cconv
1672 = sparc_decide_calling_convention(type, NULL);
1673 size_t n_param_regs = cconv->n_param_regs;
1674 /* param-regs + mem + stackpointer + callee */
1675 unsigned max_inputs = 3 + n_param_regs;
1676 ir_node **in = ALLOCAN(ir_node*, max_inputs);
1677 const arch_register_req_t **in_req
1678 = OALLOCNZ(obst, const arch_register_req_t*, max_inputs);
1682 = rbitset_popcount(cconv->caller_saves, N_SPARC_REGISTERS);
1683 ir_entity *entity = NULL;
1684 ir_node *new_frame = get_stack_pointer_for(node);
1685 bool aggregate_return
1686 = type->attr.ma.has_compound_ret_parameter;
1696 assert(n_params == get_method_n_params(type));
1698 /* construct arguments */
1701 in_req[in_arity] = arch_no_register_req;
1705 /* stack pointer input */
1706 /* construct an IncSP -> we have to always be sure that the stack is
1707 * aligned even if we don't push arguments on it */
1708 incsp = be_new_IncSP(sp_reg, new_block, new_frame,
1709 cconv->param_stack_size, 1);
1710 in_req[in_arity] = sp_reg->single_req;
1711 in[in_arity] = incsp;
1715 for (p = 0; p < n_params; ++p) {
1716 ir_node *value = get_Call_param(node, p);
1717 ir_node *new_value = be_transform_node(value);
1718 const reg_or_stackslot_t *param = &cconv->parameters[p];
1719 ir_type *param_type = get_method_param_type(type, p);
1720 ir_mode *mode = get_type_mode(param_type);
1721 ir_node *new_values[2];
1725 if (mode_is_float(mode) && param->reg0 != NULL) {
1726 unsigned size_bits = get_mode_size_bits(mode);
1727 assert(size_bits <= 64);
1728 bitcast_float_to_int(dbgi, new_block, new_value, mode, new_values);
1730 new_values[0] = new_value;
1731 new_values[1] = NULL;
1734 /* put value into registers */
1735 if (param->reg0 != NULL) {
1736 in[in_arity] = new_values[0];
1737 in_req[in_arity] = param->reg0->single_req;
1739 if (new_values[1] == NULL)
1742 if (param->reg1 != NULL) {
1743 assert(new_values[1] != NULL);
1744 in[in_arity] = new_values[1];
1745 in_req[in_arity] = param->reg1->single_req;
1750 /* we need a store if we're here */
1751 if (new_values[1] != NULL) {
1752 new_value = new_values[1];
1756 /* we need to skip over our save area when constructing the call
1757 * arguments on stack */
1758 offset = param->offset + SPARC_MIN_STACKSIZE;
1760 if (mode_is_float(mode)) {
1761 str = create_stf(dbgi, new_block, new_value, incsp, new_mem,
1762 mode, NULL, offset, true);
1764 str = new_bd_sparc_St_imm(dbgi, new_block, new_value, incsp,
1765 new_mem, mode, NULL, offset, true);
1767 set_irn_pinned(str, op_pin_state_floats);
1768 sync_ins[sync_arity++] = str;
1771 /* construct memory input */
1772 if (sync_arity == 0) {
1773 in[mem_pos] = new_mem;
1774 } else if (sync_arity == 1) {
1775 in[mem_pos] = sync_ins[0];
1777 in[mem_pos] = new_rd_Sync(NULL, new_block, sync_arity, sync_ins);
1780 if (is_SymConst(callee)) {
1781 entity = get_SymConst_entity(callee);
1783 in[in_arity] = be_transform_node(callee);
1784 in_req[in_arity] = sparc_reg_classes[CLASS_sparc_gp].class_req;
1787 assert(in_arity <= (int)max_inputs);
1794 out_arity = 1 + cconv->n_reg_results + n_caller_saves;
1796 /* create call node */
1797 if (entity != NULL) {
1798 res = new_bd_sparc_Call_imm(dbgi, new_block, in_arity, in, out_arity,
1799 entity, 0, aggregate_return);
1801 res = new_bd_sparc_Call_reg(dbgi, new_block, in_arity, in, out_arity,
1804 arch_set_irn_register_reqs_in(res, in_req);
1806 /* create output register reqs */
1808 arch_set_irn_register_req_out(res, o++, arch_no_register_req);
1809 /* add register requirements for the result regs */
1810 for (r = 0; r < n_ress; ++r) {
1811 const reg_or_stackslot_t *result_info = &cconv->results[r];
1812 const arch_register_req_t *req = result_info->req0;
1814 arch_set_irn_register_req_out(res, o++, req);
1816 assert(result_info->req1 == NULL);
1818 for (i = 0; i < N_SPARC_REGISTERS; ++i) {
1819 const arch_register_t *reg;
1820 if (!rbitset_is_set(cconv->caller_saves, i))
1822 reg = &sparc_registers[i];
1823 arch_set_irn_register_req_out(res, o++, reg->single_req);
1825 assert(o == out_arity);
1827 /* copy pinned attribute */
1828 set_irn_pinned(res, get_irn_pinned(node));
1830 /* IncSP to destroy the call stackframe */
1831 incsp = be_new_IncSP(sp_reg, new_block, incsp, -cconv->param_stack_size, 0);
1832 /* if we are the last IncSP producer in a block then we have to keep
1834 * Note: This here keeps all producers which is more than necessary */
1835 add_irn_dep(incsp, res);
1838 pmap_insert(node_to_stack, node, incsp);
1840 sparc_free_calling_convention(cconv);
1844 static ir_node *gen_Sel(ir_node *node)
1846 dbg_info *dbgi = get_irn_dbg_info(node);
1847 ir_node *block = get_nodes_block(node);
1848 ir_node *new_block = be_transform_node(block);
1849 ir_node *ptr = get_Sel_ptr(node);
1850 ir_node *new_ptr = be_transform_node(ptr);
1851 ir_entity *entity = get_Sel_entity(node);
1853 /* must be the frame pointer all other sels must have been lowered
1855 assert(is_Proj(ptr) && is_Start(get_Proj_pred(ptr)));
1857 return new_bd_sparc_FrameAddr(dbgi, new_block, new_ptr, entity, 0);
1860 static ir_node *gen_Alloc(ir_node *node)
1862 dbg_info *dbgi = get_irn_dbg_info(node);
1863 ir_node *block = get_nodes_block(node);
1864 ir_node *new_block = be_transform_node(block);
1865 ir_type *type = get_Alloc_type(node);
1866 ir_node *size = get_Alloc_count(node);
1867 ir_node *stack_pred = get_stack_pointer_for(node);
1869 if (get_Alloc_where(node) != stack_alloc)
1870 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1871 /* lowerer should have transformed all allocas to byte size */
1872 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1873 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1875 if (is_Const(size)) {
1876 ir_tarval *tv = get_Const_tarval(size);
1877 long sizel = get_tarval_long(tv);
1878 subsp = be_new_IncSP(sp_reg, new_block, stack_pred, sizel, 0);
1879 set_irn_dbg_info(subsp, dbgi);
1881 ir_node *new_size = be_transform_node(size);
1882 subsp = new_bd_sparc_SubSP(dbgi, new_block, stack_pred, new_size);
1883 arch_set_irn_register(subsp, sp_reg);
1886 /* if we are the last IncSP producer in a block then we have to keep
1888 * Note: This here keeps all producers which is more than necessary */
1891 pmap_insert(node_to_stack, node, subsp);
1892 /* the "result" is the unmodified sp value */
1896 static ir_node *gen_Proj_Alloc(ir_node *node)
1898 ir_node *alloc = get_Proj_pred(node);
1899 long pn = get_Proj_proj(node);
1901 switch ((pn_Alloc)pn) {
1903 ir_node *alloc_mem = get_Alloc_mem(alloc);
1904 return be_transform_node(alloc_mem);
1906 case pn_Alloc_res: {
1907 ir_node *new_alloc = be_transform_node(alloc);
1910 case pn_Alloc_X_regular:
1911 case pn_Alloc_X_except:
1912 panic("sparc backend: exception output of alloc not supported (at %+F)",
1915 panic("sparc backend: invalid Proj->Alloc");
1918 static ir_node *gen_Free(ir_node *node)
1920 dbg_info *dbgi = get_irn_dbg_info(node);
1921 ir_node *block = get_nodes_block(node);
1922 ir_node *new_block = be_transform_node(block);
1923 ir_type *type = get_Free_type(node);
1924 ir_node *size = get_Free_count(node);
1925 ir_node *mem = get_Free_mem(node);
1926 ir_node *new_mem = be_transform_node(mem);
1927 ir_node *stack_pred = get_stack_pointer_for(node);
1929 if (get_Alloc_where(node) != stack_alloc)
1930 panic("only stack-alloc supported in sparc backend (at %+F)", node);
1931 /* lowerer should have transformed all allocas to byte size */
1932 if (type != get_unknown_type() && get_type_size_bytes(type) != 1)
1933 panic("Found non-byte alloc in sparc backend (at %+F)", node);
1935 if (is_Const(size)) {
1936 ir_tarval *tv = get_Const_tarval(size);
1937 long sizel = get_tarval_long(tv);
1938 addsp = be_new_IncSP(sp_reg, new_block, stack_pred, -sizel, 0);
1939 set_irn_dbg_info(addsp, dbgi);
1941 ir_node *new_size = be_transform_node(size);
1942 addsp = new_bd_sparc_AddSP(dbgi, new_block, stack_pred, new_size);
1943 arch_set_irn_register(addsp, sp_reg);
1946 /* if we are the last IncSP producer in a block then we have to keep
1948 * Note: This here keeps all producers which is more than necessary */
1951 pmap_insert(node_to_stack, node, addsp);
1952 /* the "result" is the unmodified sp value */
1956 static const arch_register_req_t float1_req = {
1957 arch_register_req_type_normal,
1958 &sparc_reg_classes[CLASS_sparc_fp],
1964 static const arch_register_req_t float2_req = {
1965 arch_register_req_type_normal | arch_register_req_type_aligned,
1966 &sparc_reg_classes[CLASS_sparc_fp],
1972 static const arch_register_req_t float4_req = {
1973 arch_register_req_type_normal | arch_register_req_type_aligned,
1974 &sparc_reg_classes[CLASS_sparc_fp],
1982 static const arch_register_req_t *get_float_req(ir_mode *mode)
1984 unsigned bits = get_mode_size_bits(mode);
1986 assert(mode_is_float(mode));
1989 } else if (bits == 64) {
1992 assert(bits == 128);
1998 * Transform some Phi nodes
2000 static ir_node *gen_Phi(ir_node *node)
2002 const arch_register_req_t *req;
2003 ir_node *block = be_transform_node(get_nodes_block(node));
2004 ir_graph *irg = current_ir_graph;
2005 dbg_info *dbgi = get_irn_dbg_info(node);
2006 ir_mode *mode = get_irn_mode(node);
2009 if (mode_needs_gp_reg(mode)) {
2010 /* we shouldn't have any 64bit stuff around anymore */
2011 assert(get_mode_size_bits(mode) <= 32);
2012 /* all integer operations are on 32bit registers now */
2014 req = sparc_reg_classes[CLASS_sparc_gp].class_req;
2015 } else if (mode_is_float(mode)) {
2017 req = get_float_req(mode);
2019 req = arch_no_register_req;
2022 /* phi nodes allow loops, so we use the old arguments for now
2023 * and fix this later */
2024 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2025 copy_node_attr(irg, node, phi);
2026 be_duplicate_deps(node, phi);
2027 arch_set_irn_register_req_out(phi, 0, req);
2028 be_enqueue_preds(node);
2033 * Transform a Proj from a Load.
2035 static ir_node *gen_Proj_Load(ir_node *node)
2037 ir_node *load = get_Proj_pred(node);
2038 ir_node *new_load = be_transform_node(load);
2039 dbg_info *dbgi = get_irn_dbg_info(node);
2040 long pn = get_Proj_proj(node);
2042 /* renumber the proj */
2043 switch (get_sparc_irn_opcode(new_load)) {
2045 /* handle all gp loads equal: they have the same proj numbers. */
2046 if (pn == pn_Load_res) {
2047 return new_rd_Proj(dbgi, new_load, mode_gp, pn_sparc_Ld_res);
2048 } else if (pn == pn_Load_M) {
2049 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2053 if (pn == pn_Load_res) {
2054 const sparc_load_store_attr_t *attr
2055 = get_sparc_load_store_attr_const(new_load);
2056 ir_mode *mode = attr->load_store_mode;
2057 return new_rd_Proj(dbgi, new_load, mode, pn_sparc_Ldf_res);
2058 } else if (pn == pn_Load_M) {
2059 return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
2065 panic("Unsupported Proj from Load");
2068 static ir_node *gen_Proj_Store(ir_node *node)
2070 ir_node *store = get_Proj_pred(node);
2071 ir_node *new_store = be_transform_node(store);
2072 long pn = get_Proj_proj(node);
2074 /* renumber the proj */
2075 switch (get_sparc_irn_opcode(new_store)) {
2077 if (pn == pn_Store_M) {
2082 if (pn == pn_Store_M) {
2089 panic("Unsupported Proj from Store");
2093 * Transform the Projs from a Cmp.
2095 static ir_node *gen_Proj_Cmp(ir_node *node)
2098 panic("not implemented");
2102 * transform Projs from a Div
2104 static ir_node *gen_Proj_Div(ir_node *node)
2106 ir_node *pred = get_Proj_pred(node);
2107 ir_node *new_pred = be_transform_node(pred);
2108 long pn = get_Proj_proj(node);
2111 if (is_sparc_SDiv(new_pred) || is_sparc_UDiv(new_pred)) {
2113 } else if (is_sparc_fdiv(new_pred)) {
2114 res_mode = get_Div_resmode(pred);
2116 panic("sparc backend: Div transformed to something unexpected: %+F",
2119 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_UDiv_res);
2120 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_UDiv_M);
2121 assert((int)pn_sparc_SDiv_res == (int)pn_sparc_fdiv_res);
2122 assert((int)pn_sparc_SDiv_M == (int)pn_sparc_fdiv_M);
2125 return new_r_Proj(new_pred, res_mode, pn_sparc_SDiv_res);
2127 return new_r_Proj(new_pred, mode_gp, pn_sparc_SDiv_M);
2131 panic("Unsupported Proj from Div");
2134 static ir_node *get_frame_base(ir_graph *irg)
2136 if (frame_base == NULL) {
2137 if (current_cconv->omit_fp) {
2138 frame_base = get_initial_sp(irg);
2140 frame_base = get_initial_fp(irg);
2146 static ir_node *gen_Proj_Start(ir_node *node)
2148 ir_node *block = get_nodes_block(node);
2149 ir_node *new_block = be_transform_node(block);
2150 long pn = get_Proj_proj(node);
2151 /* make sure prolog is constructed */
2152 be_transform_node(get_Proj_pred(node));
2154 switch ((pn_Start) pn) {
2155 case pn_Start_X_initial_exec:
2156 /* exchange ProjX with a jump */
2157 return new_bd_sparc_Ba(NULL, new_block);
2159 ir_graph *irg = get_irn_irg(node);
2160 return get_initial_mem(irg);
2162 case pn_Start_T_args:
2163 return new_r_Bad(get_irn_irg(block), mode_T);
2164 case pn_Start_P_frame_base:
2165 return get_frame_base(get_irn_irg(block));
2167 panic("Unexpected start proj: %ld\n", pn);
2170 static ir_node *gen_Proj_Proj_Start(ir_node *node)
2172 long pn = get_Proj_proj(node);
2173 ir_node *block = get_nodes_block(node);
2174 ir_graph *irg = get_irn_irg(node);
2175 ir_node *new_block = be_transform_node(block);
2176 ir_node *args = get_Proj_pred(node);
2177 ir_node *start = get_Proj_pred(args);
2178 ir_node *new_start = be_transform_node(start);
2179 const reg_or_stackslot_t *param;
2181 /* Proj->Proj->Start must be a method argument */
2182 assert(get_Proj_proj(get_Proj_pred(node)) == pn_Start_T_args);
2184 param = ¤t_cconv->parameters[pn];
2186 if (param->reg0 != NULL) {
2187 /* argument transmitted in register */
2188 const arch_register_t *reg = param->reg0;
2189 ir_mode *reg_mode = reg->reg_class->mode;
2190 long new_pn = param->reg_offset + start_params_offset;
2191 ir_node *value = new_r_Proj(new_start, reg_mode, new_pn);
2192 bool is_float = false;
2195 ir_entity *entity = get_irg_entity(irg);
2196 ir_type *method_type = get_entity_type(entity);
2197 if (pn < (long)get_method_n_params(method_type)) {
2198 ir_type *param_type = get_method_param_type(method_type, pn);
2199 ir_mode *mode = get_type_mode(param_type);
2200 is_float = mode_is_float(mode);
2205 const arch_register_t *reg1 = param->reg1;
2206 ir_node *value1 = NULL;
2209 ir_mode *reg1_mode = reg1->reg_class->mode;
2210 value1 = new_r_Proj(new_start, reg1_mode, new_pn+1);
2211 } else if (param->entity != NULL) {
2212 ir_node *fp = get_initial_fp(irg);
2213 ir_node *mem = get_initial_mem(irg);
2214 ir_node *ld = new_bd_sparc_Ld_imm(NULL, new_block, fp, mem,
2215 mode_gp, param->entity,
2217 value1 = new_r_Proj(ld, mode_gp, pn_sparc_Ld_res);
2220 /* convert integer value to float */
2221 value = bitcast_int_to_float(NULL, new_block, value, value1);
2225 /* argument transmitted on stack */
2226 ir_node *mem = get_initial_mem(irg);
2227 ir_mode *mode = get_type_mode(param->type);
2228 ir_node *base = get_frame_base(irg);
2232 if (mode_is_float(mode)) {
2233 load = create_ldf(NULL, new_block, base, mem, mode,
2234 param->entity, 0, true);
2235 value = new_r_Proj(load, mode_fp, pn_sparc_Ldf_res);
2237 load = new_bd_sparc_Ld_imm(NULL, new_block, base, mem, mode,
2238 param->entity, 0, true);
2239 value = new_r_Proj(load, mode_gp, pn_sparc_Ld_res);
2241 set_irn_pinned(load, op_pin_state_floats);
2247 static ir_node *gen_Proj_Call(ir_node *node)
2249 long pn = get_Proj_proj(node);
2250 ir_node *call = get_Proj_pred(node);
2251 ir_node *new_call = be_transform_node(call);
2253 switch ((pn_Call) pn) {
2255 return new_r_Proj(new_call, mode_M, 0);
2256 case pn_Call_X_regular:
2257 case pn_Call_X_except:
2258 case pn_Call_T_result:
2261 panic("Unexpected Call proj %ld\n", pn);
2264 static ir_node *gen_Proj_Proj_Call(ir_node *node)
2266 long pn = get_Proj_proj(node);
2267 ir_node *call = get_Proj_pred(get_Proj_pred(node));
2268 ir_node *new_call = be_transform_node(call);
2269 ir_type *function_type = get_Call_type(call);
2270 calling_convention_t *cconv
2271 = sparc_decide_calling_convention(function_type, NULL);
2272 const reg_or_stackslot_t *res = &cconv->results[pn];
2273 ir_mode *mode = get_irn_mode(node);
2274 long new_pn = 1 + res->reg_offset;
2276 assert(res->req0 != NULL && res->req1 == NULL);
2277 if (mode_needs_gp_reg(mode)) {
2280 sparc_free_calling_convention(cconv);
2282 return new_r_Proj(new_call, mode, new_pn);
2286 * Transform a Proj node.
2288 static ir_node *gen_Proj(ir_node *node)
2290 ir_node *pred = get_Proj_pred(node);
2292 switch (get_irn_opcode(pred)) {
2294 return gen_Proj_Alloc(node);
2296 return gen_Proj_Store(node);
2298 return gen_Proj_Load(node);
2300 return gen_Proj_Call(node);
2302 return gen_Proj_Cmp(node);
2304 return be_duplicate_node(node);
2306 return gen_Proj_Div(node);
2308 return gen_Proj_Start(node);
2310 ir_node *pred_pred = get_Proj_pred(pred);
2311 if (is_Call(pred_pred)) {
2312 return gen_Proj_Proj_Call(node);
2313 } else if (is_Start(pred_pred)) {
2314 return gen_Proj_Proj_Start(node);
2319 if (is_sparc_AddCC_t(pred)) {
2320 return gen_Proj_AddCC_t(node);
2321 } else if (is_sparc_SubCC_t(pred)) {
2322 return gen_Proj_SubCC_t(node);
2324 panic("code selection didn't expect Proj after %+F\n", pred);
2331 static ir_node *gen_Jmp(ir_node *node)
2333 ir_node *block = get_nodes_block(node);
2334 ir_node *new_block = be_transform_node(block);
2335 dbg_info *dbgi = get_irn_dbg_info(node);
2337 return new_bd_sparc_Ba(dbgi, new_block);
2341 * configure transformation callbacks
2343 static void sparc_register_transformers(void)
2345 be_start_transform_setup();
2347 be_set_transform_function(op_Add, gen_Add);
2348 be_set_transform_function(op_Alloc, gen_Alloc);
2349 be_set_transform_function(op_And, gen_And);
2350 be_set_transform_function(op_Call, gen_Call);
2351 be_set_transform_function(op_Cmp, gen_Cmp);
2352 be_set_transform_function(op_Cond, gen_Cond);
2353 be_set_transform_function(op_Const, gen_Const);
2354 be_set_transform_function(op_Conv, gen_Conv);
2355 be_set_transform_function(op_Div, gen_Div);
2356 be_set_transform_function(op_Eor, gen_Eor);
2357 be_set_transform_function(op_Free, gen_Free);
2358 be_set_transform_function(op_Jmp, gen_Jmp);
2359 be_set_transform_function(op_Load, gen_Load);
2360 be_set_transform_function(op_Minus, gen_Minus);
2361 be_set_transform_function(op_Mul, gen_Mul);
2362 be_set_transform_function(op_Mulh, gen_Mulh);
2363 be_set_transform_function(op_Not, gen_Not);
2364 be_set_transform_function(op_Or, gen_Or);
2365 be_set_transform_function(op_Phi, gen_Phi);
2366 be_set_transform_function(op_Proj, gen_Proj);
2367 be_set_transform_function(op_Return, gen_Return);
2368 be_set_transform_function(op_Sel, gen_Sel);
2369 be_set_transform_function(op_Shl, gen_Shl);
2370 be_set_transform_function(op_Shr, gen_Shr);
2371 be_set_transform_function(op_Shrs, gen_Shrs);
2372 be_set_transform_function(op_Start, gen_Start);
2373 be_set_transform_function(op_Store, gen_Store);
2374 be_set_transform_function(op_Sub, gen_Sub);
2375 be_set_transform_function(op_SymConst, gen_SymConst);
2376 be_set_transform_function(op_Unknown, gen_Unknown);
2378 be_set_transform_function(op_sparc_AddX_t, gen_AddX_t);
2379 be_set_transform_function(op_sparc_AddCC_t,gen_AddCC_t);
2380 be_set_transform_function(op_sparc_Save, be_duplicate_node);
2381 be_set_transform_function(op_sparc_SubX_t, gen_SubX_t);
2382 be_set_transform_function(op_sparc_SubCC_t,gen_SubCC_t);
2386 * Transform a Firm graph into a SPARC graph.
2388 void sparc_transform_graph(ir_graph *irg)
2390 ir_entity *entity = get_irg_entity(irg);
2391 ir_type *frame_type;
2393 sparc_register_transformers();
2395 node_to_stack = pmap_create();
2400 mode_flags = mode_Bu;
2409 stackorder = be_collect_stacknodes(irg);
2411 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2412 if (sparc_variadic_fixups(irg, current_cconv)) {
2413 sparc_free_calling_convention(current_cconv);
2415 = sparc_decide_calling_convention(get_entity_type(entity), irg);
2417 sparc_create_stacklayout(irg, current_cconv);
2418 be_add_parameter_entity_stores(irg);
2420 be_transform_graph(irg, NULL);
2422 be_free_stackorder(stackorder);
2423 sparc_free_calling_convention(current_cconv);
2425 frame_type = get_irg_frame_type(irg);
2426 if (get_type_state(frame_type) == layout_undefined)
2427 default_layout_compound_type(frame_type);
2429 pmap_destroy(node_to_stack);
2430 node_to_stack = NULL;
2432 be_add_missing_keeps(irg);
2434 /* do code placement, to optimize the position of constants */
2438 void sparc_init_transform(void)
2440 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.transform");