2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
40 #include "raw_bitset.h"
44 #include "../besched.h"
45 #include "../beblocksched.h"
47 #include "../begnuas.h"
48 #include "../be_dbgout.h"
49 #include "../benode.h"
50 #include "../bestack.h"
52 #include "sparc_emitter.h"
53 #include "gen_sparc_emitter.h"
54 #include "sparc_nodes_attr.h"
55 #include "sparc_new_nodes.h"
56 #include "gen_sparc_regalloc_if.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static ir_heights_t *heights;
61 static const ir_node *delay_slot_filler; /**< this node has been choosen to fill
62 the next delay slot */
64 static void sparc_emit_node(const ir_node *node);
67 * Returns the register at in position pos.
69 static const arch_register_t *get_in_reg(const ir_node *node, int pos)
72 const arch_register_t *reg = NULL;
74 assert(get_irn_arity(node) > pos && "Invalid IN position");
76 /* The out register of the operator at position pos is the
77 in register we need. */
78 op = get_irn_n(node, pos);
80 reg = arch_get_irn_register(op);
82 assert(reg && "no in register found");
87 * Returns the register at out position pos.
89 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
92 const arch_register_t *reg = NULL;
94 /* 1st case: irn is not of mode_T, so it has only */
95 /* one OUT register -> good */
96 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
97 /* Proj with the corresponding projnum for the register */
99 if (get_irn_mode(node) != mode_T) {
100 reg = arch_get_irn_register(node);
101 } else if (is_sparc_irn(node)) {
102 reg = arch_irn_get_register(node, pos);
104 const ir_edge_t *edge;
106 foreach_out_edge(node, edge) {
107 proj = get_edge_src_irn(edge);
108 assert(is_Proj(proj) && "non-Proj from mode_T node");
109 if (get_Proj_proj(proj) == pos) {
110 reg = arch_get_irn_register(proj);
116 assert(reg && "no out register found");
120 static bool is_valid_immediate(int32_t value)
122 return -4096 <= value && value < 4096;
125 void sparc_emit_immediate(const ir_node *node)
127 const sparc_attr_t *attr = get_sparc_attr_const(node);
128 ir_entity *entity = attr->immediate_value_entity;
130 if (entity == NULL) {
131 int32_t value = attr->immediate_value;
132 assert(is_valid_immediate(value));
133 be_emit_irprintf("%d", value);
135 be_emit_cstring("%lo(");
136 be_gas_emit_entity(entity);
137 if (attr->immediate_value != 0) {
138 be_emit_irprintf("%+d", attr->immediate_value);
144 void sparc_emit_high_immediate(const ir_node *node)
146 const sparc_attr_t *attr = get_sparc_attr_const(node);
147 ir_entity *entity = attr->immediate_value_entity;
149 be_emit_cstring("%hi(");
150 if (entity == NULL) {
151 uint32_t value = (uint32_t) attr->immediate_value;
152 be_emit_irprintf("0x%X", value);
154 be_gas_emit_entity(entity);
155 if (attr->immediate_value != 0) {
156 be_emit_irprintf("%+d", attr->immediate_value);
162 void sparc_emit_source_register(const ir_node *node, int pos)
164 const arch_register_t *reg = get_in_reg(node, pos);
166 be_emit_string(arch_register_get_name(reg));
169 void sparc_emit_dest_register(const ir_node *node, int pos)
171 const arch_register_t *reg = get_out_reg(node, pos);
173 be_emit_string(arch_register_get_name(reg));
177 * Emits either a imm or register depending on arity of node
179 * @param register no (-1 if no register)
181 void sparc_emit_reg_or_imm(const ir_node *node, int pos)
183 if (get_irn_arity(node) > pos) {
185 sparc_emit_source_register(node, pos);
187 // we have a imm input
188 sparc_emit_immediate(node);
192 static bool is_stack_pointer_relative(const ir_node *node)
194 const arch_register_t *sp = &sparc_registers[REG_SP];
195 return (is_sparc_St(node) && get_in_reg(node, n_sparc_St_ptr) == sp)
196 || (is_sparc_Ld(node) && get_in_reg(node, n_sparc_Ld_ptr) == sp);
202 void sparc_emit_offset(const ir_node *node, int offset_node_pos)
204 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
206 if (attr->is_reg_reg) {
207 assert(!attr->is_frame_entity);
208 assert(attr->base.immediate_value == 0);
209 assert(attr->base.immediate_value_entity == NULL);
211 sparc_emit_source_register(node, offset_node_pos);
212 } else if (attr->is_frame_entity) {
213 int32_t offset = attr->base.immediate_value;
214 /* bad hack: the real stack stuff is behind the always-there spill
215 * space for the register window and stack */
216 if (is_stack_pointer_relative(node))
217 offset += SPARC_MIN_STACKSIZE;
219 assert(is_valid_immediate(offset));
220 be_emit_irprintf("%+ld", offset);
222 } else if (attr->base.immediate_value != 0
223 || attr->base.immediate_value_entity != NULL) {
225 sparc_emit_immediate(node);
229 void sparc_emit_float_load_store_mode(const ir_node *node)
231 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
232 ir_mode *mode = attr->load_store_mode;
233 int bits = get_mode_size_bits(mode);
235 assert(mode_is_float(mode));
239 case 64: be_emit_char('d'); return;
240 case 128: be_emit_char('q'); return;
242 panic("invalid flaot load/store mode %+F", mode);
246 * Emit load mode char
248 void sparc_emit_load_mode(const ir_node *node)
250 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
251 ir_mode *mode = attr->load_store_mode;
252 int bits = get_mode_size_bits(mode);
253 bool is_signed = mode_is_signed(mode);
256 be_emit_string(is_signed ? "sh" : "uh");
257 } else if (bits == 8) {
258 be_emit_string(is_signed ? "sb" : "ub");
259 } else if (bits == 64) {
267 * Emit store mode char
269 void sparc_emit_store_mode(const ir_node *node)
271 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
272 ir_mode *mode = attr->load_store_mode;
273 int bits = get_mode_size_bits(mode);
277 } else if (bits == 8) {
279 } else if (bits == 64) {
287 * emit integer signed/unsigned prefix char
289 void sparc_emit_mode_sign_prefix(const ir_node *node)
291 ir_mode *mode = get_irn_mode(node);
292 bool is_signed = mode_is_signed(mode);
293 be_emit_string(is_signed ? "s" : "u");
296 static void emit_fp_suffix(const ir_mode *mode)
298 unsigned bits = get_mode_size_bits(mode);
299 assert(mode_is_float(mode));
303 } else if (bits == 64) {
305 } else if (bits == 128) {
308 panic("invalid FP mode");
312 void sparc_emit_fp_conv_source(const ir_node *node)
314 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
315 emit_fp_suffix(attr->src_mode);
318 void sparc_emit_fp_conv_destination(const ir_node *node)
320 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
321 emit_fp_suffix(attr->dest_mode);
325 * emits the FP mode suffix char
327 void sparc_emit_fp_mode_suffix(const ir_node *node)
329 const sparc_fp_attr_t *attr = get_sparc_fp_attr_const(node);
330 emit_fp_suffix(attr->fp_mode);
333 static ir_node *get_jump_target(const ir_node *jump)
335 return get_irn_link(jump);
339 * Returns the target label for a control flow node.
341 static void sparc_emit_cfop_target(const ir_node *node)
343 ir_node *block = get_jump_target(node);
344 be_gas_emit_block_name(block);
347 static int get_sparc_Call_dest_addr_pos(const ir_node *node)
349 return get_irn_arity(node)-1;
352 static bool ba_is_fallthrough(const ir_node *node)
354 ir_node *block = get_nodes_block(node);
355 ir_node *next_block = get_irn_link(block);
356 return get_irn_link(node) == next_block;
359 static bool is_no_instruction(const ir_node *node)
361 /* copies are nops if src_reg == dest_reg */
362 if (be_is_Copy(node) || be_is_CopyKeep(node)) {
363 const arch_register_t *src_reg = get_in_reg(node, 0);
364 const arch_register_t *dest_reg = get_out_reg(node, 0);
366 if (src_reg == dest_reg)
369 if (be_is_IncSP(node) && be_get_IncSP_offset(node) == 0)
371 /* Ba is not emitted if it is a simple fallthrough */
372 if (is_sparc_Ba(node) && ba_is_fallthrough(node))
375 return be_is_Keep(node) || be_is_Barrier(node) || be_is_Start(node)
379 static bool has_delay_slot(const ir_node *node)
381 if (is_sparc_Ba(node) && ba_is_fallthrough(node))
384 return is_sparc_Bicc(node) || is_sparc_fbfcc(node) || is_sparc_Ba(node)
385 || is_sparc_SwitchJmp(node) || is_sparc_Call(node)
386 || is_sparc_SDiv(node) || is_sparc_UDiv(node)
387 || be_is_Return(node);
390 /** returns true if the emitter for this sparc node can produce more than one
391 * actual sparc instruction.
392 * Usually it is a bad sign if we have to add instructions here. We should
393 * rather try to get them lowered down. So we can actually put them into
394 * delay slots and make them more accessible to the scheduler.
396 static bool emits_multiple_instructions(const ir_node *node)
398 if (has_delay_slot(node))
401 return is_sparc_Mulh(node) || is_sparc_SDiv(node) || is_sparc_UDiv(node)
402 || be_is_MemPerm(node) || be_is_Perm(node);
406 * search for an instruction that can fill the delay slot of @p node
408 static const ir_node *pick_delay_slot_for(const ir_node *node)
410 const ir_node *check = node;
411 const ir_node *schedpoint = node;
413 /* currently we don't track which registers are still alive, so we can't
414 * pick any other instructions other than the one directly preceding */
415 static const unsigned PICK_DELAY_SLOT_MAX_DISTANCE = 1;
417 assert(has_delay_slot(node));
419 if (is_sparc_Call(node)) {
420 const sparc_attr_t *attr = get_sparc_attr_const(node);
421 ir_entity *entity = attr->immediate_value_entity;
422 if (entity != NULL) {
423 check = NULL; /* pick any instruction, dependencies on Call
426 /* we only need to check the value for the call destination */
427 check = get_irn_n(node, get_sparc_Call_dest_addr_pos(node));
430 /* the Call also destroys the value of %o7, but since this is currently
431 * marked as ignore register in the backend, it should never be used by
432 * the instruction in the delay slot. */
433 } else if (be_is_Return(node)) {
434 /* we only have to check the jump destination value */
435 int arity = get_irn_arity(node);
439 for (i = 0; i < arity; ++i) {
440 ir_node *in = get_irn_n(node, i);
441 const arch_register_t *reg = arch_get_irn_register(in);
442 if (reg == &sparc_gp_regs[REG_O7]) {
443 check = skip_Proj(in);
451 while (sched_has_prev(schedpoint)) {
452 schedpoint = sched_prev(schedpoint);
454 if (tries++ >= PICK_DELAY_SLOT_MAX_DISTANCE)
457 if (has_delay_slot(schedpoint))
460 /* skip things which don't really result in instructions */
461 if (is_no_instruction(schedpoint))
464 if (emits_multiple_instructions(schedpoint))
467 /* allowed for delayslot: any instruction which is not necessary to
468 * compute an input to the branch. */
470 && heights_reachable_in_block(heights, check, schedpoint))
473 /* found something */
481 * Emits code for stack space management
483 static void emit_be_IncSP(const ir_node *irn)
485 int offs = -be_get_IncSP_offset(irn);
490 /* SPARC stack grows downwards */
492 be_emit_cstring("\tsub ");
495 be_emit_cstring("\tadd ");
498 sparc_emit_source_register(irn, 0);
499 be_emit_irprintf(", %d", offs);
500 be_emit_cstring(", ");
501 sparc_emit_dest_register(irn, 0);
502 be_emit_finish_line_gas(irn);
506 * emits code for mulh
508 static void emit_sparc_Mulh(const ir_node *irn)
510 be_emit_cstring("\t");
511 sparc_emit_mode_sign_prefix(irn);
512 be_emit_cstring("mul ");
514 sparc_emit_source_register(irn, 0);
515 be_emit_cstring(", ");
516 sparc_emit_reg_or_imm(irn, 1);
517 be_emit_cstring(", ");
518 sparc_emit_dest_register(irn, 0);
519 be_emit_finish_line_gas(irn);
521 // our result is in the y register now
522 // we just copy it to the assigned target reg
523 be_emit_cstring("\tmov %y, ");
524 sparc_emit_dest_register(irn, 0);
525 be_emit_finish_line_gas(irn);
528 static void fill_delay_slot(void)
530 if (delay_slot_filler != NULL) {
531 sparc_emit_node(delay_slot_filler);
532 delay_slot_filler = NULL;
534 be_emit_cstring("\tnop\n");
535 be_emit_write_line();
539 static void emit_sparc_Div(const ir_node *node, bool is_signed)
541 /* can we get the delay count of the wr instruction somewhere? */
542 unsigned wry_delay_count = 3;
545 be_emit_cstring("\twr ");
546 sparc_emit_source_register(node, 0);
547 be_emit_cstring(", 0, %y");
548 be_emit_finish_line_gas(node);
550 for (i = 0; i < wry_delay_count; ++i) {
554 be_emit_irprintf("\t%s ", is_signed ? "sdiv" : "udiv");
555 sparc_emit_source_register(node, 1);
556 be_emit_cstring(", ");
557 sparc_emit_reg_or_imm(node, 2);
558 be_emit_cstring(", ");
559 sparc_emit_dest_register(node, 0);
560 be_emit_finish_line_gas(node);
563 static void emit_sparc_SDiv(const ir_node *node)
565 emit_sparc_Div(node, true);
568 static void emit_sparc_UDiv(const ir_node *node)
570 emit_sparc_Div(node, false);
574 * Emits code for Call node
576 static void emit_sparc_Call(const ir_node *node)
578 const sparc_attr_t *attr = get_sparc_attr_const(node);
579 ir_entity *entity = attr->immediate_value_entity;
581 be_emit_cstring("\tcall ");
582 if (entity != NULL) {
583 be_gas_emit_entity(entity);
584 if (attr->immediate_value != 0) {
585 be_emit_irprintf("%+d", attr->immediate_value);
587 be_emit_cstring(", 0");
589 int dest_addr = get_sparc_Call_dest_addr_pos(node);
590 sparc_emit_source_register(node, dest_addr);
592 be_emit_finish_line_gas(node);
598 * Emit code for Perm node
600 static void emit_be_Perm(const ir_node *irn)
602 be_emit_cstring("\txor ");
603 sparc_emit_source_register(irn, 1);
604 be_emit_cstring(", ");
605 sparc_emit_source_register(irn, 0);
606 be_emit_cstring(", ");
607 sparc_emit_source_register(irn, 0);
608 be_emit_finish_line_gas(NULL);
610 be_emit_cstring("\txor ");
611 sparc_emit_source_register(irn, 1);
612 be_emit_cstring(", ");
613 sparc_emit_source_register(irn, 0);
614 be_emit_cstring(", ");
615 sparc_emit_source_register(irn, 1);
616 be_emit_finish_line_gas(NULL);
618 be_emit_cstring("\txor ");
619 sparc_emit_source_register(irn, 1);
620 be_emit_cstring(", ");
621 sparc_emit_source_register(irn, 0);
622 be_emit_cstring(", ");
623 sparc_emit_source_register(irn, 0);
624 be_emit_finish_line_gas(irn);
627 static void emit_be_MemPerm(const ir_node *node)
632 ir_graph *irg = get_irn_irg(node);
633 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
635 /* this implementation only works with frame pointers currently */
636 assert(layout->sp_relative == false);
638 /* TODO: this implementation is slower than necessary.
639 The longterm goal is however to avoid the memperm node completely */
641 memperm_arity = be_get_MemPerm_entity_arity(node);
642 // we use our local registers - so this is limited to 8 inputs !
643 if (memperm_arity > 8)
644 panic("memperm with more than 8 inputs not supported yet");
646 be_emit_irprintf("\tsub %%sp, %d, %%sp", memperm_arity*4);
647 be_emit_finish_line_gas(node);
649 for (i = 0; i < memperm_arity; ++i) {
650 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
651 int offset = be_get_stack_entity_offset(layout, entity, 0);
654 be_emit_irprintf("\tst %%l%d, [%%sp%+d]", i, sp_change + SPARC_MIN_STACKSIZE);
655 be_emit_finish_line_gas(node);
657 /* load from entity */
658 be_emit_irprintf("\tld [%%fp%+d], %%l%d", offset, i);
659 be_emit_finish_line_gas(node);
663 for (i = memperm_arity-1; i >= 0; --i) {
664 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
665 int offset = be_get_stack_entity_offset(layout, entity, 0);
669 /* store to new entity */
670 be_emit_irprintf("\tst %%l%d, [%%fp%+d]", i, offset);
671 be_emit_finish_line_gas(node);
672 /* restore register */
673 be_emit_irprintf("\tld [%%sp%+d], %%l%d", sp_change + SPARC_MIN_STACKSIZE, i);
674 be_emit_finish_line_gas(node);
677 be_emit_irprintf("\tadd %%sp, %d, %%sp", memperm_arity*4);
678 be_emit_finish_line_gas(node);
680 assert(sp_change == 0);
683 static void emit_be_Return(const ir_node *node)
685 const char *destreg = "%o7";
687 /* hack: we don't explicitely model register changes because of the
688 * restore node. So we have to do it manually here */
689 if (delay_slot_filler != NULL &&
690 (is_sparc_Restore(delay_slot_filler)
691 || is_sparc_RestoreZero(delay_slot_filler))) {
694 be_emit_cstring("\tjmp ");
695 be_emit_string(destreg);
696 be_emit_cstring("+8");
697 be_emit_finish_line_gas(node);
701 static void emit_sparc_FrameAddr(const ir_node *node)
703 const sparc_attr_t *attr = get_sparc_attr_const(node);
705 // no need to fix offset as we are adressing via the framepointer
706 if (attr->immediate_value >= 0) {
707 be_emit_cstring("\tadd ");
708 sparc_emit_source_register(node, 0);
709 be_emit_cstring(", ");
710 be_emit_irprintf("%ld", attr->immediate_value);
712 be_emit_cstring("\tsub ");
713 sparc_emit_source_register(node, 0);
714 be_emit_cstring(", ");
715 be_emit_irprintf("%ld", -attr->immediate_value);
718 be_emit_cstring(", ");
719 sparc_emit_dest_register(node, 0);
720 be_emit_finish_line_gas(node);
723 static const char *get_icc_unsigned(pn_Cmp pnc)
726 case pn_Cmp_False: return "bn";
727 case pn_Cmp_Eq: return "be";
728 case pn_Cmp_Lt: return "blu";
729 case pn_Cmp_Le: return "bleu";
730 case pn_Cmp_Gt: return "bgu";
731 case pn_Cmp_Ge: return "bgeu";
732 case pn_Cmp_Lg: return "bne";
733 case pn_Cmp_Leg: return "ba";
734 default: panic("Cmp has unsupported pnc");
738 static const char *get_icc_signed(pn_Cmp pnc)
741 case pn_Cmp_False: return "bn";
742 case pn_Cmp_Eq: return "be";
743 case pn_Cmp_Lt: return "bl";
744 case pn_Cmp_Le: return "ble";
745 case pn_Cmp_Gt: return "bg";
746 case pn_Cmp_Ge: return "bge";
747 case pn_Cmp_Lg: return "bne";
748 case pn_Cmp_Leg: return "ba";
749 default: panic("Cmp has unsupported pnc");
753 static const char *get_fcc(pn_Cmp pnc)
756 case pn_Cmp_False: return "fbn";
757 case pn_Cmp_Eq: return "fbe";
758 case pn_Cmp_Lt: return "fbl";
759 case pn_Cmp_Le: return "fble";
760 case pn_Cmp_Gt: return "fbg";
761 case pn_Cmp_Ge: return "fbge";
762 case pn_Cmp_Lg: return "fblg";
763 case pn_Cmp_Leg: return "fbo";
764 case pn_Cmp_Uo: return "fbu";
765 case pn_Cmp_Ue: return "fbue";
766 case pn_Cmp_Ul: return "fbul";
767 case pn_Cmp_Ule: return "fbule";
768 case pn_Cmp_Ug: return "fbug";
769 case pn_Cmp_Uge: return "fbuge";
770 case pn_Cmp_Ne: return "fbne";
771 case pn_Cmp_True: return "fba";
775 panic("invalid pnc");
778 typedef const char* (*get_cc_func)(pn_Cmp pnc);
780 static void emit_sparc_branch(const ir_node *node, get_cc_func get_cc)
782 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
783 pn_Cmp pnc = attr->pnc;
784 const ir_node *proj_true = NULL;
785 const ir_node *proj_false = NULL;
786 const ir_edge_t *edge;
787 const ir_node *block;
788 const ir_node *next_block;
790 foreach_out_edge(node, edge) {
791 ir_node *proj = get_edge_src_irn(edge);
792 long nr = get_Proj_proj(proj);
793 if (nr == pn_Cond_true) {
800 /* for now, the code works for scheduled and non-schedules blocks */
801 block = get_nodes_block(node);
803 /* we have a block schedule */
804 next_block = get_irn_link(block);
806 if (get_irn_link(proj_true) == next_block) {
807 /* exchange both proj's so the second one can be omitted */
808 const ir_node *t = proj_true;
810 proj_true = proj_false;
812 if (is_sparc_fbfcc(node)) {
813 pnc = get_negated_pnc(pnc, mode_F);
815 pnc = get_negated_pnc(pnc, mode_Iu);
819 /* emit the true proj */
820 be_emit_cstring("\t");
821 be_emit_string(get_cc(pnc));
823 sparc_emit_cfop_target(proj_true);
824 be_emit_finish_line_gas(proj_true);
828 if (get_irn_link(proj_false) == next_block) {
829 be_emit_cstring("\t/* fallthrough to ");
830 sparc_emit_cfop_target(proj_false);
831 be_emit_cstring(" */");
832 be_emit_finish_line_gas(proj_false);
834 be_emit_cstring("\tba ");
835 sparc_emit_cfop_target(proj_false);
836 be_emit_finish_line_gas(proj_false);
841 static void emit_sparc_Bicc(const ir_node *node)
843 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
844 bool is_unsigned = attr->is_unsigned;
845 emit_sparc_branch(node, is_unsigned ? get_icc_unsigned : get_icc_signed);
848 static void emit_sparc_fbfcc(const ir_node *node)
850 emit_sparc_branch(node, get_fcc);
853 static void emit_sparc_Ba(const ir_node *node)
855 if (ba_is_fallthrough(node)) {
856 be_emit_cstring("\t/* fallthrough to ");
857 sparc_emit_cfop_target(node);
858 be_emit_cstring(" */");
860 be_emit_cstring("\tba ");
861 sparc_emit_cfop_target(node);
862 be_emit_finish_line_gas(node);
865 be_emit_finish_line_gas(node);
868 static void emit_jump_table(const ir_node *node)
870 const sparc_switch_jmp_attr_t *attr = get_sparc_switch_jmp_attr_const(node);
871 long switch_max = LONG_MIN;
872 long default_pn = attr->default_proj_num;
873 ir_entity *entity = attr->jump_table;
874 ir_node *default_block = NULL;
875 unsigned long length;
876 const ir_edge_t *edge;
880 /* go over all proj's and collect them */
881 foreach_out_edge(node, edge) {
882 ir_node *proj = get_edge_src_irn(edge);
883 long pn = get_Proj_proj(proj);
885 /* check for default proj */
886 if (pn == default_pn) {
887 assert(default_block == NULL); /* more than 1 default_pn? */
888 default_block = get_jump_target(proj);
890 switch_max = pn > switch_max ? pn : switch_max;
893 assert(switch_max > LONG_MIN);
895 length = (unsigned long) switch_max + 1;
896 /* the 16000 isn't a real limit of the architecture. But should protect us
897 * from seamingly endless compiler runs */
898 if (length > 16000) {
899 /* switch lowerer should have broken this monster to pieces... */
900 panic("too large switch encountered");
903 table = XMALLOCNZ(ir_node*, length);
904 foreach_out_edge(node, edge) {
905 ir_node *proj = get_edge_src_irn(edge);
906 long pn = get_Proj_proj(proj);
907 if (pn == default_pn)
910 table[pn] = get_jump_target(proj);
914 be_gas_emit_switch_section(GAS_SECTION_RODATA);
915 be_emit_cstring("\t.align 4\n");
916 be_gas_emit_entity(entity);
917 be_emit_cstring(":\n");
918 for (i = 0; i < length; ++i) {
919 ir_node *block = table[i];
921 block = default_block;
922 be_emit_cstring("\t.long ");
923 be_gas_emit_block_name(block);
925 be_emit_write_line();
927 be_gas_emit_switch_section(GAS_SECTION_TEXT);
932 static void emit_sparc_SwitchJmp(const ir_node *node)
934 be_emit_cstring("\tjmp ");
935 sparc_emit_source_register(node, 0);
936 be_emit_finish_line_gas(node);
939 emit_jump_table(node);
942 static void emit_fmov(const ir_node *node, const arch_register_t *src_reg,
943 const arch_register_t *dst_reg)
945 be_emit_cstring("\tfmovs %");
946 be_emit_string(arch_register_get_name(src_reg));
947 be_emit_cstring(", %");
948 be_emit_string(arch_register_get_name(dst_reg));
949 be_emit_finish_line_gas(node);
952 static const arch_register_t *get_next_fp_reg(const arch_register_t *reg)
954 unsigned index = reg->index;
955 assert(reg == &sparc_registers[index]);
957 assert(index - REG_F0 < N_sparc_fp_REGS);
958 return &sparc_registers[index];
961 static void emit_be_Copy(const ir_node *node)
963 ir_mode *mode = get_irn_mode(node);
964 const arch_register_t *src_reg = get_in_reg(node, 0);
965 const arch_register_t *dst_reg = get_out_reg(node, 0);
967 if (src_reg == dst_reg)
970 if (mode_is_float(mode)) {
971 unsigned bits = get_mode_size_bits(mode);
972 int n = bits > 32 ? bits > 64 ? 3 : 1 : 0;
974 emit_fmov(node, src_reg, dst_reg);
975 for (i = 0; i < n; ++i) {
976 src_reg = get_next_fp_reg(src_reg);
977 dst_reg = get_next_fp_reg(dst_reg);
978 emit_fmov(node, src_reg, dst_reg);
980 } else if (mode_is_data(mode)) {
981 be_emit_cstring("\tmov ");
982 sparc_emit_source_register(node, 0);
983 be_emit_cstring(", ");
984 sparc_emit_dest_register(node, 0);
985 be_emit_finish_line_gas(node);
987 panic("emit_be_Copy: invalid mode");
991 static void emit_nothing(const ir_node *irn)
996 typedef void (*emit_func) (const ir_node *);
998 static inline void set_emitter(ir_op *op, emit_func sparc_emit_node)
1000 op->ops.generic = (op_func)sparc_emit_node;
1004 * Enters the emitter functions for handled nodes into the generic
1005 * pointer of an opcode.
1007 static void sparc_register_emitters(void)
1009 /* first clear the generic function pointer for all ops */
1010 clear_irp_opcodes_generic_func();
1011 /* register all emitter functions defined in spec */
1012 sparc_register_spec_emitters();
1014 /* custom emitter */
1015 set_emitter(op_be_Copy, emit_be_Copy);
1016 set_emitter(op_be_CopyKeep, emit_be_Copy);
1017 set_emitter(op_be_IncSP, emit_be_IncSP);
1018 set_emitter(op_be_MemPerm, emit_be_MemPerm);
1019 set_emitter(op_be_Perm, emit_be_Perm);
1020 set_emitter(op_be_Return, emit_be_Return);
1021 set_emitter(op_sparc_Ba, emit_sparc_Ba);
1022 set_emitter(op_sparc_Bicc, emit_sparc_Bicc);
1023 set_emitter(op_sparc_Call, emit_sparc_Call);
1024 set_emitter(op_sparc_fbfcc, emit_sparc_fbfcc);
1025 set_emitter(op_sparc_FrameAddr, emit_sparc_FrameAddr);
1026 set_emitter(op_sparc_Mulh, emit_sparc_Mulh);
1027 set_emitter(op_sparc_SDiv, emit_sparc_SDiv);
1028 set_emitter(op_sparc_SwitchJmp, emit_sparc_SwitchJmp);
1029 set_emitter(op_sparc_UDiv, emit_sparc_UDiv);
1031 /* no need to emit anything for the following nodes */
1032 set_emitter(op_be_Barrier, emit_nothing);
1033 set_emitter(op_be_Keep, emit_nothing);
1034 set_emitter(op_be_Start, emit_nothing);
1035 set_emitter(op_Phi, emit_nothing);
1039 * Emits code for a node.
1041 static void sparc_emit_node(const ir_node *node)
1043 ir_op *op = get_irn_op(node);
1045 if (op->ops.generic) {
1046 emit_func func = (emit_func) op->ops.generic;
1047 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1050 panic("No emit handler for node %+F (graph %+F)\n", node,
1055 static ir_node *find_next_delay_slot(ir_node *from)
1057 ir_node *schedpoint = from;
1058 while (!has_delay_slot(schedpoint)) {
1059 if (!sched_has_next(schedpoint))
1061 schedpoint = sched_next(schedpoint);
1067 * Walks over the nodes in a block connected by scheduling edges
1068 * and emits code for each node.
1070 static void sparc_emit_block(ir_node *block)
1073 ir_node *next_delay_slot;
1075 assert(is_Block(block));
1077 be_gas_emit_block_name(block);
1078 be_emit_cstring(":\n");
1079 be_emit_write_line();
1081 next_delay_slot = find_next_delay_slot(sched_first(block));
1082 if (next_delay_slot != NULL)
1083 delay_slot_filler = pick_delay_slot_for(next_delay_slot);
1085 sched_foreach(block, node) {
1086 if (node == delay_slot_filler) {
1090 sparc_emit_node(node);
1092 if (node == next_delay_slot) {
1093 assert(delay_slot_filler == NULL);
1094 next_delay_slot = find_next_delay_slot(sched_next(node));
1095 if (next_delay_slot != NULL)
1096 delay_slot_filler = pick_delay_slot_for(next_delay_slot);
1102 * Emits code for function start.
1104 static void sparc_emit_func_prolog(ir_graph *irg)
1106 ir_entity *ent = get_irg_entity(irg);
1107 be_gas_emit_function_prolog(ent, 4);
1108 be_emit_write_line();
1112 * Emits code for function end
1114 static void sparc_emit_func_epilog(ir_graph *irg)
1116 ir_entity *ent = get_irg_entity(irg);
1117 const char *irg_name = get_entity_ld_name(ent);
1118 be_emit_write_line();
1119 be_emit_irprintf("\t.size %s, .-%s\n", irg_name, irg_name);
1120 be_emit_cstring("# -- End ");
1121 be_emit_string(irg_name);
1122 be_emit_cstring("\n");
1123 be_emit_write_line();
1126 static void sparc_gen_labels(ir_node *block, void *env)
1129 int n = get_Block_n_cfgpreds(block);
1132 for (n--; n >= 0; n--) {
1133 pred = get_Block_cfgpred(block, n);
1134 set_irn_link(pred, block); // link the pred of a block (which is a jmp)
1138 void sparc_emit_routine(ir_graph *irg)
1140 ir_entity *entity = get_irg_entity(irg);
1141 ir_node **block_schedule;
1145 be_gas_elf_type_char = '#';
1146 be_gas_object_file_format = OBJECT_FILE_FORMAT_ELF_SPARC;
1148 heights = heights_new(irg);
1150 /* register all emitter functions */
1151 sparc_register_emitters();
1152 be_dbg_method_begin(entity);
1154 /* create the block schedule. For now, we don't need it earlier. */
1155 block_schedule = be_create_block_schedule(irg);
1157 sparc_emit_func_prolog(irg);
1158 irg_block_walk_graph(irg, sparc_gen_labels, NULL, NULL);
1160 /* inject block scheduling links & emit code of each block */
1161 n = ARR_LEN(block_schedule);
1162 for (i = 0; i < n; ++i) {
1163 ir_node *block = block_schedule[i];
1164 ir_node *next_block = i+1 < n ? block_schedule[i+1] : NULL;
1165 set_irn_link(block, next_block);
1168 for (i = 0; i < n; ++i) {
1169 ir_node *block = block_schedule[i];
1170 if (block == get_irg_end_block(irg))
1172 sparc_emit_block(block);
1175 /* emit function epilog */
1176 sparc_emit_func_epilog(irg);
1178 heights_free(heights);
1181 void sparc_init_emitter(void)
1183 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.emit");