2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
23 * @author Hannes Rapp, Matthias Braun
30 #include "bitfiddle.h"
42 #include "raw_bitset.h"
46 #include "../besched.h"
47 #include "../beblocksched.h"
49 #include "../begnuas.h"
50 #include "../be_dbgout.h"
51 #include "../benode.h"
52 #include "../bestack.h"
54 #include "sparc_emitter.h"
55 #include "gen_sparc_emitter.h"
56 #include "sparc_nodes_attr.h"
57 #include "sparc_new_nodes.h"
58 #include "gen_sparc_regalloc_if.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static ir_heights_t *heights;
63 static const ir_node *delay_slot_filler; /**< this node has been choosen to fill
64 the next delay slot */
66 static void sparc_emit_node(const ir_node *node);
68 void sparc_emit_immediate(const ir_node *node)
70 const sparc_attr_t *attr = get_sparc_attr_const(node);
71 ir_entity *entity = attr->immediate_value_entity;
74 int32_t value = attr->immediate_value;
75 assert(sparc_is_value_imm_encodeable(value));
76 be_emit_irprintf("%d", value);
78 if (get_entity_owner(entity) == get_tls_type()) {
79 be_emit_cstring("%tle_lox10(");
81 be_emit_cstring("%lo(");
83 be_gas_emit_entity(entity);
84 if (attr->immediate_value != 0) {
85 be_emit_irprintf("%+d", attr->immediate_value);
91 void sparc_emit_high_immediate(const ir_node *node)
93 const sparc_attr_t *attr = get_sparc_attr_const(node);
94 ir_entity *entity = attr->immediate_value_entity;
97 uint32_t value = (uint32_t) attr->immediate_value;
98 be_emit_irprintf("%%hi(0x%X)", value);
100 if (get_entity_owner(entity) == get_tls_type()) {
101 be_emit_cstring("%tle_hix22(");
103 be_emit_cstring("%hi(");
105 be_gas_emit_entity(entity);
106 if (attr->immediate_value != 0) {
107 be_emit_irprintf("%+d", attr->immediate_value);
113 void sparc_emit_source_register(const ir_node *node, int pos)
115 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
117 be_emit_string(arch_register_get_name(reg));
120 void sparc_emit_dest_register(const ir_node *node, int pos)
122 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
124 be_emit_string(arch_register_get_name(reg));
128 * Emits either a imm or register depending on arity of node
130 * @param register no (-1 if no register)
132 void sparc_emit_reg_or_imm(const ir_node *node, int pos)
134 if (arch_get_irn_flags(node) & ((arch_irn_flags_t)sparc_arch_irn_flag_immediate_form)) {
135 // we have a imm input
136 sparc_emit_immediate(node);
139 sparc_emit_source_register(node, pos);
146 void sparc_emit_offset(const ir_node *node, int offset_node_pos)
148 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
150 if (attr->is_reg_reg) {
151 assert(!attr->is_frame_entity);
152 assert(attr->base.immediate_value == 0);
153 assert(attr->base.immediate_value_entity == NULL);
155 sparc_emit_source_register(node, offset_node_pos);
156 } else if (attr->is_frame_entity) {
157 int32_t offset = attr->base.immediate_value;
159 assert(sparc_is_value_imm_encodeable(offset));
160 be_emit_irprintf("%+ld", offset);
162 } else if (attr->base.immediate_value != 0
163 || attr->base.immediate_value_entity != NULL) {
165 sparc_emit_immediate(node);
169 void sparc_emit_float_load_store_mode(const ir_node *node)
171 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
172 ir_mode *mode = attr->load_store_mode;
173 int bits = get_mode_size_bits(mode);
175 assert(mode_is_float(mode));
179 case 64: be_emit_char('d'); return;
180 case 128: be_emit_char('q'); return;
182 panic("invalid flaot load/store mode %+F", mode);
186 * Emit load mode char
188 void sparc_emit_load_mode(const ir_node *node)
190 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
191 ir_mode *mode = attr->load_store_mode;
192 int bits = get_mode_size_bits(mode);
193 bool is_signed = mode_is_signed(mode);
196 be_emit_string(is_signed ? "sh" : "uh");
197 } else if (bits == 8) {
198 be_emit_string(is_signed ? "sb" : "ub");
199 } else if (bits == 64) {
207 * Emit store mode char
209 void sparc_emit_store_mode(const ir_node *node)
211 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
212 ir_mode *mode = attr->load_store_mode;
213 int bits = get_mode_size_bits(mode);
217 } else if (bits == 8) {
219 } else if (bits == 64) {
226 static void emit_fp_suffix(const ir_mode *mode)
228 unsigned bits = get_mode_size_bits(mode);
229 assert(mode_is_float(mode));
233 } else if (bits == 64) {
235 } else if (bits == 128) {
238 panic("invalid FP mode");
242 void sparc_emit_fp_conv_source(const ir_node *node)
244 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
245 emit_fp_suffix(attr->src_mode);
248 void sparc_emit_fp_conv_destination(const ir_node *node)
250 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
251 emit_fp_suffix(attr->dest_mode);
255 * emits the FP mode suffix char
257 void sparc_emit_fp_mode_suffix(const ir_node *node)
259 const sparc_fp_attr_t *attr = get_sparc_fp_attr_const(node);
260 emit_fp_suffix(attr->fp_mode);
263 static ir_node *get_jump_target(const ir_node *jump)
265 return (ir_node*)get_irn_link(jump);
269 * Returns the target label for a control flow node.
271 static void sparc_emit_cfop_target(const ir_node *node)
273 ir_node *block = get_jump_target(node);
274 be_gas_emit_block_name(block);
277 static int get_sparc_Call_dest_addr_pos(const ir_node *node)
279 return get_irn_arity(node)-1;
282 static bool ba_is_fallthrough(const ir_node *node)
284 ir_node *block = get_nodes_block(node);
285 ir_node *next_block = (ir_node*)get_irn_link(block);
286 return get_irn_link(node) == next_block;
289 static bool is_no_instruction(const ir_node *node)
291 /* copies are nops if src_reg == dest_reg */
292 if (be_is_Copy(node) || be_is_CopyKeep(node)) {
293 const arch_register_t *src_reg = arch_get_irn_register_in(node, 0);
294 const arch_register_t *dest_reg = arch_get_irn_register_out(node, 0);
296 if (src_reg == dest_reg)
299 if (be_is_IncSP(node) && be_get_IncSP_offset(node) == 0)
301 /* Ba is not emitted if it is a simple fallthrough */
302 if (is_sparc_Ba(node) && ba_is_fallthrough(node))
305 return be_is_Keep(node) || be_is_Start(node) || is_Phi(node);
308 static bool has_delay_slot(const ir_node *node)
310 if (is_sparc_Ba(node) && ba_is_fallthrough(node))
313 return is_sparc_Bicc(node) || is_sparc_fbfcc(node) || is_sparc_Ba(node)
314 || is_sparc_SwitchJmp(node) || is_sparc_Call(node)
315 || is_sparc_SDiv(node) || is_sparc_UDiv(node)
316 || is_sparc_Return(node);
319 /** returns true if the emitter for this sparc node can produce more than one
320 * actual sparc instruction.
321 * Usually it is a bad sign if we have to add instructions here. We should
322 * rather try to get them lowered down. So we can actually put them into
323 * delay slots and make them more accessible to the scheduler.
325 static bool emits_multiple_instructions(const ir_node *node)
327 if (has_delay_slot(node))
330 if (is_sparc_Call(node)) {
331 return arch_get_irn_flags(node) & sparc_arch_irn_flag_aggregate_return;
334 return is_sparc_SMulh(node) || is_sparc_UMulh(node)
335 || is_sparc_SDiv(node) || is_sparc_UDiv(node)
336 || be_is_MemPerm(node) || be_is_Perm(node);
340 * search for an instruction that can fill the delay slot of @p node
342 static const ir_node *pick_delay_slot_for(const ir_node *node)
344 const ir_node *check = node;
345 const ir_node *schedpoint = node;
347 /* currently we don't track which registers are still alive, so we can't
348 * pick any other instructions other than the one directly preceding */
349 static const unsigned PICK_DELAY_SLOT_MAX_DISTANCE = 1;
351 assert(has_delay_slot(node));
353 if (is_sparc_Call(node)) {
354 const sparc_attr_t *attr = get_sparc_attr_const(node);
355 ir_entity *entity = attr->immediate_value_entity;
356 if (entity != NULL) {
357 check = NULL; /* pick any instruction, dependencies on Call
360 /* we only need to check the value for the call destination */
361 check = get_irn_n(node, get_sparc_Call_dest_addr_pos(node));
364 /* the Call also destroys the value of %o7, but since this is currently
365 * marked as ignore register in the backend, it should never be used by
366 * the instruction in the delay slot. */
367 } else if (is_sparc_Return(node)) {
368 /* we only have to check the jump destination value */
369 int arity = get_irn_arity(node);
373 for (i = 0; i < arity; ++i) {
374 ir_node *in = get_irn_n(node, i);
375 const arch_register_t *reg = arch_get_irn_register(in);
376 if (reg == &sparc_registers[REG_O7]) {
377 check = skip_Proj(in);
385 while (sched_has_prev(schedpoint)) {
386 schedpoint = sched_prev(schedpoint);
388 if (has_delay_slot(schedpoint))
391 /* skip things which don't really result in instructions */
392 if (is_no_instruction(schedpoint))
395 if (tries++ >= PICK_DELAY_SLOT_MAX_DISTANCE)
398 if (emits_multiple_instructions(schedpoint))
401 /* if check and schedpoint are not in the same block, give up. */
403 && get_nodes_block(check) != get_nodes_block(schedpoint))
406 /* allowed for delayslot: any instruction which is not necessary to
407 * compute an input to the branch. */
409 && heights_reachable_in_block(heights, check, schedpoint))
412 /* found something */
420 * Emits code for stack space management
422 static void emit_be_IncSP(const ir_node *irn)
424 int offset = be_get_IncSP_offset(irn);
429 /* SPARC stack grows downwards */
431 be_emit_cstring("\tsub ");
434 be_emit_cstring("\tadd ");
437 sparc_emit_source_register(irn, 0);
438 be_emit_irprintf(", %d", -offset);
439 be_emit_cstring(", ");
440 sparc_emit_dest_register(irn, 0);
441 be_emit_finish_line_gas(irn);
445 * emits code for mulh
447 static void emit_sparc_Mulh(const ir_node *irn)
449 be_emit_cstring("\t");
450 if (is_sparc_UMulh(irn)) {
453 assert(is_sparc_SMulh(irn));
456 be_emit_cstring("mul ");
458 sparc_emit_source_register(irn, 0);
459 be_emit_cstring(", ");
460 sparc_emit_reg_or_imm(irn, 1);
461 be_emit_cstring(", ");
462 sparc_emit_dest_register(irn, 0);
463 be_emit_finish_line_gas(irn);
465 // our result is in the y register now
466 // we just copy it to the assigned target reg
467 be_emit_cstring("\tmov %y, ");
468 sparc_emit_dest_register(irn, 0);
469 be_emit_finish_line_gas(irn);
472 static void fill_delay_slot(void)
474 if (delay_slot_filler != NULL) {
475 sparc_emit_node(delay_slot_filler);
476 delay_slot_filler = NULL;
478 be_emit_cstring("\tnop\n");
479 be_emit_write_line();
483 static void emit_sparc_Div(const ir_node *node, bool is_signed)
485 /* can we get the delay count of the wr instruction somewhere? */
486 unsigned wry_delay_count = 3;
489 be_emit_cstring("\twr ");
490 sparc_emit_source_register(node, 0);
491 be_emit_cstring(", 0, %y");
492 be_emit_finish_line_gas(node);
494 for (i = 0; i < wry_delay_count; ++i) {
498 be_emit_irprintf("\t%s ", is_signed ? "sdiv" : "udiv");
499 sparc_emit_source_register(node, 1);
500 be_emit_cstring(", ");
501 sparc_emit_reg_or_imm(node, 2);
502 be_emit_cstring(", ");
503 sparc_emit_dest_register(node, 0);
504 be_emit_finish_line_gas(node);
507 static void emit_sparc_SDiv(const ir_node *node)
509 emit_sparc_Div(node, true);
512 static void emit_sparc_UDiv(const ir_node *node)
514 emit_sparc_Div(node, false);
518 * Emits code for Call node
520 static void emit_sparc_Call(const ir_node *node)
522 const sparc_attr_t *attr = get_sparc_attr_const(node);
523 ir_entity *entity = attr->immediate_value_entity;
525 be_emit_cstring("\tcall ");
526 if (entity != NULL) {
527 be_gas_emit_entity(entity);
528 if (attr->immediate_value != 0) {
529 be_emit_irprintf("%+d", attr->immediate_value);
531 be_emit_cstring(", 0");
533 int dest_addr = get_sparc_Call_dest_addr_pos(node);
534 sparc_emit_source_register(node, dest_addr);
536 be_emit_finish_line_gas(node);
540 if (arch_get_irn_flags(node) & sparc_arch_irn_flag_aggregate_return) {
541 be_emit_cstring("\tunimp 8\n");
542 be_emit_write_line();
547 * Emit code for Perm node
549 static void emit_be_Perm(const ir_node *irn)
551 be_emit_cstring("\txor ");
552 sparc_emit_source_register(irn, 1);
553 be_emit_cstring(", ");
554 sparc_emit_source_register(irn, 0);
555 be_emit_cstring(", ");
556 sparc_emit_source_register(irn, 0);
557 be_emit_finish_line_gas(NULL);
559 be_emit_cstring("\txor ");
560 sparc_emit_source_register(irn, 1);
561 be_emit_cstring(", ");
562 sparc_emit_source_register(irn, 0);
563 be_emit_cstring(", ");
564 sparc_emit_source_register(irn, 1);
565 be_emit_finish_line_gas(NULL);
567 be_emit_cstring("\txor ");
568 sparc_emit_source_register(irn, 1);
569 be_emit_cstring(", ");
570 sparc_emit_source_register(irn, 0);
571 be_emit_cstring(", ");
572 sparc_emit_source_register(irn, 0);
573 be_emit_finish_line_gas(irn);
576 /* The stack pointer must always be SPARC_STACK_ALIGNMENT bytes aligned, so get
577 * the next bigger integer that's evenly divisible by it. */
578 static unsigned get_aligned_sp_change(unsigned const memperm_arity)
580 const unsigned bytes = memperm_arity * SPARC_REGISTER_SIZE;
581 return round_up2(bytes, SPARC_STACK_ALIGNMENT);
584 static void emit_be_MemPerm(const ir_node *node)
588 unsigned aligned_sp_change;
590 ir_graph *irg = get_irn_irg(node);
591 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
593 /* this implementation only works with frame pointers currently */
594 assert(layout->sp_relative == false);
596 /* TODO: this implementation is slower than necessary.
597 The longterm goal is however to avoid the memperm node completely */
599 memperm_arity = be_get_MemPerm_entity_arity(node);
600 // we use our local registers - so this is limited to 8 inputs !
601 if (memperm_arity > 8)
602 panic("memperm with more than 8 inputs not supported yet");
604 aligned_sp_change = get_aligned_sp_change(memperm_arity);
605 be_emit_irprintf("\tsub %%sp, %u, %%sp", aligned_sp_change);
606 be_emit_finish_line_gas(node);
608 for (i = 0; i < memperm_arity; ++i) {
609 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
610 int offset = be_get_stack_entity_offset(layout, entity, 0);
613 be_emit_irprintf("\tst %%l%d, [%%sp%+d]", i, sp_change + SPARC_MIN_STACKSIZE);
614 be_emit_finish_line_gas(node);
616 /* load from entity */
617 be_emit_irprintf("\tld [%%fp%+d], %%l%d", offset, i);
618 be_emit_finish_line_gas(node);
619 sp_change += SPARC_REGISTER_SIZE;
622 for (i = memperm_arity-1; i >= 0; --i) {
623 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
624 int offset = be_get_stack_entity_offset(layout, entity, 0);
626 sp_change -= SPARC_REGISTER_SIZE;
628 /* store to new entity */
629 be_emit_irprintf("\tst %%l%d, [%%fp%+d]", i, offset);
630 be_emit_finish_line_gas(node);
631 /* restore register */
632 be_emit_irprintf("\tld [%%sp%+d], %%l%d", sp_change + SPARC_MIN_STACKSIZE, i);
633 be_emit_finish_line_gas(node);
636 be_emit_irprintf("\tadd %%sp, %u, %%sp", aligned_sp_change);
637 be_emit_finish_line_gas(node);
639 assert(sp_change == 0);
642 static void emit_sparc_Return(const ir_node *node)
644 ir_graph *irg = get_irn_irg(node);
645 ir_entity *entity = get_irg_entity(irg);
646 ir_type *type = get_entity_type(entity);
648 const char *destreg = "%o7";
650 /* hack: we don't explicitely model register changes because of the
651 * restore node. So we have to do it manually here */
652 if (delay_slot_filler != NULL &&
653 (is_sparc_Restore(delay_slot_filler)
654 || is_sparc_RestoreZero(delay_slot_filler))) {
657 be_emit_cstring("\tjmp ");
658 be_emit_string(destreg);
659 if (get_method_calling_convention(type) & cc_compound_ret) {
660 be_emit_cstring("+12");
662 be_emit_cstring("+8");
664 be_emit_finish_line_gas(node);
668 static void emit_sparc_FrameAddr(const ir_node *node)
670 const sparc_attr_t *attr = get_sparc_attr_const(node);
671 int32_t offset = attr->immediate_value;
674 be_emit_cstring("\tadd ");
675 sparc_emit_source_register(node, 0);
676 be_emit_cstring(", ");
677 assert(sparc_is_value_imm_encodeable(offset));
678 be_emit_irprintf("%ld", offset);
680 be_emit_cstring("\tsub ");
681 sparc_emit_source_register(node, 0);
682 be_emit_cstring(", ");
683 assert(sparc_is_value_imm_encodeable(-offset));
684 be_emit_irprintf("%ld", -offset);
687 be_emit_cstring(", ");
688 sparc_emit_dest_register(node, 0);
689 be_emit_finish_line_gas(node);
692 static const char *get_icc_unsigned(ir_relation relation)
694 switch (relation & (ir_relation_less_equal_greater)) {
695 case ir_relation_false: return "bn";
696 case ir_relation_equal: return "be";
697 case ir_relation_less: return "blu";
698 case ir_relation_less_equal: return "bleu";
699 case ir_relation_greater: return "bgu";
700 case ir_relation_greater_equal: return "bgeu";
701 case ir_relation_less_greater: return "bne";
702 case ir_relation_less_equal_greater: return "ba";
703 default: panic("Cmp has unsupported relation");
707 static const char *get_icc_signed(ir_relation relation)
709 switch (relation & (ir_relation_less_equal_greater)) {
710 case ir_relation_false: return "bn";
711 case ir_relation_equal: return "be";
712 case ir_relation_less: return "bl";
713 case ir_relation_less_equal: return "ble";
714 case ir_relation_greater: return "bg";
715 case ir_relation_greater_equal: return "bge";
716 case ir_relation_less_greater: return "bne";
717 case ir_relation_less_equal_greater: return "ba";
718 default: panic("Cmp has unsupported relation");
722 static const char *get_fcc(ir_relation relation)
725 case ir_relation_false: return "fbn";
726 case ir_relation_equal: return "fbe";
727 case ir_relation_less: return "fbl";
728 case ir_relation_less_equal: return "fble";
729 case ir_relation_greater: return "fbg";
730 case ir_relation_greater_equal: return "fbge";
731 case ir_relation_less_greater: return "fblg";
732 case ir_relation_less_equal_greater: return "fbo";
733 case ir_relation_unordered: return "fbu";
734 case ir_relation_unordered_equal: return "fbue";
735 case ir_relation_unordered_less: return "fbul";
736 case ir_relation_unordered_less_equal: return "fbule";
737 case ir_relation_unordered_greater: return "fbug";
738 case ir_relation_unordered_greater_equal: return "fbuge";
739 case ir_relation_unordered_less_greater: return "fbne";
740 case ir_relation_true: return "fba";
742 panic("invalid relation");
745 typedef const char* (*get_cc_func)(ir_relation relation);
747 static void emit_sparc_branch(const ir_node *node, get_cc_func get_cc)
749 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
750 ir_relation relation = attr->relation;
751 const ir_node *proj_true = NULL;
752 const ir_node *proj_false = NULL;
753 const ir_edge_t *edge;
754 const ir_node *block;
755 const ir_node *next_block;
757 foreach_out_edge(node, edge) {
758 ir_node *proj = get_edge_src_irn(edge);
759 long nr = get_Proj_proj(proj);
760 if (nr == pn_Cond_true) {
767 /* for now, the code works for scheduled and non-schedules blocks */
768 block = get_nodes_block(node);
770 /* we have a block schedule */
771 next_block = (ir_node*)get_irn_link(block);
773 if (get_irn_link(proj_true) == next_block) {
774 /* exchange both proj's so the second one can be omitted */
775 const ir_node *t = proj_true;
777 proj_true = proj_false;
779 relation = get_negated_relation(relation);
782 /* emit the true proj */
783 be_emit_cstring("\t");
784 be_emit_string(get_cc(relation));
786 sparc_emit_cfop_target(proj_true);
787 be_emit_finish_line_gas(proj_true);
791 if (get_irn_link(proj_false) == next_block) {
792 be_emit_cstring("\t/* fallthrough to ");
793 sparc_emit_cfop_target(proj_false);
794 be_emit_cstring(" */");
795 be_emit_finish_line_gas(proj_false);
797 be_emit_cstring("\tba ");
798 sparc_emit_cfop_target(proj_false);
799 be_emit_finish_line_gas(proj_false);
804 static void emit_sparc_Bicc(const ir_node *node)
806 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
807 bool is_unsigned = attr->is_unsigned;
808 emit_sparc_branch(node, is_unsigned ? get_icc_unsigned : get_icc_signed);
811 static void emit_sparc_fbfcc(const ir_node *node)
813 /* if the flags producing node was immediately in front of us, emit
815 ir_node *flags = get_irn_n(node, n_sparc_fbfcc_flags);
816 ir_node *prev = sched_prev(node);
817 if (is_Block(prev)) {
818 /* TODO: when the flags come from another block, then we have to do
819 * more complicated tests to see wether the flag producing node is
820 * potentially in front of us (could happen for fallthroughs) */
821 panic("TODO: fbfcc flags come from other block");
823 if (skip_Proj(flags) == prev) {
824 be_emit_cstring("\tnop\n");
826 emit_sparc_branch(node, get_fcc);
829 static void emit_sparc_Ba(const ir_node *node)
831 if (ba_is_fallthrough(node)) {
832 be_emit_cstring("\t/* fallthrough to ");
833 sparc_emit_cfop_target(node);
834 be_emit_cstring(" */");
836 be_emit_cstring("\tba ");
837 sparc_emit_cfop_target(node);
838 be_emit_finish_line_gas(node);
841 be_emit_finish_line_gas(node);
844 static void emit_sparc_SwitchJmp(const ir_node *node)
846 const sparc_switch_jmp_attr_t *attr = get_sparc_switch_jmp_attr_const(node);
848 be_emit_cstring("\tjmp ");
849 sparc_emit_source_register(node, 0);
850 be_emit_finish_line_gas(node);
853 emit_jump_table(node, attr->default_proj_num, attr->jump_table,
857 static void emit_fmov(const ir_node *node, const arch_register_t *src_reg,
858 const arch_register_t *dst_reg)
860 be_emit_cstring("\tfmovs %");
861 be_emit_string(arch_register_get_name(src_reg));
862 be_emit_cstring(", %");
863 be_emit_string(arch_register_get_name(dst_reg));
864 be_emit_finish_line_gas(node);
867 static const arch_register_t *get_next_fp_reg(const arch_register_t *reg)
869 unsigned idx = reg->global_index;
870 assert(reg == &sparc_registers[idx]);
872 assert(idx - REG_F0 < N_sparc_fp_REGS);
873 return &sparc_registers[idx];
876 static void emit_be_Copy(const ir_node *node)
878 ir_mode *mode = get_irn_mode(node);
879 const arch_register_t *src_reg = arch_get_irn_register_in(node, 0);
880 const arch_register_t *dst_reg = arch_get_irn_register_out(node, 0);
882 if (src_reg == dst_reg)
885 if (mode_is_float(mode)) {
886 unsigned bits = get_mode_size_bits(mode);
887 int n = bits > 32 ? bits > 64 ? 3 : 1 : 0;
889 emit_fmov(node, src_reg, dst_reg);
890 for (i = 0; i < n; ++i) {
891 src_reg = get_next_fp_reg(src_reg);
892 dst_reg = get_next_fp_reg(dst_reg);
893 emit_fmov(node, src_reg, dst_reg);
895 } else if (mode_is_data(mode)) {
896 be_emit_cstring("\tmov ");
897 sparc_emit_source_register(node, 0);
898 be_emit_cstring(", ");
899 sparc_emit_dest_register(node, 0);
900 be_emit_finish_line_gas(node);
902 panic("emit_be_Copy: invalid mode");
906 static void emit_nothing(const ir_node *irn)
911 typedef void (*emit_func) (const ir_node *);
913 static inline void set_emitter(ir_op *op, emit_func sparc_emit_node)
915 op->ops.generic = (op_func)sparc_emit_node;
919 * Enters the emitter functions for handled nodes into the generic
920 * pointer of an opcode.
922 static void sparc_register_emitters(void)
924 /* first clear the generic function pointer for all ops */
925 clear_irp_opcodes_generic_func();
926 /* register all emitter functions defined in spec */
927 sparc_register_spec_emitters();
930 set_emitter(op_be_Copy, emit_be_Copy);
931 set_emitter(op_be_CopyKeep, emit_be_Copy);
932 set_emitter(op_be_IncSP, emit_be_IncSP);
933 set_emitter(op_be_MemPerm, emit_be_MemPerm);
934 set_emitter(op_be_Perm, emit_be_Perm);
935 set_emitter(op_sparc_Ba, emit_sparc_Ba);
936 set_emitter(op_sparc_Bicc, emit_sparc_Bicc);
937 set_emitter(op_sparc_Call, emit_sparc_Call);
938 set_emitter(op_sparc_fbfcc, emit_sparc_fbfcc);
939 set_emitter(op_sparc_FrameAddr, emit_sparc_FrameAddr);
940 set_emitter(op_sparc_SMulh, emit_sparc_Mulh);
941 set_emitter(op_sparc_UMulh, emit_sparc_Mulh);
942 set_emitter(op_sparc_Return, emit_sparc_Return);
943 set_emitter(op_sparc_SDiv, emit_sparc_SDiv);
944 set_emitter(op_sparc_SwitchJmp, emit_sparc_SwitchJmp);
945 set_emitter(op_sparc_UDiv, emit_sparc_UDiv);
947 /* no need to emit anything for the following nodes */
948 set_emitter(op_be_Keep, emit_nothing);
949 set_emitter(op_sparc_Start, emit_nothing);
950 set_emitter(op_Phi, emit_nothing);
954 * Emits code for a node.
956 static void sparc_emit_node(const ir_node *node)
958 ir_op *op = get_irn_op(node);
960 if (op->ops.generic) {
961 emit_func func = (emit_func) op->ops.generic;
962 be_dbg_set_dbg_info(get_irn_dbg_info(node));
965 panic("No emit handler for node %+F (graph %+F)\n", node,
970 static ir_node *find_next_delay_slot(ir_node *from)
972 ir_node *schedpoint = from;
973 while (!has_delay_slot(schedpoint)) {
974 if (!sched_has_next(schedpoint))
976 schedpoint = sched_next(schedpoint);
982 * Walks over the nodes in a block connected by scheduling edges
983 * and emits code for each node.
985 static void sparc_emit_block(ir_node *block)
988 ir_node *next_delay_slot;
990 assert(is_Block(block));
992 be_gas_emit_block_name(block);
993 be_emit_cstring(":\n");
994 be_emit_write_line();
996 next_delay_slot = find_next_delay_slot(sched_first(block));
997 if (next_delay_slot != NULL)
998 delay_slot_filler = pick_delay_slot_for(next_delay_slot);
1000 sched_foreach(block, node) {
1001 if (node == delay_slot_filler) {
1005 sparc_emit_node(node);
1007 if (node == next_delay_slot) {
1008 assert(delay_slot_filler == NULL);
1009 next_delay_slot = find_next_delay_slot(sched_next(node));
1010 if (next_delay_slot != NULL)
1011 delay_slot_filler = pick_delay_slot_for(next_delay_slot);
1017 * Emits code for function start.
1019 static void sparc_emit_func_prolog(ir_graph *irg)
1021 ir_entity *ent = get_irg_entity(irg);
1022 be_gas_emit_function_prolog(ent, 4);
1023 be_emit_write_line();
1027 * Emits code for function end
1029 static void sparc_emit_func_epilog(ir_graph *irg)
1031 ir_entity *ent = get_irg_entity(irg);
1032 const char *irg_name = get_entity_ld_name(ent);
1033 be_emit_write_line();
1034 be_emit_irprintf("\t.size %s, .-%s\n", irg_name, irg_name);
1035 be_emit_cstring("# -- End ");
1036 be_emit_string(irg_name);
1037 be_emit_cstring("\n");
1038 be_emit_write_line();
1041 static void sparc_gen_labels(ir_node *block, void *env)
1044 int n = get_Block_n_cfgpreds(block);
1047 for (n--; n >= 0; n--) {
1048 pred = get_Block_cfgpred(block, n);
1049 set_irn_link(pred, block); // link the pred of a block (which is a jmp)
1053 void sparc_emit_routine(ir_graph *irg)
1055 ir_entity *entity = get_irg_entity(irg);
1056 ir_node **block_schedule;
1060 heights = heights_new(irg);
1062 /* register all emitter functions */
1063 sparc_register_emitters();
1064 be_dbg_method_begin(entity);
1066 /* create the block schedule. For now, we don't need it earlier. */
1067 block_schedule = be_create_block_schedule(irg);
1069 sparc_emit_func_prolog(irg);
1070 irg_block_walk_graph(irg, sparc_gen_labels, NULL, NULL);
1072 /* inject block scheduling links & emit code of each block */
1073 n = ARR_LEN(block_schedule);
1074 for (i = 0; i < n; ++i) {
1075 ir_node *block = block_schedule[i];
1076 ir_node *next_block = i+1 < n ? block_schedule[i+1] : NULL;
1077 set_irn_link(block, next_block);
1080 for (i = 0; i < n; ++i) {
1081 ir_node *block = block_schedule[i];
1082 if (block == get_irg_end_block(irg))
1084 sparc_emit_block(block);
1087 /* emit function epilog */
1088 sparc_emit_func_epilog(irg);
1090 heights_free(heights);
1093 void sparc_init_emitter(void)
1095 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.emit");