2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
40 #include "raw_bitset.h"
43 #include "../besched.h"
44 #include "../beblocksched.h"
46 #include "../begnuas.h"
47 #include "../be_dbgout.h"
48 #include "../benode.h"
50 #include "sparc_emitter.h"
51 #include "gen_sparc_emitter.h"
52 #include "sparc_nodes_attr.h"
53 #include "sparc_new_nodes.h"
54 #include "gen_sparc_regalloc_if.h"
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 * Returns the register at in position pos.
61 static const arch_register_t *get_in_reg(const ir_node *node, int pos)
64 const arch_register_t *reg = NULL;
66 assert(get_irn_arity(node) > pos && "Invalid IN position");
68 /* The out register of the operator at position pos is the
69 in register we need. */
70 op = get_irn_n(node, pos);
72 reg = arch_get_irn_register(op);
74 assert(reg && "no in register found");
79 * Returns the register at out position pos.
81 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
84 const arch_register_t *reg = NULL;
86 /* 1st case: irn is not of mode_T, so it has only */
87 /* one OUT register -> good */
88 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
89 /* Proj with the corresponding projnum for the register */
91 if (get_irn_mode(node) != mode_T) {
92 reg = arch_get_irn_register(node);
93 } else if (is_sparc_irn(node)) {
94 reg = arch_irn_get_register(node, pos);
96 const ir_edge_t *edge;
98 foreach_out_edge(node, edge) {
99 proj = get_edge_src_irn(edge);
100 assert(is_Proj(proj) && "non-Proj from mode_T node");
101 if (get_Proj_proj(proj) == pos) {
102 reg = arch_get_irn_register(proj);
108 assert(reg && "no out register found");
112 void sparc_emit_immediate(const ir_node *node)
114 int const val = get_sparc_attr_const(node)->immediate_value;
115 assert(-4096 <= val && val < 4096);
116 be_emit_irprintf("%d", val);
119 void sparc_emit_source_register(const ir_node *node, int pos)
121 const arch_register_t *reg = get_in_reg(node, pos);
123 be_emit_string(arch_register_get_name(reg));
126 void sparc_emit_dest_register(const ir_node *node, int pos)
128 const arch_register_t *reg = get_out_reg(node, pos);
130 be_emit_string(arch_register_get_name(reg));
134 * Emits either a imm or register depending on arity of node
136 * @param register no (-1 if no register)
138 void sparc_emit_reg_or_imm(const ir_node *node, int pos)
140 if (get_irn_arity(node) > pos) {
142 sparc_emit_source_register(node, pos);
144 // we have a imm input
145 sparc_emit_immediate(node);
149 static bool is_stack_pointer_relative(const ir_node *node)
151 const arch_register_t *sp = &sparc_gp_regs[REG_SP];
152 return (is_sparc_St(node) && get_in_reg(node, n_sparc_St_ptr) == sp)
153 || (is_sparc_Ld(node) && get_in_reg(node, n_sparc_Ld_ptr) == sp);
159 void sparc_emit_offset(const ir_node *node)
161 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
162 long offset = attr->offset;
164 /* bad hack: the real stack stuff is behind the always-there spill
165 * space for the register window and stack */
166 if (is_stack_pointer_relative(node))
167 offset += SPARC_MIN_STACKSIZE;
169 be_emit_irprintf("%+ld", offset);
173 void sparc_emit_float_load_store_mode(const ir_node *node)
175 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
176 ir_mode *mode = attr->load_store_mode;
177 int bits = get_mode_size_bits(mode);
179 assert(mode_is_float(mode));
183 case 64: be_emit_char('d'); return;
184 case 128: be_emit_char('q'); return;
186 panic("invalid flaot load/store mode %+F", mode);
190 * Emit load mode char
192 void sparc_emit_load_mode(const ir_node *node)
194 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
195 ir_mode *mode = attr->load_store_mode;
196 int bits = get_mode_size_bits(mode);
197 bool is_signed = mode_is_signed(mode);
200 be_emit_string(is_signed ? "sh" : "uh");
201 } else if (bits == 8) {
202 be_emit_string(is_signed ? "sb" : "ub");
203 } else if (bits == 64) {
211 * Emit store mode char
213 void sparc_emit_store_mode(const ir_node *node)
215 const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(node);
216 ir_mode *mode = attr->load_store_mode;
217 int bits = get_mode_size_bits(mode);
221 } else if (bits == 8) {
223 } else if (bits == 64) {
231 * emit integer signed/unsigned prefix char
233 void sparc_emit_mode_sign_prefix(const ir_node *node)
235 ir_mode *mode = get_irn_mode(node);
236 bool is_signed = mode_is_signed(mode);
237 be_emit_string(is_signed ? "s" : "u");
240 static void emit_fp_suffix(const ir_mode *mode)
242 unsigned bits = get_mode_size_bits(mode);
243 assert(mode_is_float(mode));
247 } else if (bits == 64) {
249 } else if (bits == 128) {
252 panic("invalid FP mode");
256 void sparc_emit_fp_conv_source(const ir_node *node)
258 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
259 emit_fp_suffix(attr->src_mode);
262 void sparc_emit_fp_conv_destination(const ir_node *node)
264 const sparc_fp_conv_attr_t *attr = get_sparc_fp_conv_attr_const(node);
265 emit_fp_suffix(attr->dest_mode);
269 * emits the FP mode suffix char
271 void sparc_emit_fp_mode_suffix(const ir_node *node)
273 const sparc_fp_attr_t *attr = get_sparc_fp_attr_const(node);
274 emit_fp_suffix(attr->fp_mode);
278 * Returns the target label for a control flow node.
280 static void sparc_emit_cfop_target(const ir_node *node)
282 ir_node *block = get_irn_link(node);
283 be_gas_emit_block_name(block);
289 static void sparc_emit_entity(ir_entity *entity)
291 be_gas_emit_entity(entity);
295 * Emits code for stack space management
297 static void emit_be_IncSP(const ir_node *irn)
299 int offs = -be_get_IncSP_offset(irn);
304 /* SPARC stack grows downwards */
306 be_emit_cstring("\tsub ");
309 be_emit_cstring("\tadd ");
312 sparc_emit_source_register(irn, 0);
313 be_emit_irprintf(", %d", offs);
314 be_emit_cstring(", ");
315 sparc_emit_dest_register(irn, 0);
316 be_emit_finish_line_gas(irn);
320 * emits code for save instruction with min. required stack space
322 static void emit_sparc_Save(const ir_node *irn)
324 const sparc_save_attr_t *save_attr = get_sparc_save_attr_const(irn);
325 be_emit_cstring("\tsave ");
326 sparc_emit_source_register(irn, 0);
327 be_emit_irprintf(", %d, ", -save_attr->initial_stacksize);
328 sparc_emit_dest_register(irn, 0);
329 be_emit_finish_line_gas(irn);
333 * emits code to load hi 22 bit of a constant
335 static void emit_sparc_HiImm(const ir_node *irn)
337 const sparc_attr_t *attr = get_sparc_attr_const(irn);
338 be_emit_cstring("\tsethi ");
339 be_emit_irprintf("%%hi(%d), ", attr->immediate_value);
340 sparc_emit_dest_register(irn, 0);
341 be_emit_finish_line_gas(irn);
345 * emits code to load lo 10bits of a constant
347 static void emit_sparc_LoImm(const ir_node *irn)
349 const sparc_attr_t *attr = get_sparc_attr_const(irn);
350 be_emit_cstring("\tor ");
351 sparc_emit_source_register(irn, 0);
352 be_emit_irprintf(", %%lo(%d), ", attr->immediate_value);
353 sparc_emit_dest_register(irn, 0);
354 be_emit_finish_line_gas(irn);
358 * emits code for mulh
360 static void emit_sparc_Mulh(const ir_node *irn)
362 be_emit_cstring("\t");
363 sparc_emit_mode_sign_prefix(irn);
364 be_emit_cstring("mul ");
366 sparc_emit_source_register(irn, 0);
367 be_emit_cstring(", ");
368 sparc_emit_reg_or_imm(irn, 1);
369 be_emit_cstring(", ");
370 sparc_emit_dest_register(irn, 0);
371 be_emit_finish_line_gas(irn);
373 // our result is in the y register now
374 // we just copy it to the assigned target reg
375 be_emit_cstring("\tmov %y, ");
376 sparc_emit_dest_register(irn, 0);
377 be_emit_finish_line_gas(irn);
380 static void emit_sparc_Div(const ir_node *node, bool is_signed)
382 /* can we get the delay count of the wr instruction somewhere? */
383 unsigned wry_delay_count = 3;
386 be_emit_cstring("\twr ");
387 sparc_emit_source_register(node, 0);
388 be_emit_cstring(", 0, %y");
389 be_emit_finish_line_gas(node);
391 for (i = 0; i < wry_delay_count; ++i) {
392 be_emit_cstring("\tnop");
393 be_emit_finish_line_gas(node);
396 be_emit_irprintf("\t%s ", is_signed ? "sdiv" : "udiv");
397 sparc_emit_source_register(node, 1);
398 be_emit_cstring(", ");
399 sparc_emit_source_register(node, 2);
400 be_emit_cstring(", ");
401 sparc_emit_dest_register(node, 0);
402 be_emit_finish_line_gas(node);
405 static void emit_sparc_SDiv(const ir_node *node)
408 /* aehm we would need an aditional register for an sra instruction to
409 * compute the upper bits... Just panic for now */
410 //emit_sparc_Div(node, true);
411 panic("signed div is wrong");
414 static void emit_sparc_UDiv(const ir_node *node)
416 emit_sparc_Div(node, false);
420 * Emits code for return node
422 static void emit_be_Return(const ir_node *irn)
424 be_emit_cstring("\tret");
425 //be_emit_cstring("\tjmp %i7+8");
426 be_emit_finish_line_gas(irn);
427 be_emit_cstring("\trestore");
428 be_emit_finish_line_gas(irn);
432 * Emits code for Call node
434 static void emit_sparc_Call(const ir_node *node)
436 const sparc_attr_t *attr = get_sparc_attr_const(node);
437 ir_entity *entity = attr->immediate_value_entity;
439 be_emit_cstring("\tcall ");
440 if (entity != NULL) {
441 sparc_emit_entity(entity);
442 be_emit_cstring(", 0");
444 int last = get_irn_arity(node);
445 sparc_emit_source_register(node, last-1);
447 be_emit_finish_line_gas(node);
449 /* fill delay slot */
450 be_emit_cstring("\tnop");
451 be_emit_finish_line_gas(node);
455 * Emit code for Perm node
457 static void emit_be_Perm(const ir_node *irn)
459 be_emit_cstring("\txor ");
460 sparc_emit_source_register(irn, 1);
461 be_emit_cstring(", ");
462 sparc_emit_source_register(irn, 0);
463 be_emit_cstring(", ");
464 sparc_emit_source_register(irn, 0);
465 be_emit_finish_line_gas(NULL);
467 be_emit_cstring("\txor ");
468 sparc_emit_source_register(irn, 1);
469 be_emit_cstring(", ");
470 sparc_emit_source_register(irn, 0);
471 be_emit_cstring(", ");
472 sparc_emit_source_register(irn, 1);
473 be_emit_finish_line_gas(NULL);
475 be_emit_cstring("\txor ");
476 sparc_emit_source_register(irn, 1);
477 be_emit_cstring(", ");
478 sparc_emit_source_register(irn, 0);
479 be_emit_cstring(", ");
480 sparc_emit_source_register(irn, 0);
481 be_emit_finish_line_gas(irn);
485 * TODO: not really tested but seems to work with memperm_arity == 1
487 static void emit_be_MemPerm(const ir_node *node)
492 ir_graph *irg = get_irn_irg(node);
493 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
495 /* this implementation only works with frame pointers currently */
496 assert(layout->sp_relative == false);
498 /* TODO: this implementation is slower than necessary.
499 The longterm goal is however to avoid the memperm node completely */
501 memperm_arity = be_get_MemPerm_entity_arity(node);
502 // we use our local registers - so this is limited to 8 inputs !
503 if (memperm_arity > 8)
504 panic("memperm with more than 8 inputs not supported yet");
506 be_emit_irprintf("\tsub %%sp, %d, %%sp", memperm_arity*4);
507 be_emit_finish_line_gas(node);
509 for (i = 0; i < memperm_arity; ++i) {
510 ir_entity *entity = be_get_MemPerm_in_entity(node, i);
511 int offset = be_get_stack_entity_offset(layout, entity, 0);
514 be_emit_irprintf("\tst %%l%d, [%%sp%+d]", i, sp_change + SPARC_MIN_STACKSIZE);
515 be_emit_finish_line_gas(node);
517 /* load from entity */
518 be_emit_irprintf("\tld [%%fp%+d], %%l%d", offset, i);
519 be_emit_finish_line_gas(node);
523 for (i = memperm_arity-1; i >= 0; --i) {
524 ir_entity *entity = be_get_MemPerm_out_entity(node, i);
525 int offset = be_get_stack_entity_offset(layout, entity, 0);
529 /* store to new entity */
530 be_emit_irprintf("\tst %%l%d, [%%fp%+d]", i, offset);
531 be_emit_finish_line_gas(node);
532 /* restore register */
533 be_emit_irprintf("\tld [%%sp%+d], %%l%d", sp_change + SPARC_MIN_STACKSIZE, i);
534 be_emit_finish_line_gas(node);
537 be_emit_irprintf("\tadd %%sp, %d, %%sp", memperm_arity*4);
538 be_emit_finish_line_gas(node);
540 assert(sp_change == 0);
546 static void emit_sparc_SymConst(const ir_node *irn)
548 const sparc_symconst_attr_t *attr = get_sparc_symconst_attr_const(irn);
550 //sethi %hi(const32),%reg
551 //or %reg,%lo(const32),%reg
553 be_emit_cstring("\tsethi %hi(");
554 be_gas_emit_entity(attr->entity);
555 be_emit_cstring("), ");
556 sparc_emit_dest_register(irn, 0);
557 be_emit_cstring("\n ");
559 // TODO: could be combined with the following load/store instruction
560 be_emit_cstring("\tor ");
561 sparc_emit_dest_register(irn, 0);
562 be_emit_cstring(", %lo(");
563 be_gas_emit_entity(attr->entity);
564 be_emit_cstring("), ");
565 sparc_emit_dest_register(irn, 0);
566 be_emit_finish_line_gas(irn);
570 * Emits code for FrameAddr fix
572 static void emit_sparc_FrameAddr(const ir_node *irn)
574 const sparc_symconst_attr_t *attr = get_irn_generic_attr_const(irn);
576 // no need to fix offset as we are adressing via the framepointer
577 if (attr->fp_offset >= 0) {
578 be_emit_cstring("\tadd ");
579 sparc_emit_source_register(irn, 0);
580 be_emit_cstring(", ");
581 be_emit_irprintf("%ld", attr->fp_offset);
583 be_emit_cstring("\tsub ");
584 sparc_emit_source_register(irn, 0);
585 be_emit_cstring(", ");
586 be_emit_irprintf("%ld", -attr->fp_offset);
589 be_emit_cstring(", ");
590 sparc_emit_dest_register(irn, 0);
591 be_emit_finish_line_gas(irn);
594 static const char *get_icc_unsigned(pn_Cmp pnc)
597 case pn_Cmp_False: return "bn";
598 case pn_Cmp_Eq: return "be";
599 case pn_Cmp_Lt: return "blu";
600 case pn_Cmp_Le: return "bleu";
601 case pn_Cmp_Gt: return "bgu";
602 case pn_Cmp_Ge: return "bgeu";
603 case pn_Cmp_Lg: return "bne";
604 case pn_Cmp_Leg: return "ba";
605 default: panic("Cmp has unsupported pnc");
609 static const char *get_icc_signed(pn_Cmp pnc)
612 case pn_Cmp_False: return "bn";
613 case pn_Cmp_Eq: return "be";
614 case pn_Cmp_Lt: return "bl";
615 case pn_Cmp_Le: return "ble";
616 case pn_Cmp_Gt: return "bg";
617 case pn_Cmp_Ge: return "bge";
618 case pn_Cmp_Lg: return "bne";
619 case pn_Cmp_Leg: return "ba";
620 default: panic("Cmp has unsupported pnc");
624 static const char *get_fcc(pn_Cmp pnc)
627 case pn_Cmp_False: return "fbn";
628 case pn_Cmp_Eq: return "fbe";
629 case pn_Cmp_Lt: return "fbl";
630 case pn_Cmp_Le: return "fble";
631 case pn_Cmp_Gt: return "fbg";
632 case pn_Cmp_Ge: return "fbge";
633 case pn_Cmp_Lg: return "fblg";
634 case pn_Cmp_Leg: return "fbo";
635 case pn_Cmp_Uo: return "fbu";
636 case pn_Cmp_Ue: return "fbue";
637 case pn_Cmp_Ul: return "fbul";
638 case pn_Cmp_Ule: return "fbule";
639 case pn_Cmp_Ug: return "fbug";
640 case pn_Cmp_Uge: return "fbuge";
641 case pn_Cmp_Ne: return "fbne";
642 case pn_Cmp_True: return "fba";
646 panic("invalid pnc");
649 typedef const char* (*get_cc_func)(pn_Cmp pnc);
652 * Emits code for Branch
654 static void emit_sparc_branch(const ir_node *node, get_cc_func get_cc)
656 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
657 pn_Cmp pnc = attr->pnc;
658 const ir_node *proj_true = NULL;
659 const ir_node *proj_false = NULL;
660 const ir_edge_t *edge;
661 const ir_node *block;
662 const ir_node *next_block;
664 foreach_out_edge(node, edge) {
665 ir_node *proj = get_edge_src_irn(edge);
666 long nr = get_Proj_proj(proj);
667 if (nr == pn_Cond_true) {
674 /* for now, the code works for scheduled and non-schedules blocks */
675 block = get_nodes_block(node);
677 /* we have a block schedule */
678 next_block = get_irn_link(block);
680 if (get_irn_link(proj_true) == next_block) {
681 /* exchange both proj's so the second one can be omitted */
682 const ir_node *t = proj_true;
684 proj_true = proj_false;
686 if (is_sparc_fbfcc(node)) {
687 pnc = get_negated_pnc(pnc, mode_F);
689 pnc = get_negated_pnc(pnc, mode_Iu);
693 /* emit the true proj */
694 be_emit_cstring("\t");
695 be_emit_string(get_cc(pnc));
697 sparc_emit_cfop_target(proj_true);
698 be_emit_finish_line_gas(proj_true);
700 be_emit_cstring("\tnop");
701 be_emit_pad_comment();
702 be_emit_cstring("/* TODO: use delay slot */\n");
704 if (get_irn_link(proj_false) == next_block) {
705 be_emit_cstring("\t/* fallthrough to ");
706 sparc_emit_cfop_target(proj_false);
707 be_emit_cstring(" */");
708 be_emit_finish_line_gas(proj_false);
710 be_emit_cstring("\tba ");
711 sparc_emit_cfop_target(proj_false);
712 be_emit_finish_line_gas(proj_false);
713 be_emit_cstring("\tnop\t\t/* TODO: use delay slot */\n");
714 be_emit_finish_line_gas(proj_false);
718 static void emit_sparc_Bicc(const ir_node *node)
720 const sparc_jmp_cond_attr_t *attr = get_sparc_jmp_cond_attr_const(node);
721 bool is_unsigned = attr->is_unsigned;
722 emit_sparc_branch(node, is_unsigned ? get_icc_unsigned : get_icc_signed);
725 static void emit_sparc_fbfcc(const ir_node *node)
727 emit_sparc_branch(node, get_fcc);
731 * emit Jmp (which actually is a branch always (ba) instruction)
733 static void emit_sparc_Ba(const ir_node *node)
735 ir_node *block, *next_block;
737 /* for now, the code works for scheduled and non-schedules blocks */
738 block = get_nodes_block(node);
740 /* we have a block schedule */
741 next_block = get_irn_link(block);
742 if (get_irn_link(node) != next_block) {
743 be_emit_cstring("\tba ");
744 sparc_emit_cfop_target(node);
745 be_emit_finish_line_gas(node);
746 be_emit_cstring("\tnop\t\t/* TODO: use delay slot */\n");
748 be_emit_cstring("\t/* fallthrough to ");
749 sparc_emit_cfop_target(node);
750 be_emit_cstring(" */");
752 be_emit_finish_line_gas(node);
755 static void emit_fmov(const ir_node *node, const arch_register_t *src_reg,
756 const arch_register_t *dst_reg)
758 be_emit_cstring("\tfmov ");
759 be_emit_string(arch_register_get_name(src_reg));
760 be_emit_cstring(", ");
761 be_emit_string(arch_register_get_name(dst_reg));
762 be_emit_finish_line_gas(node);
765 static const arch_register_t *get_next_fp_reg(const arch_register_t *reg)
767 unsigned index = reg->index;
768 assert(reg == &sparc_fp_regs[index]);
770 assert(index < N_sparc_fp_REGS);
771 return &sparc_fp_regs[index];
777 static void emit_be_Copy(const ir_node *node)
779 ir_mode *mode = get_irn_mode(node);
780 const arch_register_t *src_reg = get_in_reg(node, 0);
781 const arch_register_t *dst_reg = get_out_reg(node, 0);
783 if (src_reg == dst_reg)
786 if (mode_is_float(mode)) {
787 unsigned bits = get_mode_size_bits(mode);
788 int n = bits > 32 ? bits > 64 ? 3 : 1 : 0;
790 emit_fmov(node, src_reg, dst_reg);
791 for (i = 0; i < n; ++i) {
792 src_reg = get_next_fp_reg(src_reg);
793 dst_reg = get_next_fp_reg(dst_reg);
794 emit_fmov(node, src_reg, dst_reg);
796 } else if (mode_is_data(mode)) {
797 be_emit_cstring("\tmov ");
798 sparc_emit_source_register(node, 0);
799 be_emit_cstring(", ");
800 sparc_emit_dest_register(node, 0);
801 be_emit_finish_line_gas(node);
803 panic("emit_be_Copy: invalid mode");
809 * dummy emitter for ignored nodes
811 static void emit_nothing(const ir_node *irn)
817 * type of emitter function
819 typedef void (*emit_func) (const ir_node *);
822 * Set a node emitter. Make it a bit more type safe.
824 static inline void set_emitter(ir_op *op, emit_func sparc_emit_node)
826 op->ops.generic = (op_func)sparc_emit_node;
830 * Enters the emitter functions for handled nodes into the generic
831 * pointer of an opcode.
833 static void sparc_register_emitters(void)
835 /* first clear the generic function pointer for all ops */
836 clear_irp_opcodes_generic_func();
837 /* register all emitter functions defined in spec */
838 sparc_register_spec_emitters();
841 set_emitter(op_be_Copy, emit_be_Copy);
842 set_emitter(op_be_CopyKeep, emit_be_Copy);
843 set_emitter(op_be_IncSP, emit_be_IncSP);
844 set_emitter(op_be_MemPerm, emit_be_MemPerm);
845 set_emitter(op_be_Perm, emit_be_Perm);
846 set_emitter(op_be_Return, emit_be_Return);
847 set_emitter(op_sparc_Ba, emit_sparc_Ba);
848 set_emitter(op_sparc_Bicc, emit_sparc_Bicc);
849 set_emitter(op_sparc_Call, emit_sparc_Call);
850 set_emitter(op_sparc_fbfcc, emit_sparc_fbfcc);
851 set_emitter(op_sparc_FrameAddr, emit_sparc_FrameAddr);
852 set_emitter(op_sparc_HiImm, emit_sparc_HiImm);
853 set_emitter(op_sparc_LoImm, emit_sparc_LoImm);
854 set_emitter(op_sparc_Mulh, emit_sparc_Mulh);
855 set_emitter(op_sparc_Save, emit_sparc_Save);
856 set_emitter(op_sparc_SDiv, emit_sparc_SDiv);
857 set_emitter(op_sparc_SymConst, emit_sparc_SymConst);
858 set_emitter(op_sparc_UDiv, emit_sparc_UDiv);
860 /* no need to emit anything for the following nodes */
861 set_emitter(op_be_Barrier, emit_nothing);
862 set_emitter(op_be_Keep, emit_nothing);
863 set_emitter(op_be_Start, emit_nothing);
864 set_emitter(op_Phi, emit_nothing);
868 * Emits code for a node.
870 static void sparc_emit_node(const ir_node *node)
872 ir_op *op = get_irn_op(node);
874 if (op->ops.generic) {
875 emit_func func = (emit_func) op->ops.generic;
876 be_dbg_set_dbg_info(get_irn_dbg_info(node));
879 panic("No emit handler for node %+F (graph %+F)\n", node,
885 * Walks over the nodes in a block connected by scheduling edges
886 * and emits code for each node.
888 static void sparc_gen_block(ir_node *block, void *data)
893 if (! is_Block(block))
896 be_gas_emit_block_name(block);
897 be_emit_cstring(":\n");
898 be_emit_write_line();
900 sched_foreach(block, node) {
901 sparc_emit_node(node);
907 * Emits code for function start.
909 static void sparc_emit_func_prolog(ir_graph *irg)
911 ir_entity *ent = get_irg_entity(irg);
912 be_gas_emit_function_prolog(ent, 4);
913 be_emit_write_line();
917 * Emits code for function end
919 static void sparc_emit_func_epilog(ir_graph *irg)
921 ir_entity *ent = get_irg_entity(irg);
922 const char *irg_name = get_entity_ld_name(ent);
923 be_emit_write_line();
924 be_emit_irprintf("\t.size %s, .-%s\n", irg_name, irg_name);
925 be_emit_cstring("# -- End ");
926 be_emit_string(irg_name);
927 be_emit_cstring("\n");
928 be_emit_write_line();
933 * TODO: Sets labels for control flow nodes (jump target).
934 * Links control predecessors to there destination blocks.
936 static void sparc_gen_labels(ir_node *block, void *env)
939 int n = get_Block_n_cfgpreds(block);
942 for (n--; n >= 0; n--) {
943 pred = get_Block_cfgpred(block, n);
944 set_irn_link(pred, block); // link the pred of a block (which is a jmp)
952 void sparc_gen_routine(const sparc_code_gen_t *cg, ir_graph *irg)
955 ir_node *last_block = NULL;
956 ir_entity *entity = get_irg_entity(irg);
960 be_gas_elf_type_char = '#';
961 be_gas_object_file_format = OBJECT_FILE_FORMAT_ELF_SPARC;
963 /* register all emitter functions */
964 sparc_register_emitters();
965 be_dbg_method_begin(entity);
967 /* create the block schedule. For now, we don't need it earlier. */
968 blk_sched = be_create_block_schedule(irg);
970 // emit function prolog
971 sparc_emit_func_prolog(irg);
973 // generate BLOCK labels
974 irg_block_walk_graph(irg, sparc_gen_labels, NULL, NULL);
976 // inject block scheduling links & emit code of each block
977 n = ARR_LEN(blk_sched);
978 for (i = 0; i < n;) {
979 ir_node *block, *next_bl;
981 block = blk_sched[i];
983 next_bl = i < n ? blk_sched[i] : NULL;
985 /* set here the link. the emitter expects to find the next block here */
986 set_irn_link(block, next_bl);
987 sparc_gen_block(block, last_block);
991 // emit function epilog
992 sparc_emit_func_epilog(irg);
995 void sparc_init_emitter(void)
997 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.emit");