nsz Git - libfirm/blob - ir/be/sparc/sparc_cconv.c

   1 /*
   2  * Copyright (C) 1995-2010 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief   calling convention helpers
  23  * @author  Matthias Braun
  24  */
  25 #include "config.h"
  26
  27 #include "sparc_cconv.h"
  28 #include "irmode.h"
  29 #include "irgwalk.h"
  30 #include "typerep.h"
  31 #include "xmalloc.h"
  32 #include "util.h"
  33 #include "error.h"
  34 #include "gen_sparc_regalloc_if.h"
  35 #include "bitfiddle.h"
  36
  37 static const unsigned ignore_regs[] = {
  38         REG_G0,
  39         /* used in case an address offset does not fit into an immediate: */
  40         REG_G4,
  41         /* reserved for SPARC ABI: */
  42         REG_G5,
  43         REG_G6,
  44         REG_G7,
  45
  46         REG_SP,
  47         REG_O7,
  48         REG_FRAME_POINTER,
  49         REG_I7,
  50
  51         REG_FPFLAGS,
  52         REG_FLAGS,
  53         REG_Y,
  54 };
  55
  56 static const arch_register_t* const param_regs[] = {
  57         &sparc_registers[REG_I0],
  58         &sparc_registers[REG_I1],
  59         &sparc_registers[REG_I2],
  60         &sparc_registers[REG_I3],
  61         &sparc_registers[REG_I4],
  62         &sparc_registers[REG_I5],
  63 };
  64 COMPILETIME_ASSERT(ARRAY_SIZE(param_regs) == SPARC_N_PARAM_REGS, sparcparamregs)
  65
  66 static const arch_register_t* const float_result_regs[] = {
  67         &sparc_registers[REG_F0],
  68         &sparc_registers[REG_F1],
  69         &sparc_registers[REG_F2],
  70         &sparc_registers[REG_F3],
  71         &sparc_registers[REG_F4],
  72         &sparc_registers[REG_F5],
  73         &sparc_registers[REG_F6],
  74         &sparc_registers[REG_F7],
  75 };
  76 static arch_register_req_t float_result_reqs_double[8];
  77 static arch_register_req_t float_result_reqs_quad[8];
  78
  79 static const unsigned caller_saves[] = {
  80         REG_G1,
  81         REG_G2,
  82         REG_G3,
  83         REG_O0,
  84         REG_O1,
  85         REG_O2,
  86         REG_O3,
  87         REG_O4,
  88         REG_O5,
  89         REG_F0,
  90         REG_F1,
  91         REG_F2,
  92         REG_F3,
  93         REG_F4,
  94         REG_F5,
  95         REG_F6,
  96         REG_F7,
  97         REG_F8,
  98         REG_F9,
  99         REG_F10,
 100         REG_F11,
 101         REG_F12,
 102         REG_F13,
 103         REG_F14,
 104         REG_F15,
 105         REG_F16,
 106         REG_F17,
 107         REG_F18,
 108         REG_F19,
 109         REG_F20,
 110         REG_F21,
 111         REG_F22,
 112         REG_F23,
 113         REG_F24,
 114         REG_F25,
 115         REG_F26,
 116         REG_F27,
 117         REG_F28,
 118         REG_F29,
 119         REG_F30,
 120         REG_F31,
 121 };
 122 static unsigned default_caller_saves[BITSET_SIZE_ELEMS(N_SPARC_REGISTERS)];
 123
 124 static const unsigned returns_twice_saved[] = {
 125         REG_SP,
 126         REG_FRAME_POINTER,
 127         REG_I7
 128 };
 129 static unsigned default_returns_twice_saves[BITSET_SIZE_ELEMS(N_SPARC_REGISTERS)];
 130
 131 /**
 132  * Maps an input register representing the i'th register input
 133  * to the i'th register output.
 134  */
 135 static const arch_register_t *map_i_to_o_reg(const arch_register_t *reg)
 136 {
 137         unsigned idx = reg->global_index;
 138         assert(REG_I0 <= idx && idx <= REG_I7);
 139         idx += REG_O0 - REG_I0;
 140         assert(REG_O0 <= idx && idx <= REG_O7);
 141         return &sparc_registers[idx];
 142 }
 143
 144 static void check_omit_fp(ir_node *node, void *env)
 145 {
 146         bool *can_omit_fp = (bool*) env;
 147
 148         /* omit-fp is not possible if:
 149          *  - we have allocations on the stack
 150          *  - we have calls (with the exception of tail-calls once we support them)
 151          */
 152         if ((is_Alloc(node) && get_Alloc_where(node) == stack_alloc)
 153                         || (is_Free(node) && get_Free_where(node) == stack_alloc)
 154                         || is_Call(node)) {
 155                 *can_omit_fp = false;
 156         }
 157 }
 158
 159 static unsigned determine_n_float_regs(ir_mode *mode)
 160 {
 161         unsigned bits = get_mode_size_bits(mode);
 162         switch (bits) {
 163         case 32:
 164                 return 1;
 165         case 64:
 166                 return 2;
 167         case 128:
 168                 return 4;
 169         default:
 170                 panic("sparc: Unexpected floatingpoint mode %+F", mode);
 171         }
 172 }
 173
 174 calling_convention_t *sparc_decide_calling_convention(ir_type *function_type,
 175                                                       ir_graph *irg)
 176 {
 177         unsigned              stack_offset        = 0;
 178         unsigned              n_param_regs_used   = 0;
 179         int                   n_param_regs        = ARRAY_SIZE(param_regs);
 180         unsigned              n_float_result_regs = ARRAY_SIZE(float_result_regs);
 181         bool                  omit_fp             = false;
 182         mtp_additional_properties mtp
 183                 = get_method_additional_properties(function_type);
 184         reg_or_stackslot_t   *params;
 185         reg_or_stackslot_t   *results;
 186         int                   n_params;
 187         int                   n_results;
 188         int                   i;
 189         int                   regnum;
 190         unsigned              float_regnum;
 191         unsigned              n_reg_results = 0;
 192         calling_convention_t *cconv;
 193         unsigned             *caller_saves;
 194
 195         if (irg != NULL) {
 196                 const be_options_t *options = be_get_irg_options(irg);
 197                 omit_fp = options->omit_fp;
 198                 /* our current vaarg handling needs the standard space to store the
 199                  * args 0-5 in it */
 200                 if (get_method_variadicity(function_type) == variadicity_variadic)
 201                         omit_fp = false;
 202                 if (omit_fp == true) {
 203                         irg_walk_graph(irg, check_omit_fp, NULL, &omit_fp);
 204                 }
 205         }
 206
 207         caller_saves = rbitset_malloc(N_SPARC_REGISTERS);
 208         if (mtp & mtp_property_returns_twice) {
 209                 rbitset_copy(caller_saves, default_returns_twice_saves,
 210                              N_SPARC_REGISTERS);
 211         } else {
 212                 rbitset_copy(caller_saves, default_caller_saves, N_SPARC_REGISTERS);
 213         }
 214
 215         /* determine how parameters are passed */
 216         n_params = get_method_n_params(function_type);
 217         regnum   = 0;
 218         params   = XMALLOCNZ(reg_or_stackslot_t, n_params);
 219
 220         for (i = 0; i < n_params; ++i) {
 221                 ir_type            *param_type = get_method_param_type(function_type,i);
 222                 ir_mode            *mode;
 223                 int                 bits;
 224                 reg_or_stackslot_t *param;
 225
 226                 if (is_compound_type(param_type))
 227                         panic("sparc: compound arguments not supported yet");
 228
 229                 mode  = get_type_mode(param_type);
 230                 bits  = get_mode_size_bits(mode);
 231                 param = &params[i];
 232
 233                 if (i == 0 &&
 234                     (get_method_calling_convention(function_type) & cc_compound_ret)) {
 235                         assert(mode_is_reference(mode) && bits == 32);
 236                         /* special case, we have reserved space for this on the between
 237                          * type */
 238                         param->type   = param_type;
 239                         param->offset = -SPARC_MIN_STACKSIZE+SPARC_AGGREGATE_RETURN_OFFSET;
 240                         continue;
 241                 }
 242
 243                 if (regnum < n_param_regs) {
 244                         const arch_register_t *reg = param_regs[regnum];
 245                         if (irg == NULL || omit_fp)
 246                                 reg = map_i_to_o_reg(reg);
 247                         param->reg0       = reg;
 248                         param->req0       = reg->single_req;
 249                         param->reg_offset = regnum;
 250                         ++regnum;
 251                 } else {
 252                         param->type   = param_type;
 253                         param->offset = stack_offset;
 254                         /* increase offset by at least SPARC_REGISTER_SIZE bytes so everything is aligned */
 255                         stack_offset += bits > 8 * SPARC_REGISTER_SIZE ? bits / 8 : SPARC_REGISTER_SIZE;
 256                         continue;
 257                 }
 258
 259                 /* we might need a 2nd 32bit component (for 64bit or double values) */
 260                 if (bits > 32) {
 261                         if (bits > 64)
 262                                 panic("only 32 and 64bit modes supported in sparc backend");
 263
 264                         if (regnum < n_param_regs) {
 265                                 const arch_register_t *reg = param_regs[regnum];
 266                                 if (irg == NULL || omit_fp)
 267                                         reg = map_i_to_o_reg(reg);
 268                                 param->reg1       = reg;
 269                                 param->req1       = reg->single_req;
 270                                 ++regnum;
 271                         } else {
 272                                 ir_mode *regmode = param_regs[0]->reg_class->mode;
 273                                 ir_type *type    = get_type_for_mode(regmode);
 274                                 param->type      = type;
 275                                 param->offset    = stack_offset;
 276                                 assert(get_mode_size_bits(regmode) == 32);
 277                                 stack_offset += SPARC_REGISTER_SIZE;
 278                         }
 279                 }
 280         }
 281         n_param_regs_used = regnum;
 282
 283         /* determine how results are passed */
 284         n_results    = get_method_n_ress(function_type);
 285         regnum       = 0;
 286         float_regnum = 0;
 287         results      = XMALLOCNZ(reg_or_stackslot_t, n_results);
 288         for (i = 0; i < n_results; ++i) {
 289                 ir_type            *result_type = get_method_res_type(function_type, i);
 290                 ir_mode            *result_mode = get_type_mode(result_type);
 291                 reg_or_stackslot_t *result      = &results[i];
 292
 293                 if (mode_is_float(result_mode)) {
 294                         unsigned n_regs   = determine_n_float_regs(result_mode);
 295                         unsigned next_reg = round_up2(float_regnum, n_regs);
 296
 297                         if (next_reg >= n_float_result_regs) {
 298                                 panic("Too many float results for sparc backend");
 299                         } else {
 300                                 const arch_register_t *reg = float_result_regs[next_reg];
 301                                 rbitset_clear(caller_saves, reg->global_index);
 302                                 result->reg_offset = i;
 303                                 if (n_regs == 1) {
 304                                         result->req0 = reg->single_req;
 305                                 } else if (n_regs == 2) {
 306                                         result->req0 = &float_result_reqs_double[next_reg];
 307                                         rbitset_clear(caller_saves, reg->global_index+1);
 308                                 } else if (n_regs == 4) {
 309                                         result->req0 = &float_result_reqs_quad[next_reg];
 310                                         rbitset_clear(caller_saves, reg->global_index+1);
 311                                         rbitset_clear(caller_saves, reg->global_index+2);
 312                                         rbitset_clear(caller_saves, reg->global_index+3);
 313                                 } else {
 314                                         panic("invalid number of registers in sparc float result");
 315                                 }
 316                                 float_regnum = next_reg + n_regs;
 317
 318                                 ++n_reg_results;
 319                         }
 320                 } else {
 321                         if (get_mode_size_bits(result_mode) > 32) {
 322                                 panic("Results with more than 32bits not supported by sparc backend yet");
 323                         }
 324
 325                         if (regnum >= n_param_regs) {
 326                                 panic("Too many results for sparc backend");
 327                         } else {
 328                                 const arch_register_t *reg = param_regs[regnum++];
 329                                 if (irg == NULL || omit_fp)
 330                                         reg = map_i_to_o_reg(reg);
 331                                 result->req0       = reg->single_req;
 332                                 result->reg_offset = i;
 333                                 rbitset_clear(caller_saves, reg->global_index);
 334                                 ++n_reg_results;
 335                         }
 336                 }
 337         }
 338
 339         cconv                   = XMALLOCZ(calling_convention_t);
 340         cconv->parameters       = params;
 341         cconv->param_stack_size = stack_offset;
 342         cconv->n_param_regs     = n_param_regs_used;
 343         cconv->results          = results;
 344         cconv->omit_fp          = omit_fp;
 345         cconv->caller_saves     = caller_saves;
 346         cconv->n_reg_results    = n_reg_results;
 347
 348         /* setup ignore register array */
 349         if (irg != NULL) {
 350                 be_irg_t       *birg      = be_birg_from_irg(irg);
 351                 size_t          n_ignores = ARRAY_SIZE(ignore_regs);
 352                 struct obstack *obst      = &birg->obst;
 353                 size_t          r;
 354
 355                 birg->allocatable_regs = rbitset_obstack_alloc(obst, N_SPARC_REGISTERS);
 356                 rbitset_set_all(birg->allocatable_regs, N_SPARC_REGISTERS);
 357                 for (r = 0; r < n_ignores; ++r) {
 358                         rbitset_clear(birg->allocatable_regs, ignore_regs[r]);
 359                 }
 360         }
 361
 362         return cconv;
 363 }
 364
 365 void sparc_free_calling_convention(calling_convention_t *cconv)
 366 {
 367         free(cconv->parameters);
 368         free(cconv->results);
 369         free(cconv->caller_saves);
 370         free(cconv);
 371 }
 372
 373 void sparc_cconv_init(void)
 374 {
 375         size_t i;
 376         for (i = 0; i < ARRAY_SIZE(caller_saves); ++i) {
 377                 rbitset_set(default_caller_saves, caller_saves[i]);
 378         }
 379
 380         rbitset_set_all(default_returns_twice_saves, N_SPARC_REGISTERS);
 381         for (i = 0; i < ARRAY_SIZE(returns_twice_saved); ++i) {
 382                 rbitset_clear(default_returns_twice_saves, returns_twice_saved[i]);
 383         }
 384         for (i = 0; i < ARRAY_SIZE(ignore_regs); ++i) {
 385                 rbitset_clear(default_returns_twice_saves, ignore_regs[i]);
 386         }
 387
 388         for (i = 0; i < ARRAY_SIZE(float_result_reqs_double); i += 2) {
 389                 arch_register_req_t *req = &float_result_reqs_double[i];
 390                 *req = *float_result_regs[i]->single_req;
 391                 req->type |= arch_register_req_type_aligned;
 392                 req->width = 2;
 393         }
 394         for (i = 0; i < ARRAY_SIZE(float_result_reqs_quad); i += 4) {
 395                 arch_register_req_t *req = &float_result_reqs_quad[i];
 396                 *req = *float_result_regs[i]->single_req;
 397                 req->type |= arch_register_req_type_aligned;
 398                 req->width = 4;
 399         }
 400 }