nsz Git - libfirm/blob - ir/be/sparc/sparc_cconv.c

   1 /*
   2  * Copyright (C) 1995-2010 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief   calling convention helpers
  23  * @author  Matthias Braun
  24  * @version $Id$
  25  */
  26 #include "config.h"
  27
  28 #include "sparc_cconv.h"
  29 #include "irmode.h"
  30 #include "irgwalk.h"
  31 #include "typerep.h"
  32 #include "xmalloc.h"
  33 #include "util.h"
  34 #include "error.h"
  35 #include "gen_sparc_regalloc_if.h"
  36 #include "bitfiddle.h"
  37
  38 static const unsigned ignore_regs[] = {
  39         REG_G0,
  40         /* used in case an address offset does not fit into an immediate: */
  41         REG_G4,
  42         /* reserved for SPARC ABI: */
  43         REG_G5,
  44         REG_G6,
  45         REG_G7,
  46
  47         REG_SP,
  48         REG_O7,
  49         REG_FRAME_POINTER,
  50         REG_I7,
  51
  52         REG_FPFLAGS,
  53         REG_FLAGS,
  54         REG_Y,
  55 };
  56
  57 static const arch_register_t* const param_regs[] = {
  58         &sparc_registers[REG_I0],
  59         &sparc_registers[REG_I1],
  60         &sparc_registers[REG_I2],
  61         &sparc_registers[REG_I3],
  62         &sparc_registers[REG_I4],
  63         &sparc_registers[REG_I5],
  64 };
  65 COMPILETIME_ASSERT(ARRAY_SIZE(param_regs) == SPARC_N_PARAM_REGS, sparcparamregs)
  66
  67 static const arch_register_t* const float_result_regs[] = {
  68         &sparc_registers[REG_F0],
  69         &sparc_registers[REG_F1],
  70         &sparc_registers[REG_F2],
  71         &sparc_registers[REG_F3],
  72         &sparc_registers[REG_F4],
  73         &sparc_registers[REG_F5],
  74         &sparc_registers[REG_F6],
  75         &sparc_registers[REG_F7],
  76 };
  77 static arch_register_req_t float_result_reqs_double[8];
  78 static arch_register_req_t float_result_reqs_quad[8];
  79
  80 static const arch_register_t *const caller_saves[] = {
  81         &sparc_registers[REG_G1],
  82         &sparc_registers[REG_G2],
  83         &sparc_registers[REG_G3],
  84         &sparc_registers[REG_O0],
  85         &sparc_registers[REG_O1],
  86         &sparc_registers[REG_O2],
  87         &sparc_registers[REG_O3],
  88         &sparc_registers[REG_O4],
  89         &sparc_registers[REG_O5],
  90         &sparc_registers[REG_F0],
  91         &sparc_registers[REG_F1],
  92         &sparc_registers[REG_F2],
  93         &sparc_registers[REG_F3],
  94         &sparc_registers[REG_F4],
  95         &sparc_registers[REG_F5],
  96         &sparc_registers[REG_F6],
  97         &sparc_registers[REG_F7],
  98         &sparc_registers[REG_F8],
  99         &sparc_registers[REG_F9],
 100         &sparc_registers[REG_F10],
 101         &sparc_registers[REG_F11],
 102         &sparc_registers[REG_F12],
 103         &sparc_registers[REG_F13],
 104         &sparc_registers[REG_F14],
 105         &sparc_registers[REG_F15],
 106         &sparc_registers[REG_F16],
 107         &sparc_registers[REG_F17],
 108         &sparc_registers[REG_F18],
 109         &sparc_registers[REG_F19],
 110         &sparc_registers[REG_F20],
 111         &sparc_registers[REG_F21],
 112         &sparc_registers[REG_F22],
 113         &sparc_registers[REG_F23],
 114         &sparc_registers[REG_F24],
 115         &sparc_registers[REG_F25],
 116         &sparc_registers[REG_F26],
 117         &sparc_registers[REG_F27],
 118         &sparc_registers[REG_F28],
 119         &sparc_registers[REG_F29],
 120         &sparc_registers[REG_F30],
 121         &sparc_registers[REG_F31],
 122 };
 123 static unsigned default_caller_saves[BITSET_SIZE_ELEMS(N_SPARC_REGISTERS)];
 124
 125 /**
 126  * Maps an input register representing the i'th register input
 127  * to the i'th register output.
 128  */
 129 static const arch_register_t *map_i_to_o_reg(const arch_register_t *reg)
 130 {
 131         unsigned idx = reg->global_index;
 132         assert(REG_I0 <= idx && idx <= REG_I7);
 133         idx += REG_O0 - REG_I0;
 134         assert(REG_O0 <= idx && idx <= REG_O7);
 135         return &sparc_registers[idx];
 136 }
 137
 138 static void check_omit_fp(ir_node *node, void *env)
 139 {
 140         bool *can_omit_fp = (bool*) env;
 141
 142         /* omit-fp is not possible if:
 143          *  - we have allocations on the stack
 144          *  - we have calls (with the exception of tail-calls once we support them)
 145          */
 146         if ((is_Alloc(node) && get_Alloc_where(node) == stack_alloc)
 147                         || (is_Free(node) && get_Free_where(node) == stack_alloc)
 148                         || is_Call(node)) {
 149                 *can_omit_fp = false;
 150         }
 151 }
 152
 153 static unsigned determine_n_float_regs(ir_mode *mode)
 154 {
 155         unsigned bits = get_mode_size_bits(mode);
 156         switch (bits) {
 157         case 32:
 158                 return 1;
 159         case 64:
 160                 return 2;
 161         case 128:
 162                 return 4;
 163         default:
 164                 panic("sparc: Unexpected floatingpoint mode %+F", mode);
 165         }
 166 }
 167
 168 calling_convention_t *sparc_decide_calling_convention(ir_type *function_type,
 169                                                       ir_graph *irg)
 170 {
 171         unsigned              stack_offset        = 0;
 172         unsigned              n_param_regs_used   = 0;
 173         int                   n_param_regs        = ARRAY_SIZE(param_regs);
 174         unsigned              n_float_result_regs = ARRAY_SIZE(float_result_regs);
 175         bool                  omit_fp             = false;
 176         reg_or_stackslot_t   *params;
 177         reg_or_stackslot_t   *results;
 178         int                   n_params;
 179         int                   n_results;
 180         int                   i;
 181         int                   regnum;
 182         unsigned              float_regnum;
 183         unsigned              n_reg_results = 0;
 184         calling_convention_t *cconv;
 185         unsigned             *caller_saves;
 186
 187         if (irg != NULL) {
 188                 const be_options_t *options = be_get_irg_options(irg);
 189                 omit_fp = options->omit_fp;
 190                 irg_walk_graph(irg, check_omit_fp, NULL, &omit_fp);
 191         }
 192
 193         caller_saves = rbitset_malloc(N_SPARC_REGISTERS);
 194         rbitset_copy(caller_saves, default_caller_saves, N_SPARC_REGISTERS);
 195
 196         /* determine how parameters are passed */
 197         n_params = get_method_n_params(function_type);
 198         regnum   = 0;
 199         params   = XMALLOCNZ(reg_or_stackslot_t, n_params);
 200
 201         for (i = 0; i < n_params; ++i) {
 202                 ir_type            *param_type = get_method_param_type(function_type,i);
 203                 ir_mode            *mode;
 204                 int                 bits;
 205                 reg_or_stackslot_t *param;
 206
 207                 if (is_compound_type(param_type))
 208                         panic("sparc: compound arguments not supported yet");
 209
 210                 mode  = get_type_mode(param_type);
 211                 bits  = get_mode_size_bits(mode);
 212                 param = &params[i];
 213
 214                 if (i == 0 &&
 215                     (get_method_calling_convention(function_type) & cc_compound_ret)) {
 216                         assert(mode_is_reference(mode) && bits == 32);
 217                         /* special case, we have reserved space for this on the between
 218                          * type */
 219                         param->type   = param_type;
 220                         param->offset = -SPARC_MIN_STACKSIZE+SPARC_AGGREGATE_RETURN_OFFSET;
 221                         continue;
 222                 }
 223
 224                 if (regnum < n_param_regs) {
 225                         const arch_register_t *reg = param_regs[regnum];
 226                         if (irg == NULL || omit_fp)
 227                                 reg = map_i_to_o_reg(reg);
 228                         param->reg0       = reg;
 229                         param->req0       = reg->single_req;
 230                         param->reg_offset = regnum;
 231                         ++regnum;
 232                 } else {
 233                         param->type   = param_type;
 234                         param->offset = stack_offset;
 235                         /* increase offset 4 bytes so everything is aligned */
 236                         stack_offset += bits > 32 ? bits/8 : 4;
 237                         continue;
 238                 }
 239
 240                 /* we might need a 2nd 32bit component (for 64bit or double values) */
 241                 if (bits > 32) {
 242                         if (bits > 64)
 243                                 panic("only 32 and 64bit modes supported in sparc backend");
 244
 245                         if (regnum < n_param_regs) {
 246                                 const arch_register_t *reg = param_regs[regnum];
 247                                 if (irg == NULL || omit_fp)
 248                                         reg = map_i_to_o_reg(reg);
 249                                 param->reg1       = reg;
 250                                 param->req1       = reg->single_req;
 251                                 ++regnum;
 252                         } else {
 253                                 ir_mode *regmode = param_regs[0]->reg_class->mode;
 254                                 ir_type *type    = get_type_for_mode(regmode);
 255                                 param->type      = type;
 256                                 param->offset    = stack_offset;
 257                                 assert(get_mode_size_bits(regmode) == 32);
 258                                 stack_offset += 4;
 259                         }
 260                 }
 261         }
 262         n_param_regs_used = regnum;
 263
 264         /* determine how results are passed */
 265         n_results    = get_method_n_ress(function_type);
 266         regnum       = 0;
 267         float_regnum = 0;
 268         results      = XMALLOCNZ(reg_or_stackslot_t, n_results);
 269         for (i = 0; i < n_results; ++i) {
 270                 ir_type            *result_type = get_method_res_type(function_type, i);
 271                 ir_mode            *result_mode = get_type_mode(result_type);
 272                 reg_or_stackslot_t *result      = &results[i];
 273
 274                 if (mode_is_float(result_mode)) {
 275                         unsigned n_regs   = determine_n_float_regs(result_mode);
 276                         unsigned next_reg = round_up2(float_regnum, n_regs);
 277
 278                         if (next_reg >= n_float_result_regs) {
 279                                 panic("Too many float results for sparc backend");
 280                         } else {
 281                                 const arch_register_t *reg = float_result_regs[next_reg];
 282                                 rbitset_clear(caller_saves, reg->global_index);
 283                                 result->reg_offset = i;
 284                                 if (n_regs == 1) {
 285                                         result->req0 = reg->single_req;
 286                                 } else if (n_regs == 2) {
 287                                         result->req0 = &float_result_reqs_double[next_reg];
 288                                         rbitset_clear(caller_saves, reg->global_index+1);
 289                                 } else if (n_regs == 4) {
 290                                         result->req0 = &float_result_reqs_quad[next_reg];
 291                                         rbitset_clear(caller_saves, reg->global_index+1);
 292                                         rbitset_clear(caller_saves, reg->global_index+2);
 293                                         rbitset_clear(caller_saves, reg->global_index+3);
 294                                 } else {
 295                                         panic("invalid number of registers in sparc float result");
 296                                 }
 297                                 float_regnum = next_reg + n_regs;
 298
 299                                 ++n_reg_results;
 300                         }
 301                 } else {
 302                         if (get_mode_size_bits(result_mode) > 32) {
 303                                 panic("Results with more than 32bits not supported by sparc backend yet");
 304                         }
 305
 306                         if (regnum >= n_param_regs) {
 307                                 panic("Too many results for sparc backend");
 308                         } else {
 309                                 const arch_register_t *reg = param_regs[regnum++];
 310                                 if (irg == NULL || omit_fp)
 311                                         reg = map_i_to_o_reg(reg);
 312                                 result->req0       = reg->single_req;
 313                                 result->reg_offset = i;
 314                                 rbitset_clear(caller_saves, reg->global_index);
 315                                 ++n_reg_results;
 316                         }
 317                 }
 318         }
 319
 320         cconv                   = XMALLOCZ(calling_convention_t);
 321         cconv->parameters       = params;
 322         cconv->param_stack_size = stack_offset;
 323         cconv->n_param_regs     = n_param_regs_used;
 324         cconv->results          = results;
 325         cconv->omit_fp          = omit_fp;
 326         cconv->caller_saves     = caller_saves;
 327         cconv->n_reg_results    = n_reg_results;
 328
 329         /* setup ignore register array */
 330         if (irg != NULL) {
 331                 be_irg_t       *birg      = be_birg_from_irg(irg);
 332                 size_t          n_ignores = ARRAY_SIZE(ignore_regs);
 333                 struct obstack *obst      = &birg->obst;
 334                 size_t          r;
 335
 336                 birg->allocatable_regs = rbitset_obstack_alloc(obst, N_SPARC_REGISTERS);
 337                 rbitset_set_all(birg->allocatable_regs, N_SPARC_REGISTERS);
 338                 for (r = 0; r < n_ignores; ++r) {
 339                         rbitset_clear(birg->allocatable_regs, ignore_regs[r]);
 340                 }
 341         }
 342
 343         return cconv;
 344 }
 345
 346 void sparc_free_calling_convention(calling_convention_t *cconv)
 347 {
 348         free(cconv->parameters);
 349         free(cconv->results);
 350         free(cconv->caller_saves);
 351         free(cconv);
 352 }
 353
 354 void sparc_cconv_init(void)
 355 {
 356         size_t i;
 357         for (i = 0; i < ARRAY_SIZE(caller_saves); ++i) {
 358                 rbitset_set(default_caller_saves, caller_saves[i]->global_index);
 359         }
 360
 361         for (i = 0; i < ARRAY_SIZE(float_result_reqs_double); i += 2) {
 362                 arch_register_req_t *req = &float_result_reqs_double[i];
 363                 *req = *float_result_regs[i]->single_req;
 364                 req->type |= arch_register_req_type_aligned;
 365                 req->width = 2;
 366         }
 367         for (i = 0; i < ARRAY_SIZE(float_result_reqs_quad); i += 4) {
 368                 arch_register_req_t *req = &float_result_reqs_quad[i];
 369                 *req = *float_result_regs[i]->single_req;
 370                 req->type |= arch_register_req_type_aligned;
 371                 req->width = 4;
 372         }
 373 }