2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main sparc backend driver file.
23 * @author Hannes Rapp, Matthias Braun
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
42 #include "lower_alloc.h"
43 #include "lower_builtins.h"
44 #include "lower_calls.h"
45 #include "lower_softfloat.h"
53 #include "../bearch.h"
54 #include "../benode.h"
55 #include "../belower.h"
56 #include "../besched.h"
58 #include "../bemachine.h"
59 #include "../bemodule.h"
61 #include "../begnuas.h"
62 #include "../belistsched.h"
63 #include "../beflags.h"
64 #include "../beutil.h"
66 #include "bearch_sparc_t.h"
68 #include "sparc_new_nodes.h"
69 #include "gen_sparc_regalloc_if.h"
70 #include "sparc_transform.h"
71 #include "sparc_emitter.h"
72 #include "sparc_cconv.h"
74 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
76 static arch_irn_class_t sparc_classify(const ir_node *node)
79 return arch_irn_class_none;
82 static ir_entity *sparc_get_frame_entity(const ir_node *node)
84 if (is_sparc_FrameAddr(node)) {
85 const sparc_attr_t *attr = get_sparc_attr_const(node);
86 return attr->immediate_value_entity;
89 if (sparc_has_load_store_attr(node)) {
90 const sparc_load_store_attr_t *load_store_attr
91 = get_sparc_load_store_attr_const(node);
92 if (load_store_attr->is_frame_entity) {
93 return load_store_attr->base.immediate_value_entity;
101 * This function is called by the generic backend to correct offsets for
102 * nodes accessing the stack.
104 static void sparc_set_frame_offset(ir_node *node, int offset)
106 sparc_attr_t *attr = get_sparc_attr(node);
107 attr->immediate_value += offset;
109 /* must be a FrameAddr or a load/store node with frame_entity */
110 assert(is_sparc_FrameAddr(node) ||
111 get_sparc_load_store_attr_const(node)->is_frame_entity);
114 static int sparc_get_sp_bias(const ir_node *node)
116 if (is_sparc_Save(node)) {
117 const sparc_attr_t *attr = get_sparc_attr_const(node);
118 if (get_irn_arity(node) == 3)
119 panic("no support for _reg variant yet");
121 return -attr->immediate_value;
122 } else if (is_sparc_RestoreZero(node)) {
123 return SP_BIAS_RESET;
128 /* fill register allocator interface */
130 const arch_irn_ops_t sparc_irn_ops = {
132 sparc_get_frame_entity,
133 sparc_set_frame_offset,
135 NULL, /* get_inverse */
136 NULL, /* get_op_estimated_cost */
137 NULL, /* possible_memory_operand */
138 NULL, /* perform_memory_operand */
142 * Transforms the standard firm graph into
145 static void sparc_prepare_graph(ir_graph *irg)
147 sparc_transform_graph(irg);
150 static bool sparc_modifies_flags(const ir_node *node)
152 return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_flags;
155 static bool sparc_modifies_fp_flags(const ir_node *node)
157 return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_fp_flags;
160 static void sparc_before_ra(ir_graph *irg)
162 /* fixup flags register */
163 be_sched_fix_flags(irg, &sparc_reg_classes[CLASS_sparc_flags_class],
164 NULL, sparc_modifies_flags);
165 be_sched_fix_flags(irg, &sparc_reg_classes[CLASS_sparc_fpflags_class],
166 NULL, sparc_modifies_fp_flags);
169 static void sparc_init_graph(ir_graph *irg)
174 extern const arch_isa_if_t sparc_isa_if;
175 static sparc_isa_t sparc_isa_template = {
177 &sparc_isa_if, /* isa interface implementation */
182 &sparc_registers[REG_SP], /* stack pointer register */
183 &sparc_registers[REG_FRAME_POINTER],/* base pointer register */
184 &sparc_reg_classes[CLASS_sparc_gp], /* link pointer register class */
185 3, /* power of two stack alignment
187 NULL, /* main environment */
188 7, /* costs for a spill instruction */
189 5, /* costs for a reload instruction */
190 true, /* custom abi handling */
192 NULL, /* constants */
193 SPARC_FPU_ARCH_FPU, /* FPU architecture */
197 * rewrite unsigned->float conversion.
198 * Sparc has no instruction for this so instead we do the following:
200 * int signed_x = unsigned_value_x;
201 * double res = signed_x;
203 * res += 4294967296. ;
204 * return (float) res;
206 static void rewrite_unsigned_float_Conv(ir_node *node)
208 ir_graph *irg = get_irn_irg(node);
209 dbg_info *dbgi = get_irn_dbg_info(node);
210 ir_node *lower_block = get_nodes_block(node);
215 ir_node *block = get_nodes_block(node);
216 ir_node *unsigned_x = get_Conv_op(node);
217 ir_mode *mode_u = get_irn_mode(unsigned_x);
218 ir_mode *mode_s = find_signed_mode(mode_u);
219 ir_mode *mode_d = mode_D;
220 ir_node *signed_x = new_rd_Conv(dbgi, block, unsigned_x, mode_s);
221 ir_node *res = new_rd_Conv(dbgi, block, signed_x, mode_d);
222 ir_node *zero = new_r_Const(irg, get_mode_null(mode_s));
223 ir_node *cmp = new_rd_Cmp(dbgi, block, signed_x, zero,
225 ir_node *cond = new_rd_Cond(dbgi, block, cmp);
226 ir_node *proj_true = new_r_Proj(cond, mode_X, pn_Cond_true);
227 ir_node *proj_false = new_r_Proj(cond, mode_X, pn_Cond_false);
228 ir_node *in_true[1] = { proj_true };
229 ir_node *in_false[1] = { proj_false };
230 ir_node *true_block = new_r_Block(irg, ARRAY_SIZE(in_true), in_true);
231 ir_node *false_block = new_r_Block(irg, ARRAY_SIZE(in_false),in_false);
232 ir_node *true_jmp = new_r_Jmp(true_block);
233 ir_node *false_jmp = new_r_Jmp(false_block);
234 ir_tarval *correction = new_tarval_from_double(4294967296., mode_d);
235 ir_node *c_const = new_r_Const(irg, correction);
236 ir_node *fadd = new_rd_Add(dbgi, true_block, res, c_const,
239 ir_node *lower_in[2] = { true_jmp, false_jmp };
240 ir_node *phi_in[2] = { fadd, res };
241 ir_mode *dest_mode = get_irn_mode(node);
245 set_irn_in(lower_block, ARRAY_SIZE(lower_in), lower_in);
246 phi = new_r_Phi(lower_block, ARRAY_SIZE(phi_in), phi_in, mode_d);
247 assert(get_Block_phis(lower_block) == NULL);
248 set_Block_phis(lower_block, phi);
249 set_Phi_next(phi, NULL);
251 res_conv = new_rd_Conv(dbgi, lower_block, phi, dest_mode);
253 exchange(node, res_conv);
257 static int sparc_rewrite_Conv(ir_node *node, void *ctx)
259 ir_mode *to_mode = get_irn_mode(node);
260 ir_node *op = get_Conv_op(node);
261 ir_mode *from_mode = get_irn_mode(op);
264 if (mode_is_float(to_mode) && mode_is_int(from_mode)
265 && get_mode_size_bits(from_mode) == 32
266 && !mode_is_signed(from_mode)) {
267 rewrite_unsigned_float_Conv(node);
274 static void sparc_handle_intrinsics(void)
276 ir_type *tp, *int_tp, *uint_tp;
278 size_t n_records = 0;
280 runtime_rt rt_iMod, rt_uMod;
282 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
284 int_tp = new_type_primitive(mode_Is);
285 uint_tp = new_type_primitive(mode_Iu);
287 /* we need to rewrite some forms of int->float conversions */
289 i_instr_record *map_Conv = &records[n_records++].i_instr;
291 map_Conv->kind = INTRINSIC_INSTR;
292 map_Conv->op = op_Conv;
293 map_Conv->i_mapper = sparc_rewrite_Conv;
295 /* SPARC has no signed mod instruction ... */
297 i_instr_record *map_Mod = &records[n_records++].i_instr;
299 tp = new_type_method(2, 1);
300 set_method_param_type(tp, 0, int_tp);
301 set_method_param_type(tp, 1, int_tp);
302 set_method_res_type(tp, 0, int_tp);
304 rt_iMod.ent = new_entity(get_glob_type(), ID(".rem"), tp);
305 set_entity_ld_ident(rt_iMod.ent, ID(".rem"));
306 rt_iMod.mode = mode_T;
307 rt_iMod.res_mode = mode_Is;
308 rt_iMod.mem_proj_nr = pn_Mod_M;
309 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
310 rt_iMod.exc_proj_nr = pn_Mod_X_except;
311 rt_iMod.res_proj_nr = pn_Mod_res;
313 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
315 map_Mod->kind = INTRINSIC_INSTR;
316 map_Mod->op = op_Mod;
317 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
318 map_Mod->ctx = &rt_iMod;
320 /* ... nor an unsigned mod. */
322 i_instr_record *map_Mod = &records[n_records++].i_instr;
324 tp = new_type_method(2, 1);
325 set_method_param_type(tp, 0, uint_tp);
326 set_method_param_type(tp, 1, uint_tp);
327 set_method_res_type(tp, 0, uint_tp);
329 rt_uMod.ent = new_entity(get_glob_type(), ID(".urem"), tp);
330 set_entity_ld_ident(rt_uMod.ent, ID(".urem"));
331 rt_uMod.mode = mode_T;
332 rt_uMod.res_mode = mode_Iu;
333 rt_uMod.mem_proj_nr = pn_Mod_M;
334 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
335 rt_uMod.exc_proj_nr = pn_Mod_X_except;
336 rt_uMod.res_proj_nr = pn_Mod_res;
338 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
340 map_Mod->kind = INTRINSIC_INSTR;
341 map_Mod->op = op_Mod;
342 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
343 map_Mod->ctx = &rt_uMod;
346 assert(n_records < ARRAY_SIZE(records));
347 lower_intrinsics(records, n_records, /*part_block_used=*/ true);
351 * Initializes the backend ISA
353 static arch_env_t *sparc_init(FILE *outfile)
355 sparc_isa_t *isa = XMALLOC(sparc_isa_t);
356 *isa = sparc_isa_template;
357 isa->constants = pmap_create();
359 be_gas_elf_type_char = '#';
360 be_gas_object_file_format = OBJECT_FILE_FORMAT_ELF_SPARC;
362 be_emit_init(outfile);
364 sparc_register_init();
365 sparc_create_opcodes(&sparc_irn_ops);
366 sparc_handle_intrinsics();
373 * Closes the output file and frees the ISA structure.
375 static void sparc_done(void *self)
377 sparc_isa_t *isa = (sparc_isa_t*)self;
379 /* emit now all global declarations */
380 be_gas_emit_decls(isa->base.main_env);
382 pmap_destroy(isa->constants);
389 * Get the register class which shall be used to store a value of a given mode.
390 * @param self The this pointer.
391 * @param mode The mode in question.
392 * @return A register class which can hold values of the given mode.
394 static const arch_register_class_t *sparc_get_reg_class_for_mode(const ir_mode *mode)
396 if (mode_is_float(mode))
397 return &sparc_reg_classes[CLASS_sparc_fp];
399 return &sparc_reg_classes[CLASS_sparc_gp];
403 * Returns the necessary byte alignment for storing a register of given class.
405 static int sparc_get_reg_class_alignment(const arch_register_class_t *cls)
407 ir_mode *mode = arch_register_class_mode(cls);
408 return get_mode_size_bytes(mode);
411 static ir_node *sparc_create_set(ir_node *cond)
413 return ir_create_cond_set(cond, mode_Iu);
416 static void sparc_lower_for_target(void)
418 size_t i, n_irgs = get_irp_n_irgs();
419 lower_mode_b_config_t lower_mode_b_config = {
425 lower_calls_with_compounds(LF_RETURN_HIDDEN);
427 if (sparc_isa_template.fpu_arch == SPARC_FPU_ARCH_SOFTFLOAT)
428 lower_floating_point();
430 lower_builtins(0, NULL);
434 for (i = 0; i < n_irgs; ++i) {
435 ir_graph *irg = get_irp_irg(i);
436 ir_lower_mode_b(irg, &lower_mode_b_config);
437 lower_switch(irg, 4, 256, false);
438 lower_alloc(irg, SPARC_STACK_ALIGNMENT, false, -SPARC_MIN_STACKSIZE);
441 for (i = 0; i < n_irgs; ++i) {
442 ir_graph *irg = get_irp_irg(i);
443 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
445 lower_CopyB(irg, 31, 32);
449 static int sparc_is_mux_allowed(ir_node *sel, ir_node *mux_false,
452 ir_graph *irg = get_irn_irg(sel);
453 ir_mode *mode = get_irn_mode(mux_true);
455 if (get_irg_phase_state(irg) == phase_low)
458 if (!mode_is_int(mode) && !mode_is_reference(mode) && mode != mode_b)
460 if (is_Const(mux_true) && is_Const_one(mux_true) &&
461 is_Const(mux_false) && is_Const_null(mux_false))
467 * Returns the libFirm configuration parameter for this backend.
469 static const backend_params *sparc_get_backend_params(void)
471 static const ir_settings_arch_dep_t arch_dep = {
472 1, /* also_use_subs */
473 1, /* maximum_shifts */
474 31, /* highest_shift_amount */
475 NULL, /* evaluate_cost_func */
478 32, /* max_bits_for_mulh */
480 static backend_params p = {
481 0, /* no inline assembly */
482 0, /* no support for RotL nodes */
484 1, /* modulo shift efficient */
485 0, /* non-modulo shift not efficient */
486 &arch_dep, /* will be set later */
487 sparc_is_mux_allowed, /* parameter for if conversion */
488 32, /* machine size */
489 NULL, /* float arithmetic mode */
490 NULL, /* long long type */
491 NULL, /* usigned long long type */
492 NULL, /* long double type */
493 0, /* no trampoline support: size 0 */
494 0, /* no trampoline support: align 0 */
495 NULL, /* no trampoline support: no trampoline builder */
496 4 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
499 ir_mode *mode_long_long
500 = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement,
502 ir_type *type_long_long = new_type_primitive(mode_long_long);
503 ir_mode *mode_unsigned_long_long
504 = new_ir_mode("unsigned long long", irms_int_number, 64, 0,
505 irma_twos_complement, 64);
506 ir_type *type_unsigned_long_long
507 = new_type_primitive(mode_unsigned_long_long);
508 ir_mode *mode_long_double
509 = new_ir_mode("long double", irms_float_number, 128, 1,
511 ir_type *type_long_double = new_type_primitive(mode_long_double);
513 set_type_alignment_bytes(type_long_double, 8);
514 p.type_long_double = type_long_double;
515 p.type_long_long = type_long_long;
516 p.type_unsigned_long_long = type_unsigned_long_long;
520 static ir_graph **sparc_get_backend_irg_list(const void *self,
528 static asm_constraint_flags_t sparc_parse_asm_constraint(const char **c)
531 return ASM_CONSTRAINT_FLAG_INVALID;
534 static int sparc_is_valid_clobber(const char *clobber)
540 /* fpu set architectures. */
541 static const lc_opt_enum_int_items_t sparc_fpu_items[] = {
542 { "fpu", SPARC_FPU_ARCH_FPU },
543 { "softfloat", SPARC_FPU_ARCH_SOFTFLOAT },
547 static lc_opt_enum_int_var_t arch_fpu_var = {
548 &sparc_isa_template.fpu_arch, sparc_fpu_items
551 static const lc_opt_table_entry_t sparc_options[] = {
552 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
556 static ir_node *sparc_new_spill(ir_node *value, ir_node *after)
558 ir_node *block = get_block(after);
559 ir_graph *irg = get_irn_irg(value);
560 ir_node *frame = get_irg_frame(irg);
561 ir_node *mem = get_irg_no_mem(irg);
562 ir_mode *mode = get_irn_mode(value);
565 if (mode_is_float(mode)) {
566 store = create_stf(NULL, block, value, frame, mem, mode, NULL, 0, true);
568 store = new_bd_sparc_St_imm(NULL, block, value, frame, mem, mode, NULL,
571 sched_add_after(after, store);
575 static ir_node *sparc_new_reload(ir_node *value, ir_node *spill,
578 ir_node *block = get_block(before);
579 ir_graph *irg = get_irn_irg(value);
580 ir_node *frame = get_irg_frame(irg);
581 ir_mode *mode = get_irn_mode(value);
585 if (mode_is_float(mode)) {
586 load = create_ldf(NULL, block, frame, spill, mode, NULL, 0, true);
588 load = new_bd_sparc_Ld_imm(NULL, block, frame, spill, mode, NULL, 0,
591 sched_add_before(before, load);
592 assert((long)pn_sparc_Ld_res == (long)pn_sparc_Ldf_res);
593 res = new_r_Proj(load, mode, pn_sparc_Ld_res);
598 const arch_isa_if_t sparc_isa_if = {
600 sparc_lower_for_target,
602 NULL, /* handle intrinsics */
603 sparc_get_reg_class_for_mode,
605 sparc_get_reg_class_alignment,
606 sparc_get_backend_params,
607 sparc_get_backend_irg_list,
608 NULL, /* mark remat */
609 sparc_parse_asm_constraint,
610 sparc_is_valid_clobber,
613 NULL, /* get_pic_base */
614 NULL, /* before_abi */
619 NULL, /* register_saved_by */
624 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_sparc)
625 void be_init_arch_sparc(void)
627 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
628 lc_opt_entry_t *sparc_grp = lc_opt_get_grp(be_grp, "sparc");
630 lc_opt_add_table(sparc_grp, sparc_options);
632 be_register_isa_if("sparc", &sparc_isa_if);
633 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.cg");
634 sparc_init_transform();
635 sparc_init_emitter();