2 * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main sparc backend driver file.
23 * @author Hannes Rapp, Matthias Braun
29 #include "lc_opts_enum.h"
37 #include "iroptimize.h"
43 #include "lower_alloc.h"
44 #include "lower_builtins.h"
45 #include "lower_calls.h"
46 #include "lower_mode_b.h"
47 #include "lower_softfloat.h"
55 #include "../bearch.h"
56 #include "../benode.h"
57 #include "../belower.h"
58 #include "../besched.h"
60 #include "../bemachine.h"
61 #include "../bemodule.h"
63 #include "../begnuas.h"
64 #include "../belistsched.h"
65 #include "../beflags.h"
66 #include "../beutil.h"
68 #include "bearch_sparc_t.h"
70 #include "sparc_new_nodes.h"
71 #include "gen_sparc_regalloc_if.h"
72 #include "sparc_transform.h"
73 #include "sparc_emitter.h"
74 #include "sparc_cconv.h"
76 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
78 static arch_irn_class_t sparc_classify(const ir_node *node)
81 return arch_irn_class_none;
84 static ir_entity *sparc_get_frame_entity(const ir_node *node)
86 if (is_sparc_FrameAddr(node)) {
87 const sparc_attr_t *attr = get_sparc_attr_const(node);
88 return attr->immediate_value_entity;
91 if (sparc_has_load_store_attr(node)) {
92 const sparc_load_store_attr_t *load_store_attr
93 = get_sparc_load_store_attr_const(node);
94 if (load_store_attr->is_frame_entity) {
95 return load_store_attr->base.immediate_value_entity;
103 * This function is called by the generic backend to correct offsets for
104 * nodes accessing the stack.
106 static void sparc_set_frame_offset(ir_node *node, int offset)
108 sparc_attr_t *attr = get_sparc_attr(node);
109 attr->immediate_value += offset;
111 /* must be a FrameAddr or a load/store node with frame_entity */
112 assert(is_sparc_FrameAddr(node) ||
113 get_sparc_load_store_attr_const(node)->is_frame_entity);
116 static int sparc_get_sp_bias(const ir_node *node)
118 if (is_sparc_Save(node)) {
119 const sparc_attr_t *attr = get_sparc_attr_const(node);
120 if (get_irn_arity(node) == 3)
121 panic("no support for _reg variant yet");
123 return -attr->immediate_value;
124 } else if (is_sparc_RestoreZero(node)) {
125 return SP_BIAS_RESET;
130 /* fill register allocator interface */
132 const arch_irn_ops_t sparc_irn_ops = {
134 sparc_get_frame_entity,
135 sparc_set_frame_offset,
137 NULL, /* get_inverse */
138 NULL, /* get_op_estimated_cost */
139 NULL, /* possible_memory_operand */
140 NULL, /* perform_memory_operand */
144 * Transforms the standard firm graph into
147 static void sparc_prepare_graph(ir_graph *irg)
149 sparc_transform_graph(irg);
152 static bool sparc_modifies_flags(const ir_node *node)
154 return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_flags;
157 static bool sparc_modifies_fp_flags(const ir_node *node)
159 return arch_get_irn_flags(node) & sparc_arch_irn_flag_modifies_fp_flags;
162 static void sparc_before_ra(ir_graph *irg)
164 /* fixup flags register */
165 be_sched_fix_flags(irg, &sparc_reg_classes[CLASS_sparc_flags_class],
166 NULL, sparc_modifies_flags);
167 be_sched_fix_flags(irg, &sparc_reg_classes[CLASS_sparc_fpflags_class],
168 NULL, sparc_modifies_fp_flags);
171 static void sparc_init_graph(ir_graph *irg)
176 extern const arch_isa_if_t sparc_isa_if;
177 static sparc_isa_t sparc_isa_template = {
179 &sparc_isa_if, /* isa interface implementation */
184 &sparc_registers[REG_SP], /* stack pointer register */
185 &sparc_registers[REG_FRAME_POINTER],/* base pointer register */
186 &sparc_reg_classes[CLASS_sparc_gp], /* link pointer register class */
187 3, /* power of two stack alignment
189 NULL, /* main environment */
190 7, /* costs for a spill instruction */
191 5, /* costs for a reload instruction */
192 true, /* custom abi handling */
194 NULL, /* constants */
195 SPARC_FPU_ARCH_FPU, /* FPU architecture */
199 * rewrite unsigned->float conversion.
200 * Sparc has no instruction for this so instead we do the following:
202 * int signed_x = unsigned_value_x;
203 * double res = signed_x;
205 * res += 4294967296. ;
206 * return (float) res;
208 static void rewrite_unsigned_float_Conv(ir_node *node)
210 ir_graph *irg = get_irn_irg(node);
211 dbg_info *dbgi = get_irn_dbg_info(node);
212 ir_node *lower_block = get_nodes_block(node);
217 ir_node *block = get_nodes_block(node);
218 ir_node *unsigned_x = get_Conv_op(node);
219 ir_mode *mode_u = get_irn_mode(unsigned_x);
220 ir_mode *mode_s = find_signed_mode(mode_u);
221 ir_mode *mode_d = mode_D;
222 ir_node *signed_x = new_rd_Conv(dbgi, block, unsigned_x, mode_s);
223 ir_node *res = new_rd_Conv(dbgi, block, signed_x, mode_d);
224 ir_node *zero = new_r_Const(irg, get_mode_null(mode_s));
225 ir_node *cmp = new_rd_Cmp(dbgi, block, signed_x, zero,
227 ir_node *cond = new_rd_Cond(dbgi, block, cmp);
228 ir_node *proj_true = new_r_Proj(cond, mode_X, pn_Cond_true);
229 ir_node *proj_false = new_r_Proj(cond, mode_X, pn_Cond_false);
230 ir_node *in_true[1] = { proj_true };
231 ir_node *in_false[1] = { proj_false };
232 ir_node *true_block = new_r_Block(irg, ARRAY_SIZE(in_true), in_true);
233 ir_node *false_block = new_r_Block(irg, ARRAY_SIZE(in_false),in_false);
234 ir_node *true_jmp = new_r_Jmp(true_block);
235 ir_node *false_jmp = new_r_Jmp(false_block);
236 ir_tarval *correction = new_tarval_from_double(4294967296., mode_d);
237 ir_node *c_const = new_r_Const(irg, correction);
238 ir_node *fadd = new_rd_Add(dbgi, true_block, res, c_const,
241 ir_node *lower_in[2] = { true_jmp, false_jmp };
242 ir_node *phi_in[2] = { fadd, res };
243 ir_mode *dest_mode = get_irn_mode(node);
247 set_irn_in(lower_block, ARRAY_SIZE(lower_in), lower_in);
248 phi = new_r_Phi(lower_block, ARRAY_SIZE(phi_in), phi_in, mode_d);
249 assert(get_Block_phis(lower_block) == NULL);
250 set_Block_phis(lower_block, phi);
251 set_Phi_next(phi, NULL);
253 res_conv = new_rd_Conv(dbgi, lower_block, phi, dest_mode);
255 exchange(node, res_conv);
259 static int sparc_rewrite_Conv(ir_node *node, void *ctx)
261 ir_mode *to_mode = get_irn_mode(node);
262 ir_node *op = get_Conv_op(node);
263 ir_mode *from_mode = get_irn_mode(op);
266 if (mode_is_float(to_mode) && mode_is_int(from_mode)
267 && get_mode_size_bits(from_mode) == 32
268 && !mode_is_signed(from_mode)) {
269 rewrite_unsigned_float_Conv(node);
276 static void sparc_handle_intrinsics(void)
278 ir_type *tp, *int_tp, *uint_tp;
280 size_t n_records = 0;
282 runtime_rt rt_iMod, rt_uMod;
284 #define ID(x) new_id_from_chars(x, sizeof(x)-1)
286 int_tp = new_type_primitive(mode_Is);
287 uint_tp = new_type_primitive(mode_Iu);
289 /* we need to rewrite some forms of int->float conversions */
291 i_instr_record *map_Conv = &records[n_records++].i_instr;
293 map_Conv->kind = INTRINSIC_INSTR;
294 map_Conv->op = op_Conv;
295 map_Conv->i_mapper = sparc_rewrite_Conv;
297 /* SPARC has no signed mod instruction ... */
299 i_instr_record *map_Mod = &records[n_records++].i_instr;
301 tp = new_type_method(2, 1);
302 set_method_param_type(tp, 0, int_tp);
303 set_method_param_type(tp, 1, int_tp);
304 set_method_res_type(tp, 0, int_tp);
306 rt_iMod.ent = new_entity(get_glob_type(), ID(".rem"), tp);
307 set_entity_ld_ident(rt_iMod.ent, ID(".rem"));
308 rt_iMod.mode = mode_T;
309 rt_iMod.res_mode = mode_Is;
310 rt_iMod.mem_proj_nr = pn_Mod_M;
311 rt_iMod.regular_proj_nr = pn_Mod_X_regular;
312 rt_iMod.exc_proj_nr = pn_Mod_X_except;
313 rt_iMod.res_proj_nr = pn_Mod_res;
315 set_entity_visibility(rt_iMod.ent, ir_visibility_external);
317 map_Mod->kind = INTRINSIC_INSTR;
318 map_Mod->op = op_Mod;
319 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
320 map_Mod->ctx = &rt_iMod;
322 /* ... nor an unsigned mod. */
324 i_instr_record *map_Mod = &records[n_records++].i_instr;
326 tp = new_type_method(2, 1);
327 set_method_param_type(tp, 0, uint_tp);
328 set_method_param_type(tp, 1, uint_tp);
329 set_method_res_type(tp, 0, uint_tp);
331 rt_uMod.ent = new_entity(get_glob_type(), ID(".urem"), tp);
332 set_entity_ld_ident(rt_uMod.ent, ID(".urem"));
333 rt_uMod.mode = mode_T;
334 rt_uMod.res_mode = mode_Iu;
335 rt_uMod.mem_proj_nr = pn_Mod_M;
336 rt_uMod.regular_proj_nr = pn_Mod_X_regular;
337 rt_uMod.exc_proj_nr = pn_Mod_X_except;
338 rt_uMod.res_proj_nr = pn_Mod_res;
340 set_entity_visibility(rt_uMod.ent, ir_visibility_external);
342 map_Mod->kind = INTRINSIC_INSTR;
343 map_Mod->op = op_Mod;
344 map_Mod->i_mapper = (i_mapper_func)i_mapper_RuntimeCall;
345 map_Mod->ctx = &rt_uMod;
348 assert(n_records < ARRAY_SIZE(records));
349 lower_intrinsics(records, n_records, /*part_block_used=*/ true);
353 * Initializes the backend ISA
355 static arch_env_t *sparc_init(FILE *outfile)
357 sparc_isa_t *isa = XMALLOC(sparc_isa_t);
358 *isa = sparc_isa_template;
359 isa->constants = pmap_create();
361 be_gas_elf_type_char = '#';
362 be_gas_object_file_format = OBJECT_FILE_FORMAT_ELF;
363 be_gas_elf_variant = ELF_VARIANT_SPARC;
365 be_emit_init(outfile);
367 sparc_register_init();
368 sparc_create_opcodes(&sparc_irn_ops);
369 sparc_handle_intrinsics();
376 * Closes the output file and frees the ISA structure.
378 static void sparc_done(void *self)
380 sparc_isa_t *isa = (sparc_isa_t*)self;
382 /* emit now all global declarations */
383 be_gas_emit_decls(isa->base.main_env);
385 pmap_destroy(isa->constants);
392 * Get the register class which shall be used to store a value of a given mode.
393 * @param self The this pointer.
394 * @param mode The mode in question.
395 * @return A register class which can hold values of the given mode.
397 static const arch_register_class_t *sparc_get_reg_class_for_mode(const ir_mode *mode)
399 if (mode_is_float(mode))
400 return &sparc_reg_classes[CLASS_sparc_fp];
402 return &sparc_reg_classes[CLASS_sparc_gp];
406 * Returns the necessary byte alignment for storing a register of given class.
408 static int sparc_get_reg_class_alignment(const arch_register_class_t *cls)
410 ir_mode *mode = arch_register_class_mode(cls);
411 return get_mode_size_bytes(mode);
414 static ir_node *sparc_create_set(ir_node *cond)
416 return ir_create_cond_set(cond, mode_Iu);
419 static void sparc_lower_for_target(void)
421 size_t i, n_irgs = get_irp_n_irgs();
422 lower_mode_b_config_t lower_mode_b_config = {
427 lower_calls_with_compounds(LF_RETURN_HIDDEN);
429 if (sparc_isa_template.fpu_arch == SPARC_FPU_ARCH_SOFTFLOAT)
430 lower_floating_point();
432 lower_builtins(0, NULL);
436 for (i = 0; i < n_irgs; ++i) {
437 ir_graph *irg = get_irp_irg(i);
438 ir_lower_mode_b(irg, &lower_mode_b_config);
439 lower_switch(irg, 4, 256, false);
440 lower_alloc(irg, SPARC_STACK_ALIGNMENT, false, -SPARC_MIN_STACKSIZE);
443 for (i = 0; i < n_irgs; ++i) {
444 ir_graph *irg = get_irp_irg(i);
445 /* Turn all small CopyBs into loads/stores and all bigger CopyBs into
447 lower_CopyB(irg, 31, 32);
451 static int sparc_is_mux_allowed(ir_node *sel, ir_node *mux_false,
454 return ir_is_optimizable_mux(sel, mux_false, mux_true);
458 * Returns the libFirm configuration parameter for this backend.
460 static const backend_params *sparc_get_backend_params(void)
462 static const ir_settings_arch_dep_t arch_dep = {
463 1, /* also_use_subs */
464 1, /* maximum_shifts */
465 31, /* highest_shift_amount */
466 NULL, /* evaluate_cost_func */
469 32, /* max_bits_for_mulh */
471 static backend_params p = {
472 0, /* no inline assembly */
473 0, /* no support for RotL nodes */
475 1, /* modulo shift efficient */
476 0, /* non-modulo shift not efficient */
477 &arch_dep, /* will be set later */
478 sparc_is_mux_allowed, /* parameter for if conversion */
479 32, /* machine size */
480 NULL, /* float arithmetic mode */
481 NULL, /* long long type */
482 NULL, /* usigned long long type */
483 NULL, /* long double type */
484 0, /* no trampoline support: size 0 */
485 0, /* no trampoline support: align 0 */
486 NULL, /* no trampoline support: no trampoline builder */
487 4 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
490 ir_mode *mode_long_long
491 = new_ir_mode("long long", irms_int_number, 64, 1, irma_twos_complement,
493 ir_type *type_long_long = new_type_primitive(mode_long_long);
494 ir_mode *mode_unsigned_long_long
495 = new_ir_mode("unsigned long long", irms_int_number, 64, 0,
496 irma_twos_complement, 64);
497 ir_type *type_unsigned_long_long
498 = new_type_primitive(mode_unsigned_long_long);
500 p.type_long_long = type_long_long;
501 p.type_unsigned_long_long = type_unsigned_long_long;
503 if (sparc_isa_template.fpu_arch == SPARC_FPU_ARCH_SOFTFLOAT) {
504 p.mode_float_arithmetic = NULL;
505 p.type_long_double = NULL;
507 ir_mode *mode_long_double
508 = new_ir_mode("long double", irms_float_number, 128, 1,
510 ir_type *type_long_double = new_type_primitive(mode_long_double);
512 set_type_alignment_bytes(type_long_double, 8);
513 p.type_long_double = type_long_double;
518 static ir_graph **sparc_get_backend_irg_list(const void *self,
526 static asm_constraint_flags_t sparc_parse_asm_constraint(const char **c)
529 return ASM_CONSTRAINT_FLAG_INVALID;
532 static int sparc_is_valid_clobber(const char *clobber)
538 /* fpu set architectures. */
539 static const lc_opt_enum_int_items_t sparc_fpu_items[] = {
540 { "fpu", SPARC_FPU_ARCH_FPU },
541 { "softfloat", SPARC_FPU_ARCH_SOFTFLOAT },
545 static lc_opt_enum_int_var_t arch_fpu_var = {
546 &sparc_isa_template.fpu_arch, sparc_fpu_items
549 static const lc_opt_table_entry_t sparc_options[] = {
550 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &arch_fpu_var),
554 static ir_node *sparc_new_spill(ir_node *value, ir_node *after)
556 ir_node *block = get_block(after);
557 ir_graph *irg = get_irn_irg(value);
558 ir_node *frame = get_irg_frame(irg);
559 ir_node *mem = get_irg_no_mem(irg);
560 ir_mode *mode = get_irn_mode(value);
563 if (mode_is_float(mode)) {
564 store = create_stf(NULL, block, value, frame, mem, mode, NULL, 0, true);
566 store = new_bd_sparc_St_imm(NULL, block, value, frame, mem, mode, NULL,
569 sched_add_after(after, store);
573 static ir_node *sparc_new_reload(ir_node *value, ir_node *spill,
576 ir_node *block = get_block(before);
577 ir_graph *irg = get_irn_irg(value);
578 ir_node *frame = get_irg_frame(irg);
579 ir_mode *mode = get_irn_mode(value);
583 if (mode_is_float(mode)) {
584 load = create_ldf(NULL, block, frame, spill, mode, NULL, 0, true);
586 load = new_bd_sparc_Ld_imm(NULL, block, frame, spill, mode, NULL, 0,
589 sched_add_before(before, load);
590 assert((long)pn_sparc_Ld_res == (long)pn_sparc_Ldf_res);
591 res = new_r_Proj(load, mode, pn_sparc_Ld_res);
596 const arch_isa_if_t sparc_isa_if = {
598 sparc_lower_for_target,
600 NULL, /* handle intrinsics */
601 sparc_get_reg_class_for_mode,
603 sparc_get_reg_class_alignment,
604 sparc_get_backend_params,
605 sparc_get_backend_irg_list,
606 NULL, /* mark remat */
607 sparc_parse_asm_constraint,
608 sparc_is_valid_clobber,
611 NULL, /* get_pic_base */
612 NULL, /* before_abi */
617 NULL, /* register_saved_by */
622 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_sparc)
623 void be_init_arch_sparc(void)
625 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
626 lc_opt_entry_t *sparc_grp = lc_opt_get_grp(be_grp, "sparc");
628 lc_opt_add_table(sparc_grp, sparc_options);
630 be_register_isa_if("sparc", &sparc_isa_if);
631 FIRM_DBG_REGISTER(dbg, "firm.be.sparc.cg");
632 sparc_init_transform();
633 sparc_init_emitter();