2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Moritz Kroll, Jens Mueller
41 #include "../besched.h"
42 #include "../benode.h"
44 #include "ppc32_emitter.h"
45 #include "gen_ppc32_emitter.h"
46 #include "gen_ppc32_regalloc_if.h"
47 #include "ppc32_nodes_attr.h"
48 #include "ppc32_new_nodes.h"
49 #include "ppc32_map_regs.h"
51 #define SNPRINTF_BUF_LEN 128
53 static char printbuf[SNPRINTF_BUF_LEN];
58 /*************************************************************
60 * (_) | | / _| | | | |
61 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
62 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
63 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
64 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
67 *************************************************************/
69 * Returns the register at in position pos.
71 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
73 const arch_register_t *reg = NULL;
75 assert(get_irn_arity(irn) > pos && "Invalid IN position");
77 /* The out register of the operator at position pos is the
78 in register we need. */
79 op = get_irn_n(irn, pos);
81 reg = arch_get_irn_register(op);
83 assert(reg && "no in register found");
88 * Returns the register at out position pos.
90 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
92 const arch_register_t *reg = NULL;
94 assert(get_irn_n_edges(irn) > pos && "Invalid OUT position");
96 /* 1st case: irn is not of mode_T, so it has only */
97 /* one OUT register -> good */
98 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
99 /* Proj with the corresponding projnum for the register */
101 if (get_irn_mode(irn) != mode_T) {
102 reg = arch_get_irn_register(irn);
103 } else if (is_ppc32_irn(irn)) {
104 reg = arch_irn_get_register(irn, pos);
106 const ir_edge_t *edge;
108 foreach_out_edge(irn, edge) {
109 proj = get_edge_src_irn(edge);
110 assert(is_Proj(proj) && "non-Proj from mode_T node");
111 if (get_Proj_proj(proj) == pos) {
112 reg = arch_get_irn_register(proj);
118 assert(reg && "no out register found");
123 * Emit the name of the source register at given input position.
125 void ppc32_emit_source_register(const ir_node *node, int pos) {
126 const arch_register_t *reg = get_in_reg(node, pos);
127 be_emit_string(arch_register_get_name(reg));
131 * Emit the name of the destination register at given output position.
133 void ppc32_emit_dest_register(const ir_node *node, int pos) {
134 const arch_register_t *reg = get_out_reg(node, pos);
135 be_emit_string(arch_register_get_name(reg));
138 void ppc32_emit_rlwimi_helper(const ir_node *n) {
139 const rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
141 be_emit_irprintf("%i, %i, %i", rlwimi_const->shift,
142 rlwimi_const->maskA, rlwimi_const->maskB);
146 * Emit a const or symconst.
148 void ppc32_emit_immediate(const ir_node *n) {
151 switch (get_ppc32_type(n)) {
153 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
156 case ppc32_ac_SymConst:
157 buf = get_id_str(get_ppc32_symconst_ident(n));
159 case ppc32_ac_Offset:
160 be_emit_irprintf("%i", get_ppc32_offset(n));
163 assert(0 && "node_const_to_str(): Illegal offset type");
166 switch (get_ppc32_offset_mode(n)) {
171 be_emit_irprintf("lo16(%s)", buf);
174 be_emit_irprintf("hi16(%s)", buf);
177 be_emit_irprintf("ha16(%s)", buf);
180 assert(0 && "node_const_to_str(): Illegal offset mode");
186 * Emits a node's offset.
188 void ppc32_emit_offset(const ir_node *n) {
190 if (get_ppc32_type(n) == ppc32_ac_None) {
195 switch (get_ppc32_type(n)) {
197 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
200 case ppc32_ac_SymConst:
201 buf = get_id_str(get_ppc32_symconst_ident(n));
203 case ppc32_ac_Offset:
204 be_emit_irprintf("%i", get_ppc32_offset(n));
207 assert(0 && "node_offset_to_str(): Illegal offset type");
210 switch (get_ppc32_offset_mode(n)) {
215 be_emit_irprintf("lo16(%s)", buf);
218 be_emit_irprintf("hi16(%s)", buf);
221 be_emit_irprintf("ha16(%s)", buf);
224 assert(0 && "node_offset_to_str(): Illegal offset mode");
230 * Returns the target label for a control flow node.
232 static char *get_cfop_target(const ir_node *irn, char *buf) {
233 ir_node *bl = get_irn_link(irn);
235 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
240 * Emits code for a unconditional jump.
242 static void emit_Jmp(const ir_node *irn) {
243 ir_node *block = get_nodes_block(irn);
245 if (get_irn_link(irn) != get_irn_link(block)) {
246 be_emit_irprintf("\tb %s", get_cfop_target(irn, printbuf));
248 be_emit_irprintf("/* fallthrough(%+F) */", get_irn_link(irn));
250 be_emit_finish_line_gas(irn);
254 * Emits code for a call
256 static void emit_be_Call(const ir_node *irn) {
257 ir_entity *call_ent = be_Call_get_entity(irn);
260 be_emit_irprintf("\tbl %s", get_entity_ld_name(call_ent));
262 be_emit_cstring("\tmtlr ");
263 ppc32_emit_source_register(irn, be_pos_Call_ptr);
264 be_emit_pad_comment();
265 be_emit_cstring("/* Move to link register and link */\n");
266 be_emit_write_line();
267 be_emit_cstring("\tblrl");
269 be_emit_finish_line_gas(irn);
272 static void emit_ppc32_Branch(const ir_node *irn) {
273 static const char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
274 int projnum = get_ppc32_proj_nr(irn);
276 const ir_edge_t *edge = get_irn_out_edge_first(irn);
277 ir_node *proj = get_edge_src_irn(edge);
281 if (get_Proj_proj(proj) == pn_Cond_true)
286 assert(opind>=0 && opind<8);
289 get_cfop_target(proj, printbuf);
290 be_emit_irprintf("\t%8s", branchops[opind]);
291 ppc32_emit_source_register(irn, 0);
292 be_emit_cstring(", ");
293 be_emit_string(printbuf);
294 be_emit_finish_line_gas(irn);
297 edge = get_irn_out_edge_next(irn, edge);
299 ir_node *blk = get_edge_src_irn(edge);
300 be_emit_cstring("\tb ");
301 be_emit_string(get_cfop_target(blk, printbuf));
302 be_emit_finish_line_gas(irn);
306 static void emit_ppc32_LoopCopy(const ir_node *irn) {
307 be_emit_irprintf("LOOP_%ld:\n", get_irn_node_nr(irn));
308 be_emit_write_line();
310 be_emit_cstring("\tlwzu ");
311 ppc32_emit_dest_register(irn, 4);
312 be_emit_cstring(", 4(");
313 ppc32_emit_source_register(irn, 1);
315 be_emit_pad_comment();
316 be_emit_cstring("/* Load with update */\n");
317 be_emit_write_line();
319 be_emit_cstring("\tstwu ");
320 ppc32_emit_dest_register(irn, 4);
321 be_emit_cstring(", 4(");
322 ppc32_emit_source_register(irn, 2);
324 be_emit_pad_comment();
325 be_emit_cstring("/* Store with update */\n");
326 be_emit_write_line();
328 be_emit_irprintf("\tbdnz LOOP_%i", get_irn_node_nr(irn));
329 be_emit_finish_line_gas(irn);
332 static void emit_ppc32_Switch(const ir_node *irn) {
333 ir_node *proj, *defproj = NULL;
336 const ir_edge_t* edge;
337 foreach_out_edge(irn, edge) {
338 proj = get_edge_src_irn(edge);
339 assert(is_Proj(proj) && "Only proj allowed at Switch");
340 if (get_irn_mode(proj) != mode_X) continue;
342 pn = get_Proj_proj(proj);
343 /* check for default proj */
344 if (pn == get_ppc32_proj_nr(irn)) {
345 assert(defproj == NULL && "found two defProjs at Switch");
348 be_emit_cstring("\taddis ");
349 ppc32_emit_source_register(irn, 1);
350 be_emit_irprintf(", 0, hi16(%i)", pn);
351 be_emit_pad_comment();
352 be_emit_cstring("/* Load upper immediate */\n");
353 be_emit_write_line();
355 be_emit_cstring("\tori ");
356 ppc32_emit_source_register(irn, 1);
357 be_emit_cstring(", ");
358 ppc32_emit_source_register(irn, 1);
359 be_emit_irprintf(", lo16(%i)", pn);
360 be_emit_pad_comment();
361 be_emit_cstring("/* Load lower immediate */\n");
362 be_emit_write_line();
364 be_emit_cstring("\tcmp ");
365 ppc32_emit_source_register(irn, 2);
366 be_emit_cstring(", ");
367 ppc32_emit_source_register(irn, 0);
368 be_emit_cstring(", ");
369 ppc32_emit_source_register(irn, 1);
370 be_emit_pad_comment();
371 be_emit_cstring("/* Compare */\n");
372 be_emit_write_line();
374 be_emit_cstring("\tbeq ");
375 ppc32_emit_source_register(irn, 2);
376 be_emit_irprintf(", %s", get_cfop_target(proj, printbuf));
377 be_emit_cstring("/* Branch if equal */\n");
378 be_emit_write_line();
381 assert(defproj != NULL && "didn't find defProj at Switch");
382 be_emit_irprintf("\tb %s", get_cfop_target(defproj, printbuf));
383 be_emit_finish_line_gas(irn);
387 * Emits code for a backend Copy node
389 static void emit_be_Copy(const ir_node *irn) {
390 const arch_register_class_t *regclass = arch_get_irn_reg_class(irn, 0);
392 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
393 be_emit_cstring("\tmr ");
394 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
395 be_emit_cstring("\tfmr ");
396 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
397 be_emit_cstring("\tmcrf ");
399 assert(0 && "Illegal register class for Copy");
400 panic("ppc32 Emitter: Illegal register class for Copy");
402 ppc32_emit_dest_register(irn, 0);
403 be_emit_cstring(", ");
404 ppc32_emit_source_register(irn, 0);
405 be_emit_finish_line_gas(irn);
409 * Emits code for a backend Perm node
411 static void emit_be_Perm(const ir_node *irn) {
412 const arch_register_class_t *regclass = arch_get_irn_reg_class(irn, 0);
414 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
415 be_emit_cstring("\txor ");
416 ppc32_emit_source_register(irn, 0);
417 be_emit_cstring(", ");
418 ppc32_emit_source_register(irn, 0);
419 be_emit_cstring(", ");
420 ppc32_emit_source_register(irn, 1);
421 be_emit_pad_comment();
422 be_emit_cstring("/* Swap with XOR */\n");
423 be_emit_write_line();
425 be_emit_cstring("\txor ");
426 ppc32_emit_source_register(irn, 1);
427 be_emit_cstring(", ");
428 ppc32_emit_source_register(irn, 0);
429 be_emit_cstring(", ");
430 ppc32_emit_source_register(irn, 1);
431 be_emit_pad_comment();
432 be_emit_cstring("/* (continued) */\n");
433 be_emit_write_line();
435 be_emit_cstring("\txor ");
436 ppc32_emit_source_register(irn, 0);
437 be_emit_cstring(", ");
438 ppc32_emit_source_register(irn, 0);
439 be_emit_cstring(", ");
440 ppc32_emit_source_register(irn, 1);
441 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
442 be_emit_cstring("\tfmr f0, ");
443 ppc32_emit_source_register(irn, 0);
444 be_emit_pad_comment();
445 be_emit_cstring("/* Swap with moves */\n");
446 be_emit_write_line();
448 be_emit_cstring("\tfmr ");
449 ppc32_emit_source_register(irn, 0);
450 be_emit_cstring(", ");
451 ppc32_emit_source_register(irn, 1);
452 be_emit_pad_comment();
453 be_emit_cstring("/* (continued) */\n");
454 be_emit_write_line();
456 be_emit_cstring("\tfmr ");
457 ppc32_emit_source_register(irn, 1);
458 be_emit_cstring(", f0");
459 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
460 be_emit_cstring("\tmcrf cr7, ");
461 ppc32_emit_source_register(irn, 0);
462 be_emit_pad_comment();
463 be_emit_cstring("/* Swap with moves */\n");
464 be_emit_write_line();
466 be_emit_cstring("\tmcrf ");
467 ppc32_emit_source_register(irn, 0);
468 be_emit_cstring(", ");
469 ppc32_emit_source_register(irn, 1);
470 be_emit_pad_comment();
471 be_emit_cstring("/* (continued) */\n");
472 be_emit_write_line();
474 be_emit_cstring("\tmcrf ");
475 ppc32_emit_source_register(irn, 1);
476 be_emit_cstring(", cr7");
478 assert(0 && "Illegal register class for Perm");
479 panic("ppc32 Emitter: Illegal register class for Perm");
481 be_emit_finish_line_gas(irn);
486 * Emits code for a proj -> node
488 static void emit_Proj(const ir_node *irn) {
489 ir_node *pred = get_Proj_pred(irn);
491 if (is_Start(pred)) {
492 if (get_Proj_proj(irn) == pn_Start_X_initial_exec) {
498 static void emit_be_IncSP(const ir_node *irn) {
499 int offs = be_get_IncSP_offset(irn);
501 be_emit_irprintf("\t/* ignored IncSP with %d */", -offs);
502 be_emit_finish_line_gas(irn);
505 // assert(offs<=0x7fff);
506 // lc_efprintf(ppc32_get_arg_env(), F, "\taddi %1S, %1S, %d\t\t\t/* %+F (IncSP) */\n", irn, irn,
510 // fprintf(F, "\t\t\t\t\t/* omitted IncSP with 0 */\n");
514 /*static void emit_Spill(const ir_node *irn, ppc32_emit_env_t *emit_env) {
515 ir_node *context = be_get_Spill_context(irn);
516 ir_entity *entity = be_get_spill_entity(irn);
519 /***********************************************************************************
522 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
523 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
524 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
525 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
527 ***********************************************************************************/
529 * The type of a emitter function.
531 typedef void (emit_func)(const ir_node *irn);
534 * Set a node emitter. Make it a bit more type safe.
536 static inline void set_emitter(ir_op *op, emit_func ppc32_emit_node) {
537 op->ops.generic = (op_func)ppc32_emit_node;
540 static void ppc32_register_emitters(void) {
541 /* first clear generic function pointers */
542 clear_irp_opcodes_generic_func();
544 /* register generated emitter functions */
545 ppc32_register_spec_emitters();
547 set_emitter(op_ppc32_Branch, emit_ppc32_Branch);
548 set_emitter(op_ppc32_LoopCopy, emit_ppc32_LoopCopy);
549 set_emitter(op_ppc32_Switch, emit_ppc32_Switch);
550 set_emitter(op_be_Call, emit_be_Call);
551 set_emitter(op_Jmp, emit_Jmp);
552 set_emitter(op_Proj, emit_Proj);
553 set_emitter(op_be_IncSP, emit_be_IncSP);
554 set_emitter(op_be_Copy, emit_be_Copy);
555 set_emitter(op_be_Perm, emit_be_Perm);
556 // set_emitter(op_Spill, emit_Spill);
557 // set_emitter(op_Reload, emit_Reload);
561 * Emits code for a node.
563 static void ppc32_emit_node(const ir_node *irn) {
564 ir_op *op = get_irn_op(irn);
566 if (op->ops.generic) {
567 emit_func *emit = (emit_func *)op->ops.generic;
570 be_emit_cstring("\t/* TODO */");
571 be_emit_finish_line_gas(irn);
577 * Walks over the nodes in a block connected by scheduling edges
578 * and emits code for each node.
580 static void ppc32_gen_block(const ir_node *block) {
583 if (! is_Block(block))
586 be_emit_irprintf("BLOCK_%ld:\n", get_irn_node_nr(block));
587 be_emit_write_line();
588 sched_foreach(block, irn) {
589 ppc32_emit_node(irn);
595 * Emits code for function start.
597 static void ppc32_emit_start(ir_graph *irg) {
598 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
599 int framesize = get_type_size_bytes(get_irg_frame_type(irg));
601 if(! strcmp(irg_name, "main")) { // XXX: underscore hack
605 be_emit_irprintf("\t.text\n\t.globl %s\n\t.align 4\n%s:\n", irg_name, irg_name);
607 if (framesize > 24) {
608 be_emit_cstring("\tmflr r0\n");
609 be_emit_cstring("\tstw r0, 8(r1)\n");
610 be_emit_irprintf("\tstwu r1, -%i(r1)\n", framesize);
612 be_emit_irprintf("\t/* set new frame (%d) omitted */\n", framesize);
614 be_emit_write_line();
617 // store link register in linkage area (TODO: if needed)
619 be_emit_cstring("\tmflr r0\n");
620 be_emit_cstring("\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
621 be_emit_write_line();
626 * Emits code for function end
628 static void ppc32_emit_end(ir_graph *irg) {
629 int framesize = get_type_size_bytes(get_irg_frame_type(irg));
633 // restore link register
635 be_emit_cstring("\tlwz r0, 0(r1)\n");
636 be_emit_cstring("\taddi r1, r1, 4\n");
637 be_emit_cstring("\tmtlr r0\n");
638 be_emit_write_line();
641 be_emit_cstring("\tlwz r1, 0(r1)\n");
642 be_emit_cstring("\tlwz r0, 8(r1)\n");
643 be_emit_cstring("\tmtlr r0\n");
644 be_emit_write_line();
646 be_emit_cstring("\tblr\n\n");
647 be_emit_write_line();
651 * Sets labels for control flow nodes (jump target)
652 * TODO: Jump optimization
654 void ppc32_gen_labels(ir_node *block, void *env) {
659 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
660 pred = get_Block_cfgpred(block, n);
661 set_irn_link(pred, block);
666 * Main driver: generates code for one routine
668 void ppc32_gen_routine(const ppc32_code_gen_t *cg, ir_graph *irg)
673 ppc32_register_emitters();
675 ppc32_emit_start(irg);
676 irg_block_walk_graph(irg, ppc32_gen_labels, NULL, NULL);
678 n = ARR_LEN(cg->blk_sched);
679 for (i = 0; i < n;) {
682 block = cg->blk_sched[i];
684 next_bl = i < n ? cg->blk_sched[i] : NULL;
686 /* set here the link. the emitter expects to find the next block here */
687 set_irn_link(block, next_bl);
688 ppc32_gen_block(block);