2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
39 #include "../besched_t.h"
40 #include "../benode_t.h"
42 #include "ppc32_emitter.h"
43 #include "gen_ppc32_emitter.h"
44 #include "gen_ppc32_regalloc_if.h"
45 #include "ppc32_nodes_attr.h"
46 #include "ppc32_new_nodes.h"
47 #include "ppc32_map_regs.h"
49 #define SNPRINTF_BUF_LEN 128
51 static const arch_env_t *arch_env = NULL;
52 static char printbuf[SNPRINTF_BUF_LEN];
53 static char printbuf2[SNPRINTF_BUF_LEN];
58 /*************************************************************
60 * (_) | | / _| | | | |
61 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
62 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
63 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
64 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
67 *************************************************************/
69 const char *ppc32_rlwimi_emit_helper(const ir_node *n, ppc32_emit_env_t *env) {
70 rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
71 snprintf(printbuf, SNPRINTF_BUF_LEN, "%i, %i, %i", rlwimi_const->shift,
72 rlwimi_const->maskA, rlwimi_const->maskB);
78 * Return a const or symconst as string.
80 static const char *node_const_to_str(ir_node *n) {
82 switch(get_ppc32_type(n))
85 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
88 case ppc32_ac_SymConst:
89 buf=get_id_str(get_ppc32_symconst_ident(n));
92 snprintf(printbuf, SNPRINTF_BUF_LEN, "%i", get_ppc32_offset(n));
95 assert(0 && "node_const_to_str(): Illegal offset type");
98 switch(get_ppc32_offset_mode(n))
103 snprintf(printbuf2, SNPRINTF_BUF_LEN, "lo16(%s)", buf);
106 snprintf(printbuf2, SNPRINTF_BUF_LEN, "hi16(%s)", buf);
109 snprintf(printbuf2, SNPRINTF_BUF_LEN, "ha16(%s)", buf);
112 assert(0 && "node_const_to_str(): Illegal offset mode");
118 * Returns node's offset as string.
120 static const char *node_offset_to_str(ir_node *n) {
122 if(get_ppc32_type(n)==ppc32_ac_None) return "0";
123 switch(get_ppc32_type(n))
126 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
129 case ppc32_ac_SymConst:
130 buf=get_id_str(get_ppc32_symconst_ident(n));
132 case ppc32_ac_Offset:
133 snprintf(printbuf, SNPRINTF_BUF_LEN, "%i", get_ppc32_offset(n));
136 assert(0 && "node_offset_to_str(): Illegal offset type");
139 switch(get_ppc32_offset_mode(n))
144 snprintf(printbuf2, SNPRINTF_BUF_LEN, "lo16(%s)", buf);
147 snprintf(printbuf2, SNPRINTF_BUF_LEN, "hi16(%s)", buf);
150 snprintf(printbuf2, SNPRINTF_BUF_LEN, "ha16(%s)", buf);
153 assert(0 && "node_offset_to_str(): Illegal offset mode");
158 /* We always pass the ir_node which is a pointer. */
159 static int ppc32_get_arg_type(const lc_arg_occ_t *occ) {
160 return lc_arg_type_ptr;
165 * Returns the register at in position pos.
167 static const arch_register_t *get_in_reg(ir_node *irn, int pos) {
169 const arch_register_t *reg = NULL;
171 assert(get_irn_arity(irn) > pos && "Invalid IN position");
173 /* The out register of the operator at position pos is the
174 in register we need. */
175 op = get_irn_n(irn, pos);
177 reg = arch_get_irn_register(arch_env, op);
179 assert(reg && "no in register found");
184 * Returns the register at out position pos.
186 static const arch_register_t *get_out_reg(ir_node *irn, int pos) {
188 const arch_register_t *reg = NULL;
190 assert(get_irn_n_edges(irn) > pos && "Invalid OUT position");
192 /* 1st case: irn is not of mode_T, so it has only */
193 /* one OUT register -> good */
194 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
195 /* Proj with the corresponding projnum for the register */
197 if (get_irn_mode(irn) != mode_T) {
198 reg = arch_get_irn_register(arch_env, irn);
200 else if (is_ppc32_irn(irn)) {
201 reg = get_ppc32_out_reg(irn, pos);
204 const ir_edge_t *edge;
206 foreach_out_edge(irn, edge) {
207 proj = get_edge_src_irn(edge);
208 assert(is_Proj(proj) && "non-Proj from mode_T node");
209 if (get_Proj_proj(proj) == pos) {
210 reg = arch_get_irn_register(arch_env, proj);
216 assert(reg && "no out register found");
221 * Returns the number of the in register at position pos.
223 int get_ppc32_reg_nr(ir_node *irn, int pos, int in_out) {
224 const arch_register_t *reg;
227 reg = get_in_reg(irn, pos);
230 reg = get_out_reg(irn, pos);
233 return arch_register_get_index(reg);
237 * Returns the name of the in register at position pos.
239 const char *get_ppc32_reg_name(ir_node *irn, int pos, int in_out) {
240 const arch_register_t *reg;
243 reg = get_in_reg(irn, pos);
246 reg = get_out_reg(irn, pos);
249 return arch_register_get_name(reg);
253 * Get the register name for a node.
255 static int ppc32_get_reg_name(lc_appendable_t *app,
256 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
259 ir_node *X = arg->v_ptr;
260 int nr = occ->width - 1;
263 return lc_arg_append(app, occ, "(null)", 6);
265 if (occ->conversion == 'S') {
266 buf = get_ppc32_reg_name(X, nr, 1);
269 buf = get_ppc32_reg_name(X, nr, 0);
272 // lc_appendable_chadd(app, '%');
273 return lc_arg_append(app, occ, buf, strlen(buf));
277 * Returns the tarval or offset of an ppc node as a string.
279 static int ppc32_const_to_str(lc_appendable_t *app,
280 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
283 ir_node *X = arg->v_ptr;
286 return lc_arg_append(app, occ, "(null)", 6);
288 if (occ->conversion == 'C') {
289 buf = node_const_to_str(X);
292 buf = node_offset_to_str(X);
295 return lc_arg_append(app, occ, buf, strlen(buf));
299 * Determines the SSE suffix depending on the mode.
301 static int ppc32_get_mode_suffix(lc_appendable_t *app,
302 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
304 ir_node *X = arg->v_ptr;
307 return lc_arg_append(app, occ, "(null)", 6);
309 if (get_mode_size_bits(get_irn_mode(X)) == 32)
310 return lc_appendable_chadd(app, 's');
312 return lc_appendable_chadd(app, 'd');
316 * Return the ppc printf arg environment.
317 * We use the firm environment with some additional handlers.
319 const lc_arg_env_t *ppc32_get_arg_env(void) {
320 static lc_arg_env_t *env = NULL;
322 static const lc_arg_handler_t ppc32_reg_handler = { ppc32_get_arg_type, ppc32_get_reg_name };
323 static const lc_arg_handler_t ppc32_const_handler = { ppc32_get_arg_type, ppc32_const_to_str };
324 static const lc_arg_handler_t ppc32_mode_handler = { ppc32_get_arg_type, ppc32_get_mode_suffix };
327 /* extend the firm printer */
328 env = firm_get_arg_env();
331 lc_arg_register(env, "ppc:sreg", 'S', &ppc32_reg_handler);
332 lc_arg_register(env, "ppc:dreg", 'D', &ppc32_reg_handler);
333 lc_arg_register(env, "ppc:cnst", 'C', &ppc32_const_handler);
334 lc_arg_register(env, "ppc:offs", 'O', &ppc32_const_handler);
335 lc_arg_register(env, "ppc:mode", 'M', &ppc32_mode_handler);
342 * Returns the target label for a control flow node.
344 static char *get_cfop_target(const ir_node *irn, char *buf) {
345 ir_node *bl = get_irn_link(irn);
347 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
352 * Emits code for a unconditional jump.
354 static void emit_Jmp(const ir_node *irn, ppc32_emit_env_t *env) {
358 block = get_nodes_block(irn);
359 if(get_irn_link(irn) != get_irn_link(block))
360 ir_fprintf(F, "\tb %s\t\t\t/* Branch(%+F) */\n", get_cfop_target(irn, printbuf), get_irn_link(irn));
362 ir_fprintf(F, "\t\t\t\t\t\t/* fallthrough(%+F) */\n", get_irn_link(irn));
366 * Emits code for a call
368 static void emit_be_Call(const ir_node *irn, ppc32_emit_env_t *env) {
370 ir_entity *call_ent = be_Call_get_entity(irn);
374 ir_fprintf(F, "\tbl %s\t\t\t/* Branch and link(%+F) */\n", get_entity_name(call_ent), irn);
378 ir_node *node = get_irn_n(irn, be_pos_Call_ptr);
379 lc_efprintf(ppc32_get_arg_env(), F, "\tmtlr %1D\t\t\t/* Move to link register */\n", node);
380 ir_fprintf(F, "\tblrl\t\t\t/* Branch to link register and link(%+F) */\n", irn);
384 char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
386 static void emit_ppc32_Branch(const ir_node *n, ppc32_emit_env_t *env) {
388 int projnum = get_ppc32_proj_nr(n);
390 const ir_edge_t *edge = get_irn_out_edge_first(n);
391 ir_node *proj = get_edge_src_irn(edge);
395 if(get_Proj_proj(proj) == pn_Cond_true)
400 assert(opind>=0 && opind<8);
404 get_cfop_target(proj, printbuf);
405 lc_efprintf(ppc32_get_arg_env(), F, "\t%-8s%1S, %s\t\t\t/* Branch(%1S) to %s */\n",
406 branchops[opind], n, printbuf, n, printbuf);
409 edge = get_irn_out_edge_next(n, edge);
413 ir_node *irn = get_edge_src_irn(edge);
414 lc_efprintf(ppc32_get_arg_env(), F, "\tb %s\t\t\t/* Branch(%+F) */\n",
415 get_cfop_target(irn, printbuf), get_irn_link(irn));
419 static void emit_ppc32_LoopCopy(const ir_node *n, ppc32_emit_env_t *env) {
421 fprintf(F, "LOOP_%ld:\n", get_irn_node_nr(n));
422 lc_efprintf(ppc32_get_arg_env(), F, "\tlwzu %5D, 4(%2S)\t\t\t/* Load with update */\n",n,n);
423 lc_efprintf(ppc32_get_arg_env(), F, "\tstwu %5D, 4(%3S)\t\t\t/* Store with update */\n",n,n);
424 lc_efprintf(ppc32_get_arg_env(), F, "\tbdnz LOOP_%i\t\t\t/* Branch with decrement if CTR != 0 */\n",
428 static void emit_ppc32_Switch(const ir_node *n, ppc32_emit_env_t *env) {
430 ir_node *proj,*defproj=NULL;
433 const ir_edge_t* edge;
434 foreach_out_edge(n, edge) {
435 proj = get_edge_src_irn(edge);
436 assert(is_Proj(proj) && "Only proj allowed at Switch");
437 if(get_irn_mode(proj) != mode_X) continue;
439 pn = get_Proj_proj(proj);
440 /* check for default proj */
441 if (pn == get_ppc32_proj_nr(n)) {
442 assert(defproj == NULL && "found two defProjs at Switch");
448 lc_efprintf(ppc32_get_arg_env(), F, "\taddis %2S, 0, hi16(%i)\t\t\t/* Load upper immediate */\n",n,pn);
449 lc_efprintf(ppc32_get_arg_env(), F, "\tori %2S, %2S, lo16(%i)\t\t\t/* Load lower immediate */\n",n,n,pn);
450 lc_efprintf(ppc32_get_arg_env(), F, "\tcmp %3S, %1S, %2S\t\t\t/* Compare */\n",n,n,n);
451 lc_efprintf(ppc32_get_arg_env(), F, "\tbeq %3S, %s\t\t\t/* Branch if equal */\n",
452 n,get_cfop_target(proj, printbuf));
455 assert(defproj != NULL && "didn't find defProj at Switch");
456 lc_efprintf(ppc32_get_arg_env(), F, "\tb %s\t\t\t/* Default case */\n", get_cfop_target(defproj, printbuf));
460 * Emits code for a backend Copy node
462 static void emit_be_Copy(const ir_node *n, ppc32_emit_env_t *env) {
464 const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
466 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
468 lc_efprintf(ppc32_get_arg_env(), F, "\tmr %1D, %1S\t\t\t/* Move register */\n",n,n);
470 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
472 lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %1D, %1S\t\t\t/* Move register */\n",n,n);
474 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition])
476 lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %1D, %1S\t\t\t/* Move register */\n",n,n);
478 else assert(0 && "Illegal register class for Copy");
482 * Emits code for a backend Perm node
484 static void emit_be_Perm(const ir_node *n, ppc32_emit_env_t *env) {
486 const arch_register_class_t *regclass = arch_get_irn_reg_class(env->arch_env, n, 0);
488 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
490 lc_efprintf(ppc32_get_arg_env(), F, "\txor %1S, %1S, %2S\t\t\t/* Swap %1S, %2S with XOR */\n",n,n,n,n,n);
491 lc_efprintf(ppc32_get_arg_env(), F, "\txor %2S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
492 lc_efprintf(ppc32_get_arg_env(), F, "\txor %1S, %1S, %2S\t\t\t/* (continued) */\n",n,n,n);
494 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
496 lc_efprintf(ppc32_get_arg_env(), F, "\tfmr f0, %1S\t\t\t/* Swap %1S, %2S with moves */\n",n,n,n);
497 lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %1S, %2S\t\t\t/* (continued) */\n",n,n);
498 lc_efprintf(ppc32_get_arg_env(), F, "\tfmr %2S, f0\t\t\t/* (continued) */\n",n);
500 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition])
502 lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf cr7, %1S\t\t\t/* Swap %1S, %2S with moves */\n",n,n,n);
503 lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %1S, %2S\t\t\t/* (continued) */\n",n,n);
504 lc_efprintf(ppc32_get_arg_env(), F, "\tmcrf %2S, cr7\t\t\t/* (continued) */\n",n);
506 else assert(0 && "Illegal register class for Perm");
512 * Emits code for a proj -> node
514 static void emit_Proj(const ir_node *irn, ppc32_emit_env_t *env) {
515 ir_node *pred = get_Proj_pred(irn);
517 if (get_irn_op(pred) == op_Start) {
518 switch(get_Proj_proj(irn)) {
519 case pn_Start_X_initial_exec:
528 static void emit_be_IncSP(const ir_node *irn, ppc32_emit_env_t *emit_env) {
529 FILE *F = emit_env->out;
530 int offs = be_get_IncSP_offset(irn);
532 fprintf(F, "\t\t\t\t\t/* ignored IncSP with %d */\n", -offs);
535 // assert(offs<=0x7fff);
536 // lc_efprintf(ppc32_get_arg_env(), F, "\taddi %1S, %1S, %d\t\t\t/* %+F (IncSP) */\n", irn, irn,
540 // fprintf(F, "\t\t\t\t\t/* omitted IncSP with 0 */\n");
544 /*static void emit_Spill(const ir_node *irn, ppc32_emit_env_t *emit_env) {
545 ir_node *context = be_get_Spill_context(irn);
546 ir_entity *entity = be_get_spill_entity(irn);
549 /***********************************************************************************
552 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
553 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
554 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
555 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
557 ***********************************************************************************/
559 static void ppc32_register_emitters(void) {
560 /* first clear generic function pointers */
561 clear_irp_opcodes_generic_func();
563 /* register generated emitter functions */
564 ppc32_register_spec_emitters();
566 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
569 EMIT(ppc32_LoopCopy);
582 * Emits code for a node.
584 static void ppc32_emit_node(ir_node *irn, void *env) {
585 ppc32_emit_env_t *emit_env = env;
586 FILE *F = emit_env->out;
587 ir_op *op = get_irn_op(irn);
588 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
590 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
592 if (op->ops.generic) {
593 void (*emit)(ir_node *, void *) = (void (*)(ir_node *, void *))op->ops.generic;
597 ir_fprintf(F, "\t\t\t\t\t/* %+F */\n", irn);
603 * Walks over the nodes in a block connected by scheduling edges
604 * and emits code for each node.
606 static void ppc32_gen_block(ir_node *block, void *env) {
609 if (! is_Block(block))
612 fprintf(((ppc32_emit_env_t *)env)->out, "BLOCK_%ld:\n", get_irn_node_nr(block));
613 sched_foreach(block, irn) {
614 ppc32_emit_node(irn, env);
620 * Emits code for function start.
622 void ppc32_emit_start(FILE *F, ir_graph *irg, ppc32_emit_env_t *env) {
623 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
624 int framesize = get_type_size_bytes(get_irg_frame_type(env->cg->irg));
626 if(! strcmp(irg_name, "main")) // XXX: underscore hack
628 fprintf(F, "\t.text\n");
629 fprintf(F, "\t.globl _main\n");
630 fprintf(F, "\t.align 4\n");
631 fprintf(F, "_main:\n");
635 fprintf(F, "\t.text\n");
636 fprintf(F, "\t.globl %s\n", irg_name);
637 fprintf(F, "\t.align 4\n");
638 fprintf(F, "%s:\n", irg_name);
643 fprintf(F, "\tmflr r0\n");
644 fprintf(F, "\tstw r0, 8(r1)\n");
645 fprintf(F, "\tstwu r1, -%i(r1)\n", framesize);
649 fprintf(F, "\t\t\t\t\t/* set new frame (%d) omitted */\n", framesize);
655 // store link register in linkage area (TODO: if needed)
657 fprintf(F, "\tmflr r0\n");
658 fprintf(F, "\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
663 * Emits code for function end
665 void ppc32_emit_end(FILE *F, ir_graph *irg, ppc32_emit_env_t *env) {
666 int framesize = get_type_size_bytes(get_irg_frame_type(env->cg->irg));
670 // restore link register
672 fprintf(F, "\tlwz r0, 0(r1)\n");
673 fprintf(F, "\taddi r1, r1, 4\n");
674 fprintf(F, "\tmtlr r0\n");
678 fprintf(F, "\tlwz r1, 0(r1)\n");
679 fprintf(F, "\tlwz r0, 8(r1)\n");
680 fprintf(F, "\tmtlr r0\n");
682 fprintf(F, "\tblr\n\n");
686 * Sets labels for control flow nodes (jump target)
687 * TODO: Jump optimization
689 void ppc32_gen_labels(ir_node *block, void *env) {
693 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
694 pred = get_Block_cfgpred(block, n);
695 set_irn_link(pred, block);
700 * Main driver: generates code for one routine
702 void ppc32_gen_routine(FILE *F, ir_graph *irg, const ppc32_code_gen_t *cg) {
703 ppc32_emit_env_t emit_env;
708 emit_env.arch_env = cg->arch_env;
710 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ppc.emit");
712 /* set the global arch_env (needed by print hooks) */
713 arch_env = cg->arch_env;
715 ppc32_register_emitters();
717 ppc32_emit_start(F, irg, &emit_env);
718 irg_block_walk_graph(irg, ppc32_gen_labels, NULL, &emit_env);
720 n = ARR_LEN(cg->blk_sched);
721 for (i = 0; i < n;) {
724 block = cg->blk_sched[i];
726 next_bl = i < n ? cg->blk_sched[i] : NULL;
728 /* set here the link. the emitter expects to find the next block here */
729 set_irn_link(block, next_bl);
730 ppc32_gen_block(block, &emit_env);
732 ppc32_emit_end(F, irg, &emit_env);