2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Moritz Kroll, Jens Mueller
41 #include "../besched_t.h"
42 #include "../benode_t.h"
44 #include "ppc32_emitter.h"
45 #include "gen_ppc32_emitter.h"
46 #include "gen_ppc32_regalloc_if.h"
47 #include "ppc32_nodes_attr.h"
48 #include "ppc32_new_nodes.h"
49 #include "ppc32_map_regs.h"
51 #define SNPRINTF_BUF_LEN 128
53 static char printbuf[SNPRINTF_BUF_LEN];
57 static const ppc32_code_gen_t *cg;
60 /*************************************************************
62 * (_) | | / _| | | | |
63 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
64 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
65 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
66 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
69 *************************************************************/
71 * Returns the register at in position pos.
73 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
75 const arch_register_t *reg = NULL;
77 assert(get_irn_arity(irn) > pos && "Invalid IN position");
79 /* The out register of the operator at position pos is the
80 in register we need. */
81 op = get_irn_n(irn, pos);
83 reg = arch_get_irn_register(op);
85 assert(reg && "no in register found");
90 * Returns the register at out position pos.
92 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
94 const arch_register_t *reg = NULL;
96 assert(get_irn_n_edges(irn) > pos && "Invalid OUT position");
98 /* 1st case: irn is not of mode_T, so it has only */
99 /* one OUT register -> good */
100 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
101 /* Proj with the corresponding projnum for the register */
103 if (get_irn_mode(irn) != mode_T) {
104 reg = arch_get_irn_register(irn);
105 } else if (is_ppc32_irn(irn)) {
106 reg = get_ppc32_out_reg(irn, pos);
108 const ir_edge_t *edge;
110 foreach_out_edge(irn, edge) {
111 proj = get_edge_src_irn(edge);
112 assert(is_Proj(proj) && "non-Proj from mode_T node");
113 if (get_Proj_proj(proj) == pos) {
114 reg = arch_get_irn_register(proj);
120 assert(reg && "no out register found");
125 * Emit the name of the source register at given input position.
127 void ppc32_emit_source_register(const ir_node *node, int pos) {
128 const arch_register_t *reg = get_in_reg(node, pos);
129 be_emit_string(arch_register_get_name(reg));
133 * Emit the name of the destination register at given output position.
135 void ppc32_emit_dest_register(const ir_node *node, int pos) {
136 const arch_register_t *reg = get_out_reg(node, pos);
137 be_emit_string(arch_register_get_name(reg));
140 void ppc32_emit_rlwimi_helper(const ir_node *n) {
141 const rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
143 be_emit_irprintf("%i, %i, %i", rlwimi_const->shift,
144 rlwimi_const->maskA, rlwimi_const->maskB);
148 * Emit a const or symconst.
150 void ppc32_emit_immediate(const ir_node *n) {
153 switch (get_ppc32_type(n)) {
155 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
158 case ppc32_ac_SymConst:
159 buf = get_id_str(get_ppc32_symconst_ident(n));
161 case ppc32_ac_Offset:
162 be_emit_irprintf("%i", get_ppc32_offset(n));
165 assert(0 && "node_const_to_str(): Illegal offset type");
168 switch (get_ppc32_offset_mode(n)) {
173 be_emit_irprintf("lo16(%s)", buf);
176 be_emit_irprintf("hi16(%s)", buf);
179 be_emit_irprintf("ha16(%s)", buf);
182 assert(0 && "node_const_to_str(): Illegal offset mode");
188 * Emits a node's offset.
190 void ppc32_emit_offset(const ir_node *n) {
192 if (get_ppc32_type(n) == ppc32_ac_None) {
197 switch (get_ppc32_type(n)) {
199 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
202 case ppc32_ac_SymConst:
203 buf = get_id_str(get_ppc32_symconst_ident(n));
205 case ppc32_ac_Offset:
206 be_emit_irprintf("%i", get_ppc32_offset(n));
209 assert(0 && "node_offset_to_str(): Illegal offset type");
212 switch (get_ppc32_offset_mode(n)) {
217 be_emit_irprintf("lo16(%s)", buf);
220 be_emit_irprintf("hi16(%s)", buf);
223 be_emit_irprintf("ha16(%s)", buf);
226 assert(0 && "node_offset_to_str(): Illegal offset mode");
232 * Returns the target label for a control flow node.
234 static char *get_cfop_target(const ir_node *irn, char *buf) {
235 ir_node *bl = get_irn_link(irn);
237 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
242 * Emits code for a unconditional jump.
244 static void emit_Jmp(const ir_node *irn) {
245 ir_node *block = get_nodes_block(irn);
247 if (get_irn_link(irn) != get_irn_link(block)) {
248 be_emit_irprintf("\tb %s", get_cfop_target(irn, printbuf));
250 be_emit_irprintf("/* fallthrough(%+F) */", get_irn_link(irn));
252 be_emit_finish_line_gas(irn);
256 * Emits code for a call
258 static void emit_be_Call(const ir_node *irn) {
259 ir_entity *call_ent = be_Call_get_entity(irn);
262 set_entity_backend_marked(call_ent, 1);
263 be_emit_irprintf("\tbl %s", get_entity_ld_name(call_ent));
265 be_emit_cstring("\tmtlr ");
266 ppc32_emit_source_register(irn, be_pos_Call_ptr);
267 be_emit_pad_comment();
268 be_emit_cstring("/* Move to link register and link */\n");
269 be_emit_write_line();
270 be_emit_cstring("\tblrl");
272 be_emit_finish_line_gas(irn);
275 static void emit_ppc32_Branch(const ir_node *irn) {
276 static const char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
277 int projnum = get_ppc32_proj_nr(irn);
279 const ir_edge_t *edge = get_irn_out_edge_first(irn);
280 ir_node *proj = get_edge_src_irn(edge);
284 if (get_Proj_proj(proj) == pn_Cond_true)
289 assert(opind>=0 && opind<8);
292 get_cfop_target(proj, printbuf);
293 be_emit_irprintf("\t%8s", branchops[opind]);
294 ppc32_emit_source_register(irn, 0);
295 be_emit_cstring(", ");
296 be_emit_string(printbuf);
297 be_emit_finish_line_gas(irn);
300 edge = get_irn_out_edge_next(irn, edge);
302 ir_node *blk = get_edge_src_irn(edge);
303 be_emit_cstring("\tb ");
304 be_emit_string(get_cfop_target(blk, printbuf));
305 be_emit_finish_line_gas(irn);
309 static void emit_ppc32_LoopCopy(const ir_node *irn) {
310 be_emit_irprintf("LOOP_%ld:\n", get_irn_node_nr(irn));
311 be_emit_write_line();
313 be_emit_cstring("\tlwzu ");
314 ppc32_emit_dest_register(irn, 4);
315 be_emit_cstring(", 4(");
316 ppc32_emit_source_register(irn, 1);
318 be_emit_pad_comment();
319 be_emit_cstring("/* Load with update */\n");
320 be_emit_write_line();
322 be_emit_cstring("\tstwu ");
323 ppc32_emit_dest_register(irn, 4);
324 be_emit_cstring(", 4(");
325 ppc32_emit_source_register(irn, 2);
327 be_emit_pad_comment();
328 be_emit_cstring("/* Store with update */\n");
329 be_emit_write_line();
331 be_emit_irprintf("\tbdnz LOOP_%i", get_irn_node_nr(irn));
332 be_emit_finish_line_gas(irn);
335 static void emit_ppc32_Switch(const ir_node *irn) {
336 ir_node *proj, *defproj = NULL;
339 const ir_edge_t* edge;
340 foreach_out_edge(irn, edge) {
341 proj = get_edge_src_irn(edge);
342 assert(is_Proj(proj) && "Only proj allowed at Switch");
343 if (get_irn_mode(proj) != mode_X) continue;
345 pn = get_Proj_proj(proj);
346 /* check for default proj */
347 if (pn == get_ppc32_proj_nr(irn)) {
348 assert(defproj == NULL && "found two defProjs at Switch");
351 be_emit_cstring("\taddis ");
352 ppc32_emit_source_register(irn, 1);
353 be_emit_irprintf(", 0, hi16(%i)", pn);
354 be_emit_pad_comment();
355 be_emit_cstring("/* Load upper immediate */\n");
356 be_emit_write_line();
358 be_emit_cstring("\tori ");
359 ppc32_emit_source_register(irn, 1);
360 be_emit_cstring(", ");
361 ppc32_emit_source_register(irn, 1);
362 be_emit_irprintf(", lo16(%i)", pn);
363 be_emit_pad_comment();
364 be_emit_cstring("/* Load lower immediate */\n");
365 be_emit_write_line();
367 be_emit_cstring("\tcmp ");
368 ppc32_emit_source_register(irn, 2);
369 be_emit_cstring(", ");
370 ppc32_emit_source_register(irn, 0);
371 be_emit_cstring(", ");
372 ppc32_emit_source_register(irn, 1);
373 be_emit_pad_comment();
374 be_emit_cstring("/* Compare */\n");
375 be_emit_write_line();
377 be_emit_cstring("\tbeq ");
378 ppc32_emit_source_register(irn, 2);
379 be_emit_irprintf(", %s", get_cfop_target(proj, printbuf));
380 be_emit_cstring("/* Branch if equal */\n");
381 be_emit_write_line();
384 assert(defproj != NULL && "didn't find defProj at Switch");
385 be_emit_irprintf("\tb %s", get_cfop_target(defproj, printbuf));
386 be_emit_finish_line_gas(irn);
390 * Emits code for a backend Copy node
392 static void emit_be_Copy(const ir_node *irn) {
393 const arch_register_class_t *regclass = arch_get_irn_reg_class(irn, 0);
395 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
396 be_emit_cstring("\tmr ");
397 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
398 be_emit_cstring("\tfmr ");
399 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
400 be_emit_cstring("\tmcrf ");
402 assert(0 && "Illegal register class for Copy");
403 panic("ppc32 Emitter: Illegal register class for Copy");
405 ppc32_emit_dest_register(irn, 0);
406 be_emit_cstring(", ");
407 ppc32_emit_source_register(irn, 0);
408 be_emit_finish_line_gas(irn);
412 * Emits code for a backend Perm node
414 static void emit_be_Perm(const ir_node *irn) {
415 const arch_register_class_t *regclass = arch_get_irn_reg_class(irn, 0);
417 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
418 be_emit_cstring("\txor ");
419 ppc32_emit_source_register(irn, 0);
420 be_emit_cstring(", ");
421 ppc32_emit_source_register(irn, 0);
422 be_emit_cstring(", ");
423 ppc32_emit_source_register(irn, 1);
424 be_emit_pad_comment();
425 be_emit_cstring("/* Swap with XOR */\n");
426 be_emit_write_line();
428 be_emit_cstring("\txor ");
429 ppc32_emit_source_register(irn, 1);
430 be_emit_cstring(", ");
431 ppc32_emit_source_register(irn, 0);
432 be_emit_cstring(", ");
433 ppc32_emit_source_register(irn, 1);
434 be_emit_pad_comment();
435 be_emit_cstring("/* (continued) */\n");
436 be_emit_write_line();
438 be_emit_cstring("\txor ");
439 ppc32_emit_source_register(irn, 0);
440 be_emit_cstring(", ");
441 ppc32_emit_source_register(irn, 0);
442 be_emit_cstring(", ");
443 ppc32_emit_source_register(irn, 1);
444 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
445 be_emit_cstring("\tfmr f0, ");
446 ppc32_emit_source_register(irn, 0);
447 be_emit_pad_comment();
448 be_emit_cstring("/* Swap with moves */\n");
449 be_emit_write_line();
451 be_emit_cstring("\tfmr ");
452 ppc32_emit_source_register(irn, 0);
453 be_emit_cstring(", ");
454 ppc32_emit_source_register(irn, 1);
455 be_emit_pad_comment();
456 be_emit_cstring("/* (continued) */\n");
457 be_emit_write_line();
459 be_emit_cstring("\tfmr ");
460 ppc32_emit_source_register(irn, 1);
461 be_emit_cstring(", f0");
462 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
463 be_emit_cstring("\tmcrf cr7, ");
464 ppc32_emit_source_register(irn, 0);
465 be_emit_pad_comment();
466 be_emit_cstring("/* Swap with moves */\n");
467 be_emit_write_line();
469 be_emit_cstring("\tmcrf ");
470 ppc32_emit_source_register(irn, 0);
471 be_emit_cstring(", ");
472 ppc32_emit_source_register(irn, 1);
473 be_emit_pad_comment();
474 be_emit_cstring("/* (continued) */\n");
475 be_emit_write_line();
477 be_emit_cstring("\tmcrf ");
478 ppc32_emit_source_register(irn, 1);
479 be_emit_cstring(", cr7");
481 assert(0 && "Illegal register class for Perm");
482 panic("ppc32 Emitter: Illegal register class for Perm");
484 be_emit_finish_line_gas(irn);
489 * Emits code for a proj -> node
491 static void emit_Proj(const ir_node *irn) {
492 ir_node *pred = get_Proj_pred(irn);
494 if (is_Start(pred)) {
495 if (get_Proj_proj(irn) == pn_Start_X_initial_exec) {
501 static void emit_be_IncSP(const ir_node *irn) {
502 int offs = be_get_IncSP_offset(irn);
504 be_emit_irprintf("\t/* ignored IncSP with %d */", -offs);
505 be_emit_finish_line_gas(irn);
508 // assert(offs<=0x7fff);
509 // lc_efprintf(ppc32_get_arg_env(), F, "\taddi %1S, %1S, %d\t\t\t/* %+F (IncSP) */\n", irn, irn,
513 // fprintf(F, "\t\t\t\t\t/* omitted IncSP with 0 */\n");
517 /*static void emit_Spill(const ir_node *irn, ppc32_emit_env_t *emit_env) {
518 ir_node *context = be_get_Spill_context(irn);
519 ir_entity *entity = be_get_spill_entity(irn);
522 /***********************************************************************************
525 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
526 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
527 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
528 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
530 ***********************************************************************************/
532 * The type of a emitter function.
534 typedef void (emit_func)(const ir_node *irn);
537 * Set a node emitter. Make it a bit more type safe.
539 static INLINE void set_emitter(ir_op *op, emit_func ppc32_emit_node) {
540 op->ops.generic = (op_func)ppc32_emit_node;
543 static void ppc32_register_emitters(void) {
544 /* first clear generic function pointers */
545 clear_irp_opcodes_generic_func();
547 /* register generated emitter functions */
548 ppc32_register_spec_emitters();
550 set_emitter(op_ppc32_Branch, emit_ppc32_Branch);
551 set_emitter(op_ppc32_LoopCopy, emit_ppc32_LoopCopy);
552 set_emitter(op_ppc32_Switch, emit_ppc32_Switch);
553 set_emitter(op_be_Call, emit_be_Call);
554 set_emitter(op_Jmp, emit_Jmp);
555 set_emitter(op_Proj, emit_Proj);
556 set_emitter(op_be_IncSP, emit_be_IncSP);
557 set_emitter(op_be_Copy, emit_be_Copy);
558 set_emitter(op_be_Perm, emit_be_Perm);
559 // set_emitter(op_Spill, emit_Spill);
560 // set_emitter(op_Reload, emit_Reload);
564 * Emits code for a node.
566 static void ppc32_emit_node(const ir_node *irn) {
567 ir_op *op = get_irn_op(irn);
569 if (op->ops.generic) {
570 emit_func *emit = (emit_func *)op->ops.generic;
573 be_emit_cstring("\t/* TODO */");
574 be_emit_finish_line_gas(irn);
580 * Walks over the nodes in a block connected by scheduling edges
581 * and emits code for each node.
583 static void ppc32_gen_block(const ir_node *block) {
586 if (! is_Block(block))
589 be_emit_irprintf("BLOCK_%ld:\n", get_irn_node_nr(block));
590 be_emit_write_line();
591 sched_foreach(block, irn) {
592 ppc32_emit_node(irn);
598 * Emits code for function start.
600 static void ppc32_emit_start(ir_graph *irg) {
601 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
602 int framesize = get_type_size_bytes(get_irg_frame_type(cg->irg));
604 if(! strcmp(irg_name, "main")) { // XXX: underscore hack
608 be_emit_irprintf("\t.text\n\t.globl %s\n\t.align 4\n%s:\n", irg_name, irg_name);
610 if (framesize > 24) {
611 be_emit_cstring("\tmflr r0\n");
612 be_emit_cstring("\tstw r0, 8(r1)\n");
613 be_emit_irprintf("\tstwu r1, -%i(r1)\n", framesize);
615 be_emit_irprintf("\t/* set new frame (%d) omitted */\n", framesize);
617 be_emit_write_line();
620 // store link register in linkage area (TODO: if needed)
622 be_emit_cstring("\tmflr r0\n");
623 be_emit_cstring("\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
624 be_emit_write_line();
629 * Emits code for function end
631 static void ppc32_emit_end(ir_graph *irg) {
632 int framesize = get_type_size_bytes(get_irg_frame_type(cg->irg));
636 // restore link register
638 be_emit_cstring("\tlwz r0, 0(r1)\n");
639 be_emit_cstring("\taddi r1, r1, 4\n");
640 be_emit_cstring("\tmtlr r0\n");
641 be_emit_write_line();
644 be_emit_cstring("\tlwz r1, 0(r1)\n");
645 be_emit_cstring("\tlwz r0, 8(r1)\n");
646 be_emit_cstring("\tmtlr r0\n");
647 be_emit_write_line();
649 be_emit_cstring("\tblr\n\n");
650 be_emit_write_line();
654 * Sets labels for control flow nodes (jump target)
655 * TODO: Jump optimization
657 void ppc32_gen_labels(ir_node *block, void *env) {
662 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
663 pred = get_Block_cfgpred(block, n);
664 set_irn_link(pred, block);
669 * Main driver: generates code for one routine
671 void ppc32_gen_routine(const ppc32_code_gen_t *ppc32_cg, ir_graph *irg)
678 ppc32_register_emitters();
680 ppc32_emit_start(irg);
681 irg_block_walk_graph(irg, ppc32_gen_labels, NULL, NULL);
683 n = ARR_LEN(cg->blk_sched);
684 for (i = 0; i < n;) {
687 block = cg->blk_sched[i];
689 next_bl = i < n ? cg->blk_sched[i] : NULL;
691 /* set here the link. the emitter expects to find the next block here */
692 set_irn_link(block, next_bl);
693 ppc32_gen_block(block);