2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * @author Moritz Kroll, Jens Mueller
43 #include "../besched_t.h"
44 #include "../benode_t.h"
46 #include "ppc32_emitter.h"
47 #include "gen_ppc32_emitter.h"
48 #include "gen_ppc32_regalloc_if.h"
49 #include "ppc32_nodes_attr.h"
50 #include "ppc32_new_nodes.h"
51 #include "ppc32_map_regs.h"
53 #define SNPRINTF_BUF_LEN 128
55 static char printbuf[SNPRINTF_BUF_LEN];
59 static const arch_env_t *arch_env;
60 static const ppc32_code_gen_t *cg;
63 /*************************************************************
65 * (_) | | / _| | | | |
66 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
67 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
68 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
69 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
72 *************************************************************/
74 * Returns the register at in position pos.
76 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
93 * Returns the register at out position pos.
95 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
97 const arch_register_t *reg = NULL;
99 assert(get_irn_n_edges(irn) > pos && "Invalid OUT position");
101 /* 1st case: irn is not of mode_T, so it has only */
102 /* one OUT register -> good */
103 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
104 /* Proj with the corresponding projnum for the register */
106 if (get_irn_mode(irn) != mode_T) {
107 reg = arch_get_irn_register(arch_env, irn);
108 } else if (is_ppc32_irn(irn)) {
109 reg = get_ppc32_out_reg(irn, pos);
111 const ir_edge_t *edge;
113 foreach_out_edge(irn, edge) {
114 proj = get_edge_src_irn(edge);
115 assert(is_Proj(proj) && "non-Proj from mode_T node");
116 if (get_Proj_proj(proj) == pos) {
117 reg = arch_get_irn_register(arch_env, proj);
123 assert(reg && "no out register found");
128 * Emit the name of the source register at given input position.
130 void ppc32_emit_source_register(const ir_node *node, int pos) {
131 const arch_register_t *reg = get_in_reg(node, pos);
132 be_emit_string(arch_register_get_name(reg));
136 * Emit the name of the destination register at given output position.
138 void ppc32_emit_dest_register(const ir_node *node, int pos) {
139 const arch_register_t *reg = get_out_reg(node, pos);
140 be_emit_string(arch_register_get_name(reg));
143 void ppc32_emit_rlwimi_helper(const ir_node *n) {
144 const rlwimi_const_t *rlwimi_const = get_ppc32_rlwimi_const(n);
146 be_emit_irprintf("%i, %i, %i", rlwimi_const->shift,
147 rlwimi_const->maskA, rlwimi_const->maskB);
151 * Emit a const or symconst.
153 void ppc32_emit_immediate(const ir_node *n) {
156 switch (get_ppc32_type(n)) {
158 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
161 case ppc32_ac_SymConst:
162 buf = get_id_str(get_ppc32_symconst_ident(n));
164 case ppc32_ac_Offset:
165 be_emit_irprintf("%i", get_ppc32_offset(n));
168 assert(0 && "node_const_to_str(): Illegal offset type");
171 switch (get_ppc32_offset_mode(n)) {
176 be_emit_irprintf("lo16(%s)", buf);
179 be_emit_irprintf("hi16(%s)", buf);
182 be_emit_irprintf("ha16(%s)", buf);
185 assert(0 && "node_const_to_str(): Illegal offset mode");
191 * Emits a node's offset.
193 void ppc32_emit_offset(const ir_node *n) {
195 if (get_ppc32_type(n) == ppc32_ac_None) {
200 switch (get_ppc32_type(n)) {
202 tarval_snprintf(printbuf, SNPRINTF_BUF_LEN, get_ppc32_constant_tarval(n));
205 case ppc32_ac_SymConst:
206 buf = get_id_str(get_ppc32_symconst_ident(n));
208 case ppc32_ac_Offset:
209 be_emit_irprintf("%i", get_ppc32_offset(n));
212 assert(0 && "node_offset_to_str(): Illegal offset type");
215 switch (get_ppc32_offset_mode(n)) {
220 be_emit_irprintf("lo16(%s)", buf);
223 be_emit_irprintf("hi16(%s)", buf);
226 be_emit_irprintf("ha16(%s)", buf);
229 assert(0 && "node_offset_to_str(): Illegal offset mode");
235 * Returns the target label for a control flow node.
237 static char *get_cfop_target(const ir_node *irn, char *buf) {
238 ir_node *bl = get_irn_link(irn);
240 snprintf(buf, SNPRINTF_BUF_LEN, "BLOCK_%ld", get_irn_node_nr(bl));
245 * Emits code for a unconditional jump.
247 static void emit_Jmp(const ir_node *irn) {
248 ir_node *block = get_nodes_block(irn);
250 if (get_irn_link(irn) != get_irn_link(block)) {
251 be_emit_irprintf("\tb %s", get_cfop_target(irn, printbuf));
253 be_emit_irprintf("/* fallthrough(%+F) */", get_irn_link(irn));
255 be_emit_finish_line_gas(irn);
259 * Emits code for a call
261 static void emit_be_Call(const ir_node *irn) {
262 ir_entity *call_ent = be_Call_get_entity(irn);
265 set_entity_backend_marked(call_ent, 1);
266 be_emit_irprintf("\tbl %s", get_entity_ld_name(call_ent));
268 be_emit_cstring("\tmtlr ");
269 ppc32_emit_source_register(irn, be_pos_Call_ptr);
270 be_emit_pad_comment();
271 be_emit_cstring("/* Move to link register and link */\n");
272 be_emit_write_line();
273 be_emit_cstring("\tblrl");
275 be_emit_finish_line_gas(irn);
278 static void emit_ppc32_Branch(const ir_node *irn) {
279 static const char *branchops[8] = { 0, "beq", "blt", "ble", "bgt", "bge", "bne", "b" };
280 int projnum = get_ppc32_proj_nr(irn);
282 const ir_edge_t *edge = get_irn_out_edge_first(irn);
283 ir_node *proj = get_edge_src_irn(edge);
287 if (get_Proj_proj(proj) == pn_Cond_true)
292 assert(opind>=0 && opind<8);
295 get_cfop_target(proj, printbuf);
296 be_emit_irprintf("\t%8s", branchops[opind]);
297 ppc32_emit_source_register(irn, 0);
298 be_emit_cstring(", ");
299 be_emit_string(printbuf);
300 be_emit_finish_line_gas(irn);
303 edge = get_irn_out_edge_next(irn, edge);
305 ir_node *blk = get_edge_src_irn(edge);
306 be_emit_cstring("\tb ");
307 be_emit_string(get_cfop_target(blk, printbuf));
308 be_emit_finish_line_gas(irn);
312 static void emit_ppc32_LoopCopy(const ir_node *irn) {
313 be_emit_irprintf("LOOP_%ld:\n", get_irn_node_nr(irn));
314 be_emit_write_line();
316 be_emit_cstring("\tlwzu ");
317 ppc32_emit_dest_register(irn, 4);
318 be_emit_cstring(", 4(");
319 ppc32_emit_source_register(irn, 1);
321 be_emit_pad_comment();
322 be_emit_cstring("/* Load with update */\n");
323 be_emit_write_line();
325 be_emit_cstring("\tstwu ");
326 ppc32_emit_dest_register(irn, 4);
327 be_emit_cstring(", 4(");
328 ppc32_emit_source_register(irn, 2);
330 be_emit_pad_comment();
331 be_emit_cstring("/* Store with update */\n");
332 be_emit_write_line();
334 be_emit_irprintf("\tbdnz LOOP_%i", get_irn_node_nr(irn));
335 be_emit_finish_line_gas(irn);
338 static void emit_ppc32_Switch(const ir_node *irn) {
339 ir_node *proj, *defproj = NULL;
342 const ir_edge_t* edge;
343 foreach_out_edge(irn, edge) {
344 proj = get_edge_src_irn(edge);
345 assert(is_Proj(proj) && "Only proj allowed at Switch");
346 if (get_irn_mode(proj) != mode_X) continue;
348 pn = get_Proj_proj(proj);
349 /* check for default proj */
350 if (pn == get_ppc32_proj_nr(irn)) {
351 assert(defproj == NULL && "found two defProjs at Switch");
354 be_emit_cstring("\taddis ");
355 ppc32_emit_source_register(irn, 1);
356 be_emit_irprintf(", 0, hi16(%i)", pn);
357 be_emit_pad_comment();
358 be_emit_cstring("/* Load upper immediate */\n");
359 be_emit_write_line();
361 be_emit_cstring("\tori ");
362 ppc32_emit_source_register(irn, 1);
363 be_emit_cstring(", ");
364 ppc32_emit_source_register(irn, 1);
365 be_emit_irprintf(", lo16(%i)", pn);
366 be_emit_pad_comment();
367 be_emit_cstring("/* Load lower immediate */\n");
368 be_emit_write_line();
370 be_emit_cstring("\tcmp ");
371 ppc32_emit_source_register(irn, 2);
372 be_emit_cstring(", ");
373 ppc32_emit_source_register(irn, 0);
374 be_emit_cstring(", ");
375 ppc32_emit_source_register(irn, 1);
376 be_emit_pad_comment();
377 be_emit_cstring("/* Compare */\n");
378 be_emit_write_line();
380 be_emit_cstring("\tbeq ");
381 ppc32_emit_source_register(irn, 2);
382 be_emit_irprintf(", %s", get_cfop_target(proj, printbuf));
383 be_emit_cstring("/* Branch if equal */\n");
384 be_emit_write_line();
387 assert(defproj != NULL && "didn't find defProj at Switch");
388 be_emit_irprintf("\tb %s", get_cfop_target(defproj, printbuf));
389 be_emit_finish_line_gas(irn);
393 * Emits code for a backend Copy node
395 static void emit_be_Copy(const ir_node *irn) {
396 const arch_register_class_t *regclass = arch_get_irn_reg_class(arch_env, irn, 0);
398 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
399 be_emit_cstring("\tmr ");
400 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
401 be_emit_cstring("\tfmr ");
402 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
403 be_emit_cstring("\tmcrf ");
405 assert(0 && "Illegal register class for Copy");
406 panic("ppc32 Emitter: Illegal register class for Copy");
408 ppc32_emit_dest_register(irn, 0);
409 be_emit_cstring(", ");
410 ppc32_emit_source_register(irn, 0);
411 be_emit_finish_line_gas(irn);
415 * Emits code for a backend Perm node
417 static void emit_be_Perm(const ir_node *irn) {
418 const arch_register_class_t *regclass = arch_get_irn_reg_class(arch_env, irn, 0);
420 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp]) {
421 be_emit_cstring("\txor ");
422 ppc32_emit_source_register(irn, 0);
423 be_emit_cstring(", ");
424 ppc32_emit_source_register(irn, 0);
425 be_emit_cstring(", ");
426 ppc32_emit_source_register(irn, 1);
427 be_emit_pad_comment();
428 be_emit_cstring("/* Swap with XOR */\n");
429 be_emit_write_line();
431 be_emit_cstring("\txor ");
432 ppc32_emit_source_register(irn, 1);
433 be_emit_cstring(", ");
434 ppc32_emit_source_register(irn, 0);
435 be_emit_cstring(", ");
436 ppc32_emit_source_register(irn, 1);
437 be_emit_pad_comment();
438 be_emit_cstring("/* (continued) */\n");
439 be_emit_write_line();
441 be_emit_cstring("\txor ");
442 ppc32_emit_source_register(irn, 0);
443 be_emit_cstring(", ");
444 ppc32_emit_source_register(irn, 0);
445 be_emit_cstring(", ");
446 ppc32_emit_source_register(irn, 1);
447 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp]) {
448 be_emit_cstring("\tfmr f0, ");
449 ppc32_emit_source_register(irn, 0);
450 be_emit_pad_comment();
451 be_emit_cstring("/* Swap with moves */\n");
452 be_emit_write_line();
454 be_emit_cstring("\tfmr ");
455 ppc32_emit_source_register(irn, 0);
456 be_emit_cstring(", ");
457 ppc32_emit_source_register(irn, 1);
458 be_emit_pad_comment();
459 be_emit_cstring("/* (continued) */\n");
460 be_emit_write_line();
462 be_emit_cstring("\tfmr ");
463 ppc32_emit_source_register(irn, 1);
464 be_emit_cstring(", f0");
465 } else if (regclass == &ppc32_reg_classes[CLASS_ppc32_condition]) {
466 be_emit_cstring("\tmcrf cr7, ");
467 ppc32_emit_source_register(irn, 0);
468 be_emit_pad_comment();
469 be_emit_cstring("/* Swap with moves */\n");
470 be_emit_write_line();
472 be_emit_cstring("\tmcrf ");
473 ppc32_emit_source_register(irn, 0);
474 be_emit_cstring(", ");
475 ppc32_emit_source_register(irn, 1);
476 be_emit_pad_comment();
477 be_emit_cstring("/* (continued) */\n");
478 be_emit_write_line();
480 be_emit_cstring("\tmcrf ");
481 ppc32_emit_source_register(irn, 1);
482 be_emit_cstring(", cr7");
484 assert(0 && "Illegal register class for Perm");
485 panic("ppc32 Emitter: Illegal register class for Perm");
487 be_emit_finish_line_gas(irn);
492 * Emits code for a proj -> node
494 static void emit_Proj(const ir_node *irn) {
495 ir_node *pred = get_Proj_pred(irn);
497 if (is_Start(pred)) {
498 if (get_Proj_proj(irn) == pn_Start_X_initial_exec) {
504 static void emit_be_IncSP(const ir_node *irn) {
505 int offs = be_get_IncSP_offset(irn);
507 be_emit_irprintf("\t/* ignored IncSP with %d */", -offs);
508 be_emit_finish_line_gas(irn);
511 // assert(offs<=0x7fff);
512 // lc_efprintf(ppc32_get_arg_env(), F, "\taddi %1S, %1S, %d\t\t\t/* %+F (IncSP) */\n", irn, irn,
516 // fprintf(F, "\t\t\t\t\t/* omitted IncSP with 0 */\n");
520 /*static void emit_Spill(const ir_node *irn, ppc32_emit_env_t *emit_env) {
521 ir_node *context = be_get_Spill_context(irn);
522 ir_entity *entity = be_get_spill_entity(irn);
525 /***********************************************************************************
528 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
529 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
530 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
531 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
533 ***********************************************************************************/
535 * The type of a emitter function.
537 typedef void (emit_func)(const ir_node *irn);
540 * Set a node emitter. Make it a bit more type safe.
542 static INLINE void set_emitter(ir_op *op, emit_func ppc32_emit_node) {
543 op->ops.generic = (op_func)ppc32_emit_node;
546 static void ppc32_register_emitters(void) {
547 /* first clear generic function pointers */
548 clear_irp_opcodes_generic_func();
550 /* register generated emitter functions */
551 ppc32_register_spec_emitters();
553 set_emitter(op_ppc32_Branch, emit_ppc32_Branch);
554 set_emitter(op_ppc32_LoopCopy, emit_ppc32_LoopCopy);
555 set_emitter(op_ppc32_Switch, emit_ppc32_Switch);
556 set_emitter(op_be_Call, emit_be_Call);
557 set_emitter(op_Jmp, emit_Jmp);
558 set_emitter(op_Proj, emit_Proj);
559 set_emitter(op_be_IncSP, emit_be_IncSP);
560 set_emitter(op_be_Copy, emit_be_Copy);
561 set_emitter(op_be_Perm, emit_be_Perm);
562 // set_emitter(op_Spill, emit_Spill);
563 // set_emitter(op_Reload, emit_Reload);
567 * Emits code for a node.
569 static void ppc32_emit_node(const ir_node *irn) {
570 ir_op *op = get_irn_op(irn);
572 if (op->ops.generic) {
573 emit_func *emit = (emit_func *)op->ops.generic;
576 be_emit_cstring("\t/* TODO */");
577 be_emit_finish_line_gas(irn);
583 * Walks over the nodes in a block connected by scheduling edges
584 * and emits code for each node.
586 static void ppc32_gen_block(const ir_node *block) {
589 if (! is_Block(block))
592 be_emit_irprintf("BLOCK_%ld:\n", get_irn_node_nr(block));
593 be_emit_write_line();
594 sched_foreach(block, irn) {
595 ppc32_emit_node(irn);
601 * Emits code for function start.
603 static void ppc32_emit_start(ir_graph *irg) {
604 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
605 int framesize = get_type_size_bytes(get_irg_frame_type(cg->irg));
607 if(! strcmp(irg_name, "main")) { // XXX: underscore hack
611 be_emit_irprintf("\t.text\n\t.globl %s\n\t.align 4\n%s:\n", irg_name, irg_name);
613 if (framesize > 24) {
614 be_emit_cstring("\tmflr r0\n");
615 be_emit_cstring("\tstw r0, 8(r1)\n");
616 be_emit_irprintf("\tstwu r1, -%i(r1)\n", framesize);
618 be_emit_irprintf("\t/* set new frame (%d) omitted */\n", framesize);
620 be_emit_write_line();
623 // store link register in linkage area (TODO: if needed)
625 be_emit_cstring("\tmflr r0\n");
626 be_emit_cstring("\tstwu r0, -4(r1)\n"); // stw r0, 8(SP)
627 be_emit_write_line();
632 * Emits code for function end
634 static void ppc32_emit_end(ir_graph *irg) {
635 int framesize = get_type_size_bytes(get_irg_frame_type(cg->irg));
639 // restore link register
641 be_emit_cstring("\tlwz r0, 0(r1)\n");
642 be_emit_cstring("\taddi r1, r1, 4\n");
643 be_emit_cstring("\tmtlr r0\n");
644 be_emit_write_line();
647 be_emit_cstring("\tlwz r1, 0(r1)\n");
648 be_emit_cstring("\tlwz r0, 8(r1)\n");
649 be_emit_cstring("\tmtlr r0\n");
650 be_emit_write_line();
652 be_emit_cstring("\tblr\n\n");
653 be_emit_write_line();
657 * Sets labels for control flow nodes (jump target)
658 * TODO: Jump optimization
660 void ppc32_gen_labels(ir_node *block, void *env) {
665 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
666 pred = get_Block_cfgpred(block, n);
667 set_irn_link(pred, block);
672 * Main driver: generates code for one routine
674 void ppc32_gen_routine(const ppc32_code_gen_t *ppc32_cg, ir_graph *irg)
680 arch_env = cg->arch_env;
682 ppc32_register_emitters();
684 ppc32_emit_start(irg);
685 irg_block_walk_graph(irg, ppc32_gen_labels, NULL, NULL);
687 n = ARR_LEN(cg->blk_sched);
688 for (i = 0; i < n;) {
691 block = cg->blk_sched[i];
693 next_bl = i < n ? cg->blk_sched[i] : NULL;
695 /* set here the link. the emitter expects to find the next block here */
696 set_irn_link(block, next_bl);
697 ppc32_gen_block(block);