1 /* The main ppc backend driver file. */
8 #include "pseudo_irg.h"
19 #include "../bearch.h" /* the general register allocator interface */
20 #include "../benode_t.h"
21 #include "../belower.h"
22 #include "../besched_t.h"
25 #include "../bemachine.h"
26 #include "../bemodule.h"
27 #include "../beblocksched.h"
31 #include "bearch_ppc32_t.h"
33 #include "ppc32_new_nodes.h" /* ppc nodes interface */
34 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "ppc32_gen_decls.h" /* interface declaration emitter */
36 #include "ppc32_transform.h"
37 #include "ppc32_transform_conv.h"
38 #include "ppc32_emitter.h"
39 #include "ppc32_map_regs.h"
41 #define DEBUG_MODULE "firm.be.ppc.isa"
44 pset *symbol_pset = NULL;
46 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
47 static set *cur_reg_set = NULL;
49 /**************************************************
52 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
53 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
54 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
55 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
58 **************************************************/
60 static ir_node *my_skip_proj(const ir_node *n) {
67 * Return register requirements for a ppc node.
68 * If the node returns a tuple (mode_T) then the proj's
69 * will be asked for this information.
71 static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
72 const ppc32_register_req_t *irn_req;
73 long node_pos = pos == -1 ? 0 : pos;
74 ir_mode *mode = get_irn_mode(irn);
75 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
77 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
78 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
82 if (mode == mode_T && pos < 0) {
83 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
87 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
90 /* in case of a proj, we need to get the correct OUT slot */
91 /* of the node corresponding to the proj number */
93 node_pos = ppc32_translate_proj_pos(irn);
99 irn = my_skip_proj(irn);
101 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
104 /* get requirements for our own nodes */
105 if (is_ppc32_irn(irn)) {
107 irn_req = get_ppc32_in_req(irn, pos);
110 irn_req = get_ppc32_out_req(irn, node_pos);
113 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
115 memcpy(req, &(irn_req->req), sizeof(*req));
117 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
118 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
119 req->other_same = get_irn_n(irn, irn_req->same_pos);
122 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
123 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
124 req->other_different = get_irn_n(irn, irn_req->different_pos);
127 /* get requirements for FIRM nodes */
129 /* treat Phi like Const with default requirements */
131 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
133 if (mode_is_float(mode)) {
134 memcpy(req, &(ppc32_default_req_ppc32_fp.req), sizeof(*req));
136 else if (mode_is_int(mode) || mode_is_reference(mode)) {
137 memcpy(req, &(ppc32_default_req_ppc32_gp.req), sizeof(*req));
139 else if (mode == mode_T || mode == mode_M) {
140 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
144 assert(0 && "unsupported Phi-Mode");
148 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
156 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
161 if (get_irn_mode(irn) == mode_X) {
165 pos = ppc32_translate_proj_pos(irn);
166 irn = my_skip_proj(irn);
169 if (is_ppc32_irn(irn)) {
170 const arch_register_t **slots;
172 slots = get_ppc32_slots(irn);
176 /* here we set the registers for the Phi nodes */
177 ppc32_set_firm_reg(irn, reg, cur_reg_set);
181 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
183 const arch_register_t *reg = NULL;
187 if (get_irn_mode(irn) == mode_X) {
191 pos = ppc32_translate_proj_pos(irn);
192 irn = my_skip_proj(irn);
195 if (is_ppc32_irn(irn)) {
196 const arch_register_t **slots;
197 slots = get_ppc32_slots(irn);
201 reg = ppc32_get_firm_reg(irn, cur_reg_set);
207 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
208 irn = my_skip_proj(irn);
211 return arch_irn_class_branch;
213 else if (is_ppc32_irn(irn)) {
214 return arch_irn_class_normal;
220 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
221 irn = my_skip_proj(irn);
223 if (is_ppc32_irn(irn)) {
224 return get_ppc32_flags(irn);
226 else if (is_Unknown(irn)) {
227 return arch_irn_flags_ignore;
233 static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
234 if(!is_ppc32_irn(irn)) return NULL;
235 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
236 return get_ppc32_frame_entity(irn);
239 static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
240 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
242 set_ppc32_frame_entity(irn, ent);
246 * This function is called by the generic backend to correct offsets for
247 * nodes accessing the stack.
249 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
250 set_ppc32_offset(irn, bias);
253 static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
259 const be_abi_call_t *call;
264 * Initialize the callback object.
265 * @param call The call object.
266 * @param aenv The architecture environment.
267 * @param irg The graph with the method.
268 * @return Some pointer. This pointer is passed to all other callback functions as self object.
270 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
272 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
279 * Destroy the callback object.
280 * @param self The callback object.
282 static void ppc32_abi_done(void *self)
288 * Get the between type for that call.
289 * @param self The callback object.
290 * @return The between type of for that call.
292 static ir_type *ppc32_abi_get_between_type(void *self)
294 static ir_type *between_type = NULL;
295 static ir_entity *old_bp_ent = NULL;
298 ir_entity *ret_addr_ent;
299 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
300 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
302 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
303 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
304 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
306 set_entity_offset(old_bp_ent, 0);
307 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
308 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
315 * Put all registers which are saved by the prologue/epilogue in a set.
316 * @param self The callback object.
319 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
324 * Generate the prologue.
325 * @param self The callback object.
326 * @param mem A pointer to the mem node. Update this if you define new memory.
327 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
328 * @return The register which shall be used as a stack frame base.
330 * All nodes which define registers in @p reg_map must keep @p reg_map current.
332 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
334 ppc32_abi_env *env = (ppc32_abi_env *) self;
335 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
336 isleaf = flags.bits.irg_is_leaf;
338 if(flags.bits.try_omit_fp)
339 return &ppc32_gp_regs[REG_R1];
341 return &ppc32_gp_regs[REG_R31];
345 * Generate the epilogue.
346 * @param self The callback object.
347 * @param mem Memory one can attach to.
348 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
350 * All nodes which define registers in @p reg_map must keep @p reg_map current.
351 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
353 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
357 static const be_abi_callbacks_t ppc32_abi_callbacks = {
360 ppc32_abi_get_between_type,
361 ppc32_abi_regs_saved_by_me,
366 /* fill register allocator interface */
368 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
369 ppc32_get_irn_reg_req,
374 ppc32_get_frame_entity,
375 ppc32_set_frame_entity,
376 ppc32_set_stack_bias,
378 NULL, /* get_inverse */
379 NULL, /* get_op_estimated_cost */
380 NULL, /* possible_memory_operand */
381 NULL, /* perform_memory_operand */
384 ppc32_irn_ops_t ppc32_irn_ops = {
391 /**************************************************
394 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
395 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
396 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
397 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
400 **************************************************/
402 static void ppc32_before_abi(void *self) {
403 ppc32_code_gen_t *cg = self;
404 ir_type *frame_type = get_irg_frame_type(cg->irg);
406 frame_alloc_area(frame_type, 24, 4, 1);
408 ppc32_init_conv_walk();
409 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
412 if(cg->area_size < 32) cg->area_size = 32;
413 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
417 static void ppc32_search_start_successor(ir_node *block, void *env) {
418 ppc32_code_gen_t *cg = env;
419 int n = get_Block_n_cfgpreds(block);
420 ir_node *startblock = get_irg_start_block(cg->irg);
421 if(block == startblock) return;
423 for (n--; n >= 0; n--) {
424 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
425 if(predblock == startblock)
427 cg->start_succ_block = block;
434 * Transforms the standard firm graph into
437 static void ppc32_prepare_graph(void *self) {
438 ppc32_code_gen_t *cg = self;
440 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
441 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
442 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
444 ppc32_register_transformers();
445 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
446 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
447 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
453 * Called immediatly before emit phase.
455 static void ppc32_finish_irg(void *self) {
456 /* TODO: - fix offsets for nodes accessing stack
463 * These are some hooks which must be filled but are probably not needed.
465 static void ppc32_before_sched(void *self) {
466 /* Some stuff you need to do after scheduling but before register allocation */
470 * Called before the register allocator.
471 * Calculate a block schedule here. We need it for the x87
472 * simulator and the emitter.
474 static void ppc32_before_ra(void *self) {
475 ppc32_code_gen_t *cg = self;
476 cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
479 static void ppc32_transform_spill(ir_node *node, void *env)
481 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
483 if(be_is_Spill(node))
485 ir_node *store, *proj;
486 dbg_info *dbg = get_irn_dbg_info(node);
487 ir_node *block = get_nodes_block(node);
489 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
491 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
493 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
494 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
496 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
498 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
499 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
501 else assert(0 && "Spill for register class not supported yet!");
503 set_ppc32_frame_entity(store, be_get_frame_entity(node));
505 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
507 if (sched_is_scheduled(node)) {
508 sched_add_after(sched_prev(node), store);
509 sched_add_after(store, proj);
514 exchange(node, proj);
517 if(be_is_Reload(node))
519 ir_node *load, *proj;
520 const arch_register_t *reg;
521 dbg_info *dbg = get_irn_dbg_info(node);
522 ir_node *block = get_nodes_block(node);
523 ir_mode *mode = get_irn_mode(node);
525 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
527 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
529 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
531 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
533 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
535 else assert(0 && "Reload for register class not supported yet!");
537 set_ppc32_frame_entity(load, be_get_frame_entity(node));
539 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
541 if (sched_is_scheduled(node)) {
542 sched_add_after(sched_prev(node), load);
543 sched_add_after(load, proj);
548 /* copy the register from the old node to the new Load */
549 reg = arch_get_irn_register(cgenv->arch_env, node);
550 arch_set_irn_register(cgenv->arch_env, load, reg);
552 exchange(node, proj);
557 * Some stuff to do immediately after register allocation
559 static void ppc32_after_ra(void *self) {
560 ppc32_code_gen_t *cg = self;
561 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
565 * Emits the code, closes the output file and frees
566 * the code generator interface.
568 static void ppc32_emit_and_done(void *self) {
569 ppc32_code_gen_t *cg = self;
570 ir_graph *irg = cg->irg;
571 FILE *out = cg->isa->out;
573 if (cg->emit_decls) {
574 ppc32_gen_decls(out);
578 dump_ir_block_graph_sched(irg, "-ppc-finished");
579 ppc32_gen_routine(out, irg, cg);
583 /* de-allocate code generator */
584 del_set(cg->reg_set);
589 del_pset(symbol_pset);
594 int is_direct_entity(ir_entity *ent);
597 * Collects all SymConsts which need to be accessed "indirectly"
599 * @param node the firm node
600 * @param env the debug module
602 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
603 if(get_irn_op(node) == op_SymConst)
605 ir_entity *ent = get_SymConst_entity(node);
606 if(!is_direct_entity(ent))
607 pset_insert_ptr(symbol_pset, ent);
611 static void *ppc32_cg_init(be_irg_t *birg);
613 static const arch_code_generator_if_t ppc32_code_gen_if = {
618 ppc32_before_sched, /* before scheduling hook */
619 ppc32_before_ra, /* before register allocation hook */
626 * Initializes the code generator.
628 static void *ppc32_cg_init(be_irg_t *birg) {
629 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
630 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
632 cg->impl = &ppc32_code_gen_if;
634 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
635 cg->arch_env = birg->main_env->arch_env;
640 cg->start_succ_block = NULL;
641 cg->blk_sched = NULL;
642 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
646 if (isa->num_codegens > 1)
652 symbol_pset = pset_new_ptr(8);
653 for(i=0; i<get_irp_n_irgs(); i++)
655 cg->irg = get_irp_irg(i);
656 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
661 cur_reg_set = cg->reg_set;
663 ppc32_irn_ops.cg = cg;
665 return (arch_code_generator_t *)cg;
670 /*****************************************************************
671 * ____ _ _ _____ _____
672 * | _ \ | | | | |_ _|/ ____| /\
673 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
674 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
675 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
676 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
678 *****************************************************************/
680 static ppc32_isa_t ppc32_isa_template = {
682 &ppc32_gp_regs[REG_R1], // stack pointer
683 &ppc32_gp_regs[REG_R31], // base pointer
684 -1, // stack is decreasing
685 0, // num codegens... ??
690 * Initializes the backend ISA and opens the output file.
692 static void *ppc32_init(FILE *file_handle) {
693 static int inited = 0;
699 isa = xmalloc(sizeof(*isa));
700 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
702 isa->out = file_handle;
704 ppc32_register_init(isa);
705 ppc32_create_opcodes();
715 * Closes the output file and frees the ISA structure.
717 static void ppc32_done(void *self) {
723 static int ppc32_get_n_reg_class(const void *self) {
727 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
728 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
729 return &ppc32_reg_classes[i];
735 * Get the register class which shall be used to store a value of a given mode.
736 * @param self The this pointer.
737 * @param mode The mode in question.
738 * @return A register class which can hold values of the given mode.
740 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
741 if (mode_is_float(mode))
742 return &ppc32_reg_classes[CLASS_ppc32_fp];
744 return &ppc32_reg_classes[CLASS_ppc32_gp];
749 * Get the ABI restrictions for procedure calls.
750 * @param self The this pointer.
751 * @param method_type The type of the method (procedure) in question.
752 * @param abi The abi object to be modified
754 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
757 int i, n = get_method_n_params(method_type);
758 int stackoffs = 0, lastoffs = 0, stackparamsize;
763 const arch_register_t *reg;
764 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
766 if(get_type_visibility(method_type)!=visibility_external_allocated)
767 call_flags.bits.call_has_imm = 1;
769 /* set stack parameter passing style */
770 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
772 for (i = 0; i < n; i++) {
773 tp = get_method_param_type(method_type, i);
774 if(is_atomic_type(tp))
776 mode = get_type_mode(tp);
778 if(mode_is_float(mode))
780 if(fpregi <= REG_F13)
782 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
783 else gpregi += 2, stackparamsize=8; // mode == irm_D
784 reg = &ppc32_fp_regs[fpregi++];
788 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
789 else stackparamsize=8; // mode == irm_D
795 if(gpregi <= REG_R10)
796 reg = &ppc32_gp_regs[gpregi++];
803 be_abi_call_param_reg(abi, i, reg);
806 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
807 lastoffs = stackoffs+stackparamsize;
809 stackoffs += stackparamsize;
813 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
814 stackoffs += (get_type_size_bytes(tp)+3) & -4;
815 lastoffs = stackoffs;
819 /* explain where result can be found if any */
820 if (get_method_n_ress(method_type) > 0) {
821 tp = get_method_res_type(method_type, 0);
822 mode = get_type_mode(tp);
824 be_abi_call_res_reg(abi, 0,
825 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
829 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
830 return &ppc32_irn_ops;
833 const arch_irn_handler_t ppc32_irn_handler = {
837 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
838 return &ppc32_irn_handler;
841 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
842 return is_ppc32_irn(irn);
846 * Initializes the code generator interface.
848 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
849 return &ppc32_code_gen_if;
852 list_sched_selector_t ppc32_sched_selector;
855 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
857 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
858 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
859 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
860 return &ppc32_sched_selector;
863 static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
868 * Returns the necessary byte alignment for storing a register of given class.
870 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
871 ir_mode *mode = arch_register_class_mode(cls);
872 return get_mode_size_bytes(mode);
875 static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
881 static const be_machine_t *ppc32_get_machine(const void *self) {
888 * Return irp irgs in the desired order.
890 static ir_graph **ppc32_get_irg_list(const void *self, ir_graph **irg_list) {
895 * Returns the libFirm configuration parameter for this backend.
897 static const backend_params *ppc32_get_libfirm_params(void) {
898 static arch_dep_params_t ad = {
900 0, /* Muls are fast enough on ARM */
901 31, /* shift would be ok */
902 0, /* SMUL is needed, only in Arch M*/
903 0, /* UMUL is needed, only in Arch M */
904 32, /* SMUL & UMUL available for 32 bit */
906 static backend_params p = {
907 NULL, /* no additional opcodes */
908 NULL, /* will be set later */
909 1, /* need dword lowering */
910 NULL, /* but yet no creator function */
911 NULL, /* context for create_intrinsic_fkt */
918 const arch_isa_if_t ppc32_isa_if = {
921 ppc32_get_n_reg_class,
923 ppc32_get_reg_class_for_mode,
925 ppc32_get_irn_handler,
926 ppc32_get_code_generator_if,
927 ppc32_get_list_sched_selector,
928 ppc32_get_ilp_sched_selector,
929 ppc32_get_reg_class_alignment,
930 ppc32_get_libfirm_params,
931 ppc32_get_allowed_execution_units,
936 void be_init_arch_ppc32(void)
938 be_register_isa_if("ppc32", &ppc32_isa_if);
941 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);