1 /* The main ppc backend driver file. */
8 #include "pseudo_irg.h"
19 #include "../bearch.h" /* the general register allocator interface */
20 #include "../benode_t.h"
21 #include "../belower.h"
22 #include "../besched_t.h"
28 #include "bearch_ppc32_t.h"
30 #include "ppc32_new_nodes.h" /* ppc nodes interface */
31 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
32 #include "ppc32_gen_decls.h" /* interface declaration emitter */
33 #include "ppc32_transform.h"
34 #include "ppc32_transform_conv.h"
35 #include "ppc32_emitter.h"
36 #include "ppc32_map_regs.h"
38 #define DEBUG_MODULE "firm.be.ppc.isa"
41 pset *symbol_pset = NULL;
43 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
44 static set *cur_reg_set = NULL;
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
57 static ir_node *my_skip_proj(const ir_node *n) {
64 * Return register requirements for a ppc node.
65 * If the node returns a tuple (mode_T) then the proj's
66 * will be asked for this information.
68 static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
69 const ppc32_register_req_t *irn_req;
70 long node_pos = pos == -1 ? 0 : pos;
71 ir_mode *mode = get_irn_mode(irn);
72 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
74 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
75 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
79 if (mode == mode_T && pos < 0) {
80 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
84 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
87 /* in case of a proj, we need to get the correct OUT slot */
88 /* of the node corresponding to the proj number */
90 node_pos = ppc32_translate_proj_pos(irn);
96 irn = my_skip_proj(irn);
98 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
101 /* get requirements for our own nodes */
102 if (is_ppc32_irn(irn)) {
104 irn_req = get_ppc32_in_req(irn, pos);
107 irn_req = get_ppc32_out_req(irn, node_pos);
110 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
112 memcpy(req, &(irn_req->req), sizeof(*req));
114 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
115 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
116 req->other_same = get_irn_n(irn, irn_req->same_pos);
119 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
120 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
121 req->other_different = get_irn_n(irn, irn_req->different_pos);
124 /* get requirements for FIRM nodes */
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
130 if (mode_is_float(mode)) {
131 memcpy(req, &(ppc32_default_req_ppc32_fp.req), sizeof(*req));
133 else if (mode_is_int(mode) || mode_is_reference(mode)) {
134 memcpy(req, &(ppc32_default_req_ppc32_gp.req), sizeof(*req));
136 else if (mode == mode_T || mode == mode_M) {
137 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
141 assert(0 && "unsupported Phi-Mode");
145 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
153 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
158 if (get_irn_mode(irn) == mode_X) {
162 pos = ppc32_translate_proj_pos(irn);
163 irn = my_skip_proj(irn);
166 if (is_ppc32_irn(irn)) {
167 const arch_register_t **slots;
169 slots = get_ppc32_slots(irn);
173 /* here we set the registers for the Phi nodes */
174 ppc32_set_firm_reg(irn, reg, cur_reg_set);
178 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
180 const arch_register_t *reg = NULL;
184 if (get_irn_mode(irn) == mode_X) {
188 pos = ppc32_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_ppc32_irn(irn)) {
193 const arch_register_t **slots;
194 slots = get_ppc32_slots(irn);
198 reg = ppc32_get_firm_reg(irn, cur_reg_set);
204 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
205 irn = my_skip_proj(irn);
208 return arch_irn_class_branch;
210 else if (is_ppc32_irn(irn)) {
211 return arch_irn_class_normal;
217 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
218 irn = my_skip_proj(irn);
220 if (is_ppc32_irn(irn)) {
221 return get_ppc32_flags(irn);
223 else if (is_Unknown(irn)) {
224 return arch_irn_flags_ignore;
230 static entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
231 if(!is_ppc32_irn(irn)) return NULL;
232 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
233 return get_ppc32_frame_entity(irn);
236 static void ppc32_set_frame_entity(const void *self, const ir_node *irn, entity *ent) {
237 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
239 set_ppc32_frame_entity(irn, ent);
243 * This function is called by the generic backend to correct offsets for
244 * nodes accessing the stack.
246 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
247 set_ppc32_offset(irn, bias);
252 const be_abi_call_t *call;
257 * Initialize the callback object.
258 * @param call The call object.
259 * @param aenv The architecture environment.
260 * @param irg The graph with the method.
261 * @return Some pointer. This pointer is passed to all other callback functions as self object.
263 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
265 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
272 * Destroy the callback object.
273 * @param self The callback object.
275 static void ppc32_abi_done(void *self)
281 * Get the between type for that call.
282 * @param self The callback object.
283 * @return The between type of for that call.
285 static ir_type *ppc32_abi_get_between_type(void *self)
287 static ir_type *between_type = NULL;
288 static entity *old_bp_ent = NULL;
291 entity *ret_addr_ent;
292 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
293 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
295 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
296 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
297 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
299 set_entity_offset_bytes(old_bp_ent, 0);
300 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
301 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
308 * Put all registers which are saved by the prologue/epilogue in a set.
309 * @param self The callback object.
312 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
317 * Generate the prologue.
318 * @param self The callback object.
319 * @param mem A pointer to the mem node. Update this if you define new memory.
320 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
321 * @return The register which shall be used as a stack frame base.
323 * All nodes which define registers in @p reg_map must keep @p reg_map current.
325 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
327 ppc32_abi_env *env = (ppc32_abi_env *) self;
328 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
329 isleaf = flags.bits.irg_is_leaf;
331 if(flags.bits.try_omit_fp)
332 return &ppc32_gp_regs[REG_R1];
334 return &ppc32_gp_regs[REG_R31];
338 * Generate the epilogue.
339 * @param self The callback object.
340 * @param mem Memory one can attach to.
341 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
343 * All nodes which define registers in @p reg_map must keep @p reg_map current.
344 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
346 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
350 static const be_abi_callbacks_t ppc32_abi_callbacks = {
353 ppc32_abi_get_between_type,
354 ppc32_abi_regs_saved_by_me,
359 /* fill register allocator interface */
361 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
362 ppc32_get_irn_reg_req,
367 ppc32_get_frame_entity,
368 ppc32_set_frame_entity,
369 ppc32_set_stack_bias,
370 NULL, /* get_inverse */
371 NULL, /* get_op_estimated_cost */
372 NULL, /* possible_memory_operand */
373 NULL, /* perform_memory_operand */
376 ppc32_irn_ops_t ppc32_irn_ops = {
383 /**************************************************
386 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
387 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
388 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
389 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
392 **************************************************/
394 static void ppc32_before_abi(void *self) {
395 ppc32_code_gen_t *cg = self;
396 ir_type *frame_type = get_irg_frame_type(cg->irg);
398 frame_alloc_area(frame_type, 24, 4, 1);
400 ppc32_init_conv_walk();
401 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
404 if(cg->area_size < 32) cg->area_size = 32;
405 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
409 static void ppc32_search_start_successor(ir_node *block, void *env) {
410 ppc32_code_gen_t *cg = env;
411 int n = get_Block_n_cfgpreds(block);
412 ir_node *startblock = get_irg_start_block(cg->irg);
413 if(block == startblock) return;
415 for (n--; n >= 0; n--) {
416 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
417 if(predblock == startblock)
419 cg->start_succ_block = block;
426 * Transforms the standard firm graph into
429 static void ppc32_prepare_graph(void *self) {
430 ppc32_code_gen_t *cg = self;
432 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
433 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
434 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
436 ppc32_register_transformers();
437 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
438 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
439 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
445 * Called immediatly before emit phase.
447 static void ppc32_finish_irg(void *self) {
448 /* TODO: - fix offsets for nodes accessing stack
455 * These are some hooks which must be filled but are probably not needed.
457 static void ppc32_before_sched(void *self) {
458 /* Some stuff you need to do after scheduling but before register allocation */
462 * Called before the register allocator.
463 * Calculate a block schedule here. We need it for the x87
464 * simulator and the emitter.
466 static void ppc32_before_ra(void *self) {
467 ppc32_code_gen_t *cg = self;
468 cg->blk_sched = sched_create_block_schedule(cg->irg);
471 static void ppc32_transform_spill(ir_node *node, void *env)
473 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
475 if(be_is_Spill(node))
477 ir_node *store, *proj;
478 dbg_info *dbg = get_irn_dbg_info(node);
479 ir_node *block = get_nodes_block(node);
481 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
483 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
485 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
486 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
488 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
490 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
491 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
493 else assert(0 && "Spill for register class not supported yet!");
495 set_ppc32_frame_entity(store, be_get_frame_entity(node));
497 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
499 if (sched_is_scheduled(node)) {
500 sched_add_after(sched_prev(node), store);
501 sched_add_after(store, proj);
506 exchange(node, proj);
509 if(be_is_Reload(node))
511 ir_node *load, *proj;
512 const arch_register_t *reg;
513 dbg_info *dbg = get_irn_dbg_info(node);
514 ir_node *block = get_nodes_block(node);
515 ir_mode *mode = get_irn_mode(node);
517 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
519 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
521 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
523 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
525 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
527 else assert(0 && "Reload for register class not supported yet!");
529 set_ppc32_frame_entity(load, be_get_frame_entity(node));
531 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
533 if (sched_is_scheduled(node)) {
534 sched_add_after(sched_prev(node), load);
535 sched_add_after(load, proj);
540 /* copy the register from the old node to the new Load */
541 reg = arch_get_irn_register(cgenv->arch_env, node);
542 arch_set_irn_register(cgenv->arch_env, load, reg);
544 exchange(node, proj);
549 * Some stuff to do immediately after register allocation
551 static void ppc32_after_ra(void *self) {
552 ppc32_code_gen_t *cg = self;
553 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
557 * Emits the code, closes the output file and frees
558 * the code generator interface.
560 static void ppc32_emit_and_done(void *self) {
561 ppc32_code_gen_t *cg = self;
562 ir_graph *irg = cg->irg;
563 FILE *out = cg->isa->out;
565 if (cg->emit_decls) {
566 ppc32_gen_decls(out);
570 dump_ir_block_graph_sched(irg, "-ppc-finished");
571 ppc32_gen_routine(out, irg, cg);
575 /* de-allocate code generator */
576 del_set(cg->reg_set);
581 del_pset(symbol_pset);
586 int is_direct_entity(entity *ent);
589 * Collects all SymConsts which need to be accessed "indirectly"
591 * @param node the firm node
592 * @param env the debug module
594 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
595 if(get_irn_op(node) == op_SymConst)
597 entity *ent = get_SymConst_entity(node);
598 if(!is_direct_entity(ent))
599 pset_insert_ptr(symbol_pset, ent);
603 static void *ppc32_cg_init(const be_irg_t *birg);
605 static const arch_code_generator_if_t ppc32_code_gen_if = {
609 ppc32_before_sched, /* before scheduling hook */
610 ppc32_before_ra, /* before register allocation hook */
617 * Initializes the code generator.
619 static void *ppc32_cg_init(const be_irg_t *birg) {
620 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
621 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
623 cg->impl = &ppc32_code_gen_if;
625 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
626 cg->arch_env = birg->main_env->arch_env;
631 cg->start_succ_block = NULL;
632 cg->blk_sched = NULL;
633 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
637 if (isa->num_codegens > 1)
643 symbol_pset = pset_new_ptr(8);
644 for(i=0; i<get_irp_n_irgs(); i++)
646 cg->irg = get_irp_irg(i);
647 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
652 cur_reg_set = cg->reg_set;
654 ppc32_irn_ops.cg = cg;
656 return (arch_code_generator_t *)cg;
661 /*****************************************************************
662 * ____ _ _ _____ _____
663 * | _ \ | | | | |_ _|/ ____| /\
664 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
665 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
666 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
667 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
669 *****************************************************************/
671 static ppc32_isa_t ppc32_isa_template = {
673 &ppc32_gp_regs[REG_R1], // stack pointer
674 &ppc32_gp_regs[REG_R31], // base pointer
675 -1, // stack is decreasing
676 0, // num codegens... ??
681 * Initializes the backend ISA and opens the output file.
683 static void *ppc32_init(FILE *file_handle) {
684 static int inited = 0;
690 isa = xmalloc(sizeof(*isa));
691 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
693 isa->out = file_handle;
695 ppc32_register_init(isa);
696 ppc32_create_opcodes();
706 * Closes the output file and frees the ISA structure.
708 static void ppc32_done(void *self) {
714 static int ppc32_get_n_reg_class(const void *self) {
718 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
719 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
720 return &ppc32_reg_classes[i];
726 * Get the register class which shall be used to store a value of a given mode.
727 * @param self The this pointer.
728 * @param mode The mode in question.
729 * @return A register class which can hold values of the given mode.
731 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
732 if (mode_is_float(mode))
733 return &ppc32_reg_classes[CLASS_ppc32_fp];
735 return &ppc32_reg_classes[CLASS_ppc32_gp];
740 * Get the ABI restrictions for procedure calls.
741 * @param self The this pointer.
742 * @param method_type The type of the method (procedure) in question.
743 * @param abi The abi object to be modified
745 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
748 int i, n = get_method_n_params(method_type);
749 int stackoffs = 0, lastoffs = 0, stackparamsize;
754 const arch_register_t *reg;
755 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
757 if(get_type_visibility(method_type)!=visibility_external_allocated)
758 call_flags.bits.call_has_imm = 1;
760 /* set stack parameter passing style */
761 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
763 for (i = 0; i < n; i++) {
764 tp = get_method_param_type(method_type, i);
765 if(is_atomic_type(tp))
767 mode = get_type_mode(tp);
769 if(mode_is_float(mode))
771 if(fpregi <= REG_F13)
773 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
774 else gpregi += 2, stackparamsize=8; // mode == irm_D
775 reg = &ppc32_fp_regs[fpregi++];
779 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
780 else stackparamsize=8; // mode == irm_D
786 if(gpregi <= REG_R10)
787 reg = &ppc32_gp_regs[gpregi++];
794 be_abi_call_param_reg(abi, i, reg);
797 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
798 lastoffs = stackoffs+stackparamsize;
800 stackoffs += stackparamsize;
804 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
805 stackoffs += (get_type_size_bytes(tp)+3) & -4;
806 lastoffs = stackoffs;
810 /* explain where result can be found if any */
811 if (get_method_n_ress(method_type) > 0) {
812 tp = get_method_res_type(method_type, 0);
813 mode = get_type_mode(tp);
815 be_abi_call_res_reg(abi, 0,
816 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
820 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
821 return &ppc32_irn_ops;
824 const arch_irn_handler_t ppc32_irn_handler = {
828 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
829 return &ppc32_irn_handler;
832 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
833 return is_ppc32_irn(irn);
837 * Initializes the code generator interface.
839 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
840 return &ppc32_code_gen_if;
843 list_sched_selector_t ppc32_sched_selector;
846 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
848 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self) {
849 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
850 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
851 return &ppc32_sched_selector;
855 * Returns the necessary byte alignment for storing a register of given class.
857 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
858 ir_mode *mode = arch_register_class_mode(cls);
859 return get_mode_size_bytes(mode);
863 * Returns the libFirm configuration parameter for this backend.
865 static const backend_params *ppc32_get_libfirm_params(void) {
866 static arch_dep_params_t ad = {
868 0, /* Muls are fast enough on ARM */
869 31, /* shift would be ok */
870 0, /* SMUL is needed, only in Arch M*/
871 0, /* UMUL is needed, only in Arch M */
872 32, /* SMUL & UMUL available for 32 bit */
874 static backend_params p = {
875 NULL, /* no additional opcodes */
876 NULL, /* will be set later */
877 1, /* need dword lowering */
878 NULL, /* but yet no creator function */
879 NULL, /* context for create_intrinsic_fkt */
887 static void ppc32_register_options(lc_opt_entry_t *ent)
890 #endif /* WITH_LIBCORE */
892 const arch_isa_if_t ppc32_isa_if = {
895 ppc32_get_n_reg_class,
897 ppc32_get_reg_class_for_mode,
899 ppc32_get_irn_handler,
900 ppc32_get_code_generator_if,
901 ppc32_get_list_sched_selector,
902 ppc32_get_reg_class_alignment,
903 ppc32_get_libfirm_params,
905 ppc32_register_options