2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main ppc backend driver file.
23 * @author Moritz Kroll, Jens Mueller
30 #include "pseudo_irg.h"
41 #include "../bearch_t.h" /* the general register allocator interface */
42 #include "../benode_t.h"
43 #include "../belower.h"
44 #include "../besched_t.h"
47 #include "../bemachine.h"
48 #include "../bemodule.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
54 #include "bearch_ppc32_t.h"
56 #include "ppc32_new_nodes.h" /* ppc nodes interface */
57 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
58 #include "ppc32_gen_decls.h" /* interface declaration emitter */
59 #include "ppc32_transform.h"
60 #include "ppc32_transform_conv.h"
61 #include "ppc32_emitter.h"
62 #include "ppc32_map_regs.h"
64 #define DEBUG_MODULE "firm.be.ppc.isa"
67 pset *symbol_pset = NULL;
69 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
70 static set *cur_reg_set = NULL;
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
84 * Return register requirements for a ppc node.
85 * If the node returns a tuple (mode_T) then the proj's
86 * will be asked for this information.
89 arch_register_req_t *ppc32_get_irn_reg_req(const void *self,
90 const ir_node *irn, int pos) {
91 long node_pos = pos == -1 ? 0 : pos;
92 ir_mode *mode = get_irn_mode(irn);
93 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
95 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
96 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
102 return arch_no_register_req;
105 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
108 /* in case of a proj, we need to get the correct OUT slot */
109 /* of the node corresponding to the proj number */
111 node_pos = ppc32_translate_proj_pos(irn);
116 irn = skip_Proj_const(irn);
118 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
121 /* get requirements for our own nodes */
122 if (is_ppc32_irn(irn)) {
123 const arch_register_req_t *req;
125 req = get_ppc32_in_req(irn, pos);
127 req = get_ppc32_out_req(irn, node_pos);
130 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
134 /* unknowns should be transformed by now */
135 assert(!is_Unknown(irn));
137 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
138 return arch_no_register_req;
141 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
146 if (get_irn_mode(irn) == mode_X) {
150 pos = ppc32_translate_proj_pos(irn);
151 irn = skip_Proj(irn);
154 if (is_ppc32_irn(irn)) {
155 const arch_register_t **slots;
157 slots = get_ppc32_slots(irn);
161 /* here we set the registers for the Phi nodes */
162 ppc32_set_firm_reg(irn, reg, cur_reg_set);
166 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
168 const arch_register_t *reg = NULL;
172 if (get_irn_mode(irn) == mode_X) {
176 pos = ppc32_translate_proj_pos(irn);
177 irn = skip_Proj_const(irn);
180 if (is_ppc32_irn(irn)) {
181 const arch_register_t **slots;
182 slots = get_ppc32_slots(irn);
186 reg = ppc32_get_firm_reg(irn, cur_reg_set);
192 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
193 irn = skip_Proj_const(irn);
196 return arch_irn_class_branch;
198 else if (is_ppc32_irn(irn)) {
199 return arch_irn_class_normal;
205 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
206 irn = skip_Proj_const(irn);
208 if (is_ppc32_irn(irn)) {
209 return get_ppc32_flags(irn);
211 else if (is_Unknown(irn)) {
212 return arch_irn_flags_ignore;
218 static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
219 if(!is_ppc32_irn(irn)) return NULL;
220 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
221 return get_ppc32_frame_entity(irn);
224 static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
225 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
227 set_ppc32_frame_entity(irn, ent);
231 * This function is called by the generic backend to correct offsets for
232 * nodes accessing the stack.
234 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
235 set_ppc32_offset(irn, bias);
238 static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
244 const be_abi_call_t *call;
249 * Initialize the callback object.
250 * @param call The call object.
251 * @param aenv The architecture environment.
252 * @param irg The graph with the method.
253 * @return Some pointer. This pointer is passed to all other callback functions as self object.
255 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
257 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
264 * Destroy the callback object.
265 * @param self The callback object.
267 static void ppc32_abi_done(void *self)
273 * Get the between type for that call.
274 * @param self The callback object.
275 * @return The between type of for that call.
277 static ir_type *ppc32_abi_get_between_type(void *self)
279 static ir_type *between_type = NULL;
280 static ir_entity *old_bp_ent = NULL;
283 ir_entity *ret_addr_ent;
284 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
285 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
287 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
288 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
289 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
291 set_entity_offset(old_bp_ent, 0);
292 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
293 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
300 * Put all registers which are saved by the prologue/epilogue in a set.
301 * @param self The callback object.
304 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
309 * Generate the prologue.
310 * @param self The callback object.
311 * @param mem A pointer to the mem node. Update this if you define new memory.
312 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
313 * @return The register which shall be used as a stack frame base.
315 * All nodes which define registers in @p reg_map must keep @p reg_map current.
317 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
319 ppc32_abi_env *env = (ppc32_abi_env *) self;
320 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
321 isleaf = flags.bits.irg_is_leaf;
323 if(flags.bits.try_omit_fp)
324 return &ppc32_gp_regs[REG_R1];
326 return &ppc32_gp_regs[REG_R31];
330 * Generate the epilogue.
331 * @param self The callback object.
332 * @param mem Memory one can attach to.
333 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
335 * All nodes which define registers in @p reg_map must keep @p reg_map current.
336 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
338 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
342 static const be_abi_callbacks_t ppc32_abi_callbacks = {
345 ppc32_abi_get_between_type,
346 ppc32_abi_regs_saved_by_me,
351 /* fill register allocator interface */
353 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
354 ppc32_get_irn_reg_req,
359 ppc32_get_frame_entity,
360 ppc32_set_frame_entity,
361 ppc32_set_stack_bias,
363 NULL, /* get_inverse */
364 NULL, /* get_op_estimated_cost */
365 NULL, /* possible_memory_operand */
366 NULL, /* perform_memory_operand */
369 ppc32_irn_ops_t ppc32_irn_ops = {
376 /**************************************************
379 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
380 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
381 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
382 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
385 **************************************************/
387 static void ppc32_before_abi(void *self) {
388 ppc32_code_gen_t *cg = self;
389 ir_type *frame_type = get_irg_frame_type(cg->irg);
391 frame_alloc_area(frame_type, 24, 4, 1);
393 ppc32_init_conv_walk();
394 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
397 if(cg->area_size < 32) cg->area_size = 32;
398 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
402 static void ppc32_search_start_successor(ir_node *block, void *env) {
403 ppc32_code_gen_t *cg = env;
404 int n = get_Block_n_cfgpreds(block);
405 ir_node *startblock = get_irg_start_block(cg->irg);
406 if(block == startblock) return;
408 for (n--; n >= 0; n--) {
409 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
410 if(predblock == startblock)
412 cg->start_succ_block = block;
419 * Transforms the standard firm graph into
422 static void ppc32_prepare_graph(void *self) {
423 ppc32_code_gen_t *cg = self;
425 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
426 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
427 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
429 ppc32_register_transformers();
430 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
431 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
432 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
438 * Called immediatly before emit phase.
440 static void ppc32_finish_irg(void *self) {
441 /* TODO: - fix offsets for nodes accessing stack
448 * These are some hooks which must be filled but are probably not needed.
450 static void ppc32_before_sched(void *self) {
451 /* Some stuff you need to do after scheduling but before register allocation */
455 * Called before the register allocator.
456 * Calculate a block schedule here. We need it for the x87
457 * simulator and the emitter.
459 static void ppc32_before_ra(void *self) {
460 ppc32_code_gen_t *cg = self;
461 cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
464 static void ppc32_transform_spill(ir_node *node, void *env)
466 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
468 if(be_is_Spill(node))
470 ir_node *store, *proj;
471 dbg_info *dbg = get_irn_dbg_info(node);
472 ir_node *block = get_nodes_block(node);
474 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
476 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
478 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
479 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
481 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
483 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
484 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
486 else assert(0 && "Spill for register class not supported yet!");
488 set_ppc32_frame_entity(store, be_get_frame_entity(node));
490 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
492 if (sched_is_scheduled(node)) {
493 sched_add_after(sched_prev(node), store);
494 sched_add_after(store, proj);
499 exchange(node, proj);
502 if(be_is_Reload(node))
504 ir_node *load, *proj;
505 const arch_register_t *reg;
506 dbg_info *dbg = get_irn_dbg_info(node);
507 ir_node *block = get_nodes_block(node);
508 ir_mode *mode = get_irn_mode(node);
510 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
512 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
514 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
516 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
518 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
520 else assert(0 && "Reload for register class not supported yet!");
522 set_ppc32_frame_entity(load, be_get_frame_entity(node));
524 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
526 if (sched_is_scheduled(node)) {
527 sched_add_after(sched_prev(node), load);
528 sched_add_after(load, proj);
533 /* copy the register from the old node to the new Load */
534 reg = arch_get_irn_register(cgenv->arch_env, node);
535 arch_set_irn_register(cgenv->arch_env, load, reg);
537 exchange(node, proj);
542 * Some stuff to do immediately after register allocation
544 static void ppc32_after_ra(void *self) {
545 ppc32_code_gen_t *cg = self;
546 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
550 * Emits the code, closes the output file and frees
551 * the code generator interface.
553 static void ppc32_emit_and_done(void *self) {
554 ppc32_code_gen_t *cg = self;
555 ir_graph *irg = cg->irg;
556 FILE *out = cg->isa->out;
558 if (cg->emit_decls) {
559 ppc32_gen_decls(out);
563 dump_ir_block_graph_sched(irg, "-ppc-finished");
564 ppc32_gen_routine(out, irg, cg);
568 /* de-allocate code generator */
569 del_set(cg->reg_set);
574 del_pset(symbol_pset);
579 int is_direct_entity(ir_entity *ent);
582 * Collects all SymConsts which need to be accessed "indirectly"
584 * @param node the firm node
585 * @param env the debug module
587 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
588 if(get_irn_op(node) == op_SymConst)
590 ir_entity *ent = get_SymConst_entity(node);
591 if(!is_direct_entity(ent))
592 pset_insert_ptr(symbol_pset, ent);
596 static void *ppc32_cg_init(be_irg_t *birg);
598 static const arch_code_generator_if_t ppc32_code_gen_if = {
603 ppc32_before_sched, /* before scheduling hook */
604 ppc32_before_ra, /* before register allocation hook */
611 * Initializes the code generator.
613 static void *ppc32_cg_init(be_irg_t *birg) {
614 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
615 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
617 cg->impl = &ppc32_code_gen_if;
619 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
620 cg->arch_env = birg->main_env->arch_env;
625 cg->start_succ_block = NULL;
626 cg->blk_sched = NULL;
627 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
631 if (isa->num_codegens > 1)
637 symbol_pset = pset_new_ptr(8);
638 for(i=0; i<get_irp_n_irgs(); i++)
640 cg->irg = get_irp_irg(i);
641 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
646 cur_reg_set = cg->reg_set;
648 ppc32_irn_ops.cg = cg;
650 return (arch_code_generator_t *)cg;
655 /*****************************************************************
656 * ____ _ _ _____ _____
657 * | _ \ | | | | |_ _|/ ____| /\
658 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
659 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
660 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
661 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
663 *****************************************************************/
665 static ppc32_isa_t ppc32_isa_template = {
667 &ppc32_gp_regs[REG_R1], // stack pointer
668 &ppc32_gp_regs[REG_R31], // base pointer
669 -1, // stack is decreasing
670 0, // num codegens... ??
675 * Initializes the backend ISA and opens the output file.
677 static void *ppc32_init(FILE *file_handle) {
678 static int inited = 0;
684 isa = xmalloc(sizeof(*isa));
685 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
687 isa->out = file_handle;
689 ppc32_register_init(isa);
690 ppc32_create_opcodes();
700 * Closes the output file and frees the ISA structure.
702 static void ppc32_done(void *self) {
708 static int ppc32_get_n_reg_class(const void *self) {
712 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
713 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
714 return &ppc32_reg_classes[i];
720 * Get the register class which shall be used to store a value of a given mode.
721 * @param self The this pointer.
722 * @param mode The mode in question.
723 * @return A register class which can hold values of the given mode.
725 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
726 if (mode_is_float(mode))
727 return &ppc32_reg_classes[CLASS_ppc32_fp];
729 return &ppc32_reg_classes[CLASS_ppc32_gp];
734 * Get the ABI restrictions for procedure calls.
735 * @param self The this pointer.
736 * @param method_type The type of the method (procedure) in question.
737 * @param abi The abi object to be modified
739 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
742 int i, n = get_method_n_params(method_type);
743 int stackoffs = 0, lastoffs = 0, stackparamsize;
748 const arch_register_t *reg;
749 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
751 if(get_type_visibility(method_type)!=visibility_external_allocated)
752 call_flags.bits.call_has_imm = 1;
754 /* set stack parameter passing style */
755 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
757 for (i = 0; i < n; i++) {
758 tp = get_method_param_type(method_type, i);
759 if(is_atomic_type(tp))
761 mode = get_type_mode(tp);
763 if(mode_is_float(mode))
765 if(fpregi <= REG_F13)
767 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
768 else gpregi += 2, stackparamsize=8; // mode == irm_D
769 reg = &ppc32_fp_regs[fpregi++];
773 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
774 else stackparamsize=8; // mode == irm_D
780 if(gpregi <= REG_R10)
781 reg = &ppc32_gp_regs[gpregi++];
788 be_abi_call_param_reg(abi, i, reg);
791 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
792 lastoffs = stackoffs+stackparamsize;
794 stackoffs += stackparamsize;
798 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
799 stackoffs += (get_type_size_bytes(tp)+3) & -4;
800 lastoffs = stackoffs;
804 /* explain where result can be found if any */
805 if (get_method_n_ress(method_type) > 0) {
806 tp = get_method_res_type(method_type, 0);
807 mode = get_type_mode(tp);
809 be_abi_call_res_reg(abi, 0,
810 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
814 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
815 return &ppc32_irn_ops;
818 const arch_irn_handler_t ppc32_irn_handler = {
822 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
823 return &ppc32_irn_handler;
826 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
827 return is_ppc32_irn(irn);
831 * Initializes the code generator interface.
833 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
834 return &ppc32_code_gen_if;
837 list_sched_selector_t ppc32_sched_selector;
840 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
842 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
843 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
844 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
845 return &ppc32_sched_selector;
848 static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
853 * Returns the necessary byte alignment for storing a register of given class.
855 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
856 ir_mode *mode = arch_register_class_mode(cls);
857 return get_mode_size_bytes(mode);
860 static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
866 static const be_machine_t *ppc32_get_machine(const void *self) {
873 * Return irp irgs in the desired order.
875 static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) {
880 * Returns the libFirm configuration parameter for this backend.
882 static const backend_params *ppc32_get_libfirm_params(void) {
883 static arch_dep_params_t ad = {
885 0, /* Muls are fast enough on ARM */
886 31, /* shift would be ok */
887 0, /* SMUL is needed, only in Arch M*/
888 0, /* UMUL is needed, only in Arch M */
889 32, /* SMUL & UMUL available for 32 bit */
891 static backend_params p = {
892 NULL, /* no additional opcodes */
893 NULL, /* will be set later */
894 1, /* need dword lowering */
895 NULL, /* but yet no creator function */
896 NULL, /* context for create_intrinsic_fkt */
903 const arch_isa_if_t ppc32_isa_if = {
906 ppc32_get_n_reg_class,
908 ppc32_get_reg_class_for_mode,
910 ppc32_get_irn_handler,
911 ppc32_get_code_generator_if,
912 ppc32_get_list_sched_selector,
913 ppc32_get_ilp_sched_selector,
914 ppc32_get_reg_class_alignment,
915 ppc32_get_libfirm_params,
916 ppc32_get_allowed_execution_units,
921 void be_init_arch_ppc32(void)
923 be_register_isa_if("ppc32", &ppc32_isa_if);
926 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);