2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 /* The main ppc backend driver file. */
26 #include "pseudo_irg.h"
37 #include "../bearch_t.h" /* the general register allocator interface */
38 #include "../benode_t.h"
39 #include "../belower.h"
40 #include "../besched_t.h"
43 #include "../bemachine.h"
44 #include "../bemodule.h"
45 #include "../beblocksched.h"
46 #include "../beirg_t.h"
50 #include "bearch_ppc32_t.h"
52 #include "ppc32_new_nodes.h" /* ppc nodes interface */
53 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
54 #include "ppc32_gen_decls.h" /* interface declaration emitter */
55 #include "ppc32_transform.h"
56 #include "ppc32_transform_conv.h"
57 #include "ppc32_emitter.h"
58 #include "ppc32_map_regs.h"
60 #define DEBUG_MODULE "firm.be.ppc.isa"
63 pset *symbol_pset = NULL;
65 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
66 static set *cur_reg_set = NULL;
68 /**************************************************
71 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
72 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
73 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
74 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
77 **************************************************/
80 * Return register requirements for a ppc node.
81 * If the node returns a tuple (mode_T) then the proj's
82 * will be asked for this information.
85 arch_register_req_t *ppc32_get_irn_reg_req(const void *self,
86 const ir_node *irn, int pos) {
87 long node_pos = pos == -1 ? 0 : pos;
88 ir_mode *mode = get_irn_mode(irn);
89 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
91 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
92 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
93 return arch_no_register_req;
96 if (mode == mode_T && pos < 0) {
97 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
98 return arch_no_register_req;
101 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
104 /* in case of a proj, we need to get the correct OUT slot */
105 /* of the node corresponding to the proj number */
107 node_pos = ppc32_translate_proj_pos(irn);
112 irn = skip_Proj_const(irn);
114 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
117 /* get requirements for our own nodes */
118 if (is_ppc32_irn(irn)) {
119 const arch_register_req_t *req;
121 req = get_ppc32_in_req(irn, pos);
123 req = get_ppc32_out_req(irn, node_pos);
126 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
130 /* unknowns should be transformed by now */
131 assert(!is_Unknown(irn));
133 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
134 return arch_no_register_req;
137 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
142 if (get_irn_mode(irn) == mode_X) {
146 pos = ppc32_translate_proj_pos(irn);
147 irn = skip_Proj(irn);
150 if (is_ppc32_irn(irn)) {
151 const arch_register_t **slots;
153 slots = get_ppc32_slots(irn);
157 /* here we set the registers for the Phi nodes */
158 ppc32_set_firm_reg(irn, reg, cur_reg_set);
162 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
164 const arch_register_t *reg = NULL;
168 if (get_irn_mode(irn) == mode_X) {
172 pos = ppc32_translate_proj_pos(irn);
173 irn = skip_Proj_const(irn);
176 if (is_ppc32_irn(irn)) {
177 const arch_register_t **slots;
178 slots = get_ppc32_slots(irn);
182 reg = ppc32_get_firm_reg(irn, cur_reg_set);
188 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
189 irn = skip_Proj_const(irn);
192 return arch_irn_class_branch;
194 else if (is_ppc32_irn(irn)) {
195 return arch_irn_class_normal;
201 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
202 irn = skip_Proj_const(irn);
204 if (is_ppc32_irn(irn)) {
205 return get_ppc32_flags(irn);
207 else if (is_Unknown(irn)) {
208 return arch_irn_flags_ignore;
214 static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
215 if(!is_ppc32_irn(irn)) return NULL;
216 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
217 return get_ppc32_frame_entity(irn);
220 static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
221 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
223 set_ppc32_frame_entity(irn, ent);
227 * This function is called by the generic backend to correct offsets for
228 * nodes accessing the stack.
230 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
231 set_ppc32_offset(irn, bias);
234 static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
240 const be_abi_call_t *call;
245 * Initialize the callback object.
246 * @param call The call object.
247 * @param aenv The architecture environment.
248 * @param irg The graph with the method.
249 * @return Some pointer. This pointer is passed to all other callback functions as self object.
251 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
253 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
260 * Destroy the callback object.
261 * @param self The callback object.
263 static void ppc32_abi_done(void *self)
269 * Get the between type for that call.
270 * @param self The callback object.
271 * @return The between type of for that call.
273 static ir_type *ppc32_abi_get_between_type(void *self)
275 static ir_type *between_type = NULL;
276 static ir_entity *old_bp_ent = NULL;
279 ir_entity *ret_addr_ent;
280 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
281 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
283 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
284 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
285 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
287 set_entity_offset(old_bp_ent, 0);
288 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
289 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
296 * Put all registers which are saved by the prologue/epilogue in a set.
297 * @param self The callback object.
300 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
305 * Generate the prologue.
306 * @param self The callback object.
307 * @param mem A pointer to the mem node. Update this if you define new memory.
308 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
309 * @return The register which shall be used as a stack frame base.
311 * All nodes which define registers in @p reg_map must keep @p reg_map current.
313 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
315 ppc32_abi_env *env = (ppc32_abi_env *) self;
316 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
317 isleaf = flags.bits.irg_is_leaf;
319 if(flags.bits.try_omit_fp)
320 return &ppc32_gp_regs[REG_R1];
322 return &ppc32_gp_regs[REG_R31];
326 * Generate the epilogue.
327 * @param self The callback object.
328 * @param mem Memory one can attach to.
329 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
331 * All nodes which define registers in @p reg_map must keep @p reg_map current.
332 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
334 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
338 static const be_abi_callbacks_t ppc32_abi_callbacks = {
341 ppc32_abi_get_between_type,
342 ppc32_abi_regs_saved_by_me,
347 /* fill register allocator interface */
349 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
350 ppc32_get_irn_reg_req,
355 ppc32_get_frame_entity,
356 ppc32_set_frame_entity,
357 ppc32_set_stack_bias,
359 NULL, /* get_inverse */
360 NULL, /* get_op_estimated_cost */
361 NULL, /* possible_memory_operand */
362 NULL, /* perform_memory_operand */
365 ppc32_irn_ops_t ppc32_irn_ops = {
372 /**************************************************
375 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
376 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
377 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
378 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
381 **************************************************/
383 static void ppc32_before_abi(void *self) {
384 ppc32_code_gen_t *cg = self;
385 ir_type *frame_type = get_irg_frame_type(cg->irg);
387 frame_alloc_area(frame_type, 24, 4, 1);
389 ppc32_init_conv_walk();
390 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
393 if(cg->area_size < 32) cg->area_size = 32;
394 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
398 static void ppc32_search_start_successor(ir_node *block, void *env) {
399 ppc32_code_gen_t *cg = env;
400 int n = get_Block_n_cfgpreds(block);
401 ir_node *startblock = get_irg_start_block(cg->irg);
402 if(block == startblock) return;
404 for (n--; n >= 0; n--) {
405 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
406 if(predblock == startblock)
408 cg->start_succ_block = block;
415 * Transforms the standard firm graph into
418 static void ppc32_prepare_graph(void *self) {
419 ppc32_code_gen_t *cg = self;
421 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
422 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
423 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
425 ppc32_register_transformers();
426 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
427 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
428 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
434 * Called immediatly before emit phase.
436 static void ppc32_finish_irg(void *self) {
437 /* TODO: - fix offsets for nodes accessing stack
444 * These are some hooks which must be filled but are probably not needed.
446 static void ppc32_before_sched(void *self) {
447 /* Some stuff you need to do after scheduling but before register allocation */
451 * Called before the register allocator.
452 * Calculate a block schedule here. We need it for the x87
453 * simulator and the emitter.
455 static void ppc32_before_ra(void *self) {
456 ppc32_code_gen_t *cg = self;
457 cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
460 static void ppc32_transform_spill(ir_node *node, void *env)
462 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
464 if(be_is_Spill(node))
466 ir_node *store, *proj;
467 dbg_info *dbg = get_irn_dbg_info(node);
468 ir_node *block = get_nodes_block(node);
470 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
472 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
474 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
475 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
477 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
479 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
480 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
482 else assert(0 && "Spill for register class not supported yet!");
484 set_ppc32_frame_entity(store, be_get_frame_entity(node));
486 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
488 if (sched_is_scheduled(node)) {
489 sched_add_after(sched_prev(node), store);
490 sched_add_after(store, proj);
495 exchange(node, proj);
498 if(be_is_Reload(node))
500 ir_node *load, *proj;
501 const arch_register_t *reg;
502 dbg_info *dbg = get_irn_dbg_info(node);
503 ir_node *block = get_nodes_block(node);
504 ir_mode *mode = get_irn_mode(node);
506 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
508 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
510 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
512 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
514 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
516 else assert(0 && "Reload for register class not supported yet!");
518 set_ppc32_frame_entity(load, be_get_frame_entity(node));
520 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
522 if (sched_is_scheduled(node)) {
523 sched_add_after(sched_prev(node), load);
524 sched_add_after(load, proj);
529 /* copy the register from the old node to the new Load */
530 reg = arch_get_irn_register(cgenv->arch_env, node);
531 arch_set_irn_register(cgenv->arch_env, load, reg);
533 exchange(node, proj);
538 * Some stuff to do immediately after register allocation
540 static void ppc32_after_ra(void *self) {
541 ppc32_code_gen_t *cg = self;
542 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
546 * Emits the code, closes the output file and frees
547 * the code generator interface.
549 static void ppc32_emit_and_done(void *self) {
550 ppc32_code_gen_t *cg = self;
551 ir_graph *irg = cg->irg;
552 FILE *out = cg->isa->out;
554 if (cg->emit_decls) {
555 ppc32_gen_decls(out);
559 dump_ir_block_graph_sched(irg, "-ppc-finished");
560 ppc32_gen_routine(out, irg, cg);
564 /* de-allocate code generator */
565 del_set(cg->reg_set);
570 del_pset(symbol_pset);
575 int is_direct_entity(ir_entity *ent);
578 * Collects all SymConsts which need to be accessed "indirectly"
580 * @param node the firm node
581 * @param env the debug module
583 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
584 if(get_irn_op(node) == op_SymConst)
586 ir_entity *ent = get_SymConst_entity(node);
587 if(!is_direct_entity(ent))
588 pset_insert_ptr(symbol_pset, ent);
592 static void *ppc32_cg_init(be_irg_t *birg);
594 static const arch_code_generator_if_t ppc32_code_gen_if = {
599 ppc32_before_sched, /* before scheduling hook */
600 ppc32_before_ra, /* before register allocation hook */
607 * Initializes the code generator.
609 static void *ppc32_cg_init(be_irg_t *birg) {
610 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
611 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
613 cg->impl = &ppc32_code_gen_if;
615 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
616 cg->arch_env = birg->main_env->arch_env;
621 cg->start_succ_block = NULL;
622 cg->blk_sched = NULL;
623 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
627 if (isa->num_codegens > 1)
633 symbol_pset = pset_new_ptr(8);
634 for(i=0; i<get_irp_n_irgs(); i++)
636 cg->irg = get_irp_irg(i);
637 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
642 cur_reg_set = cg->reg_set;
644 ppc32_irn_ops.cg = cg;
646 return (arch_code_generator_t *)cg;
651 /*****************************************************************
652 * ____ _ _ _____ _____
653 * | _ \ | | | | |_ _|/ ____| /\
654 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
655 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
656 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
657 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
659 *****************************************************************/
661 static ppc32_isa_t ppc32_isa_template = {
663 &ppc32_gp_regs[REG_R1], // stack pointer
664 &ppc32_gp_regs[REG_R31], // base pointer
665 -1, // stack is decreasing
666 0, // num codegens... ??
671 * Initializes the backend ISA and opens the output file.
673 static void *ppc32_init(FILE *file_handle) {
674 static int inited = 0;
680 isa = xmalloc(sizeof(*isa));
681 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
683 isa->out = file_handle;
685 ppc32_register_init(isa);
686 ppc32_create_opcodes();
696 * Closes the output file and frees the ISA structure.
698 static void ppc32_done(void *self) {
704 static int ppc32_get_n_reg_class(const void *self) {
708 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
709 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
710 return &ppc32_reg_classes[i];
716 * Get the register class which shall be used to store a value of a given mode.
717 * @param self The this pointer.
718 * @param mode The mode in question.
719 * @return A register class which can hold values of the given mode.
721 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
722 if (mode_is_float(mode))
723 return &ppc32_reg_classes[CLASS_ppc32_fp];
725 return &ppc32_reg_classes[CLASS_ppc32_gp];
730 * Get the ABI restrictions for procedure calls.
731 * @param self The this pointer.
732 * @param method_type The type of the method (procedure) in question.
733 * @param abi The abi object to be modified
735 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
738 int i, n = get_method_n_params(method_type);
739 int stackoffs = 0, lastoffs = 0, stackparamsize;
744 const arch_register_t *reg;
745 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
747 if(get_type_visibility(method_type)!=visibility_external_allocated)
748 call_flags.bits.call_has_imm = 1;
750 /* set stack parameter passing style */
751 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
753 for (i = 0; i < n; i++) {
754 tp = get_method_param_type(method_type, i);
755 if(is_atomic_type(tp))
757 mode = get_type_mode(tp);
759 if(mode_is_float(mode))
761 if(fpregi <= REG_F13)
763 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
764 else gpregi += 2, stackparamsize=8; // mode == irm_D
765 reg = &ppc32_fp_regs[fpregi++];
769 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
770 else stackparamsize=8; // mode == irm_D
776 if(gpregi <= REG_R10)
777 reg = &ppc32_gp_regs[gpregi++];
784 be_abi_call_param_reg(abi, i, reg);
787 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
788 lastoffs = stackoffs+stackparamsize;
790 stackoffs += stackparamsize;
794 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
795 stackoffs += (get_type_size_bytes(tp)+3) & -4;
796 lastoffs = stackoffs;
800 /* explain where result can be found if any */
801 if (get_method_n_ress(method_type) > 0) {
802 tp = get_method_res_type(method_type, 0);
803 mode = get_type_mode(tp);
805 be_abi_call_res_reg(abi, 0,
806 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
810 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
811 return &ppc32_irn_ops;
814 const arch_irn_handler_t ppc32_irn_handler = {
818 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
819 return &ppc32_irn_handler;
822 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
823 return is_ppc32_irn(irn);
827 * Initializes the code generator interface.
829 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
830 return &ppc32_code_gen_if;
833 list_sched_selector_t ppc32_sched_selector;
836 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
838 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
839 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
840 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
841 return &ppc32_sched_selector;
844 static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
849 * Returns the necessary byte alignment for storing a register of given class.
851 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
852 ir_mode *mode = arch_register_class_mode(cls);
853 return get_mode_size_bytes(mode);
856 static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
862 static const be_machine_t *ppc32_get_machine(const void *self) {
869 * Return irp irgs in the desired order.
871 static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) {
876 * Returns the libFirm configuration parameter for this backend.
878 static const backend_params *ppc32_get_libfirm_params(void) {
879 static arch_dep_params_t ad = {
881 0, /* Muls are fast enough on ARM */
882 31, /* shift would be ok */
883 0, /* SMUL is needed, only in Arch M*/
884 0, /* UMUL is needed, only in Arch M */
885 32, /* SMUL & UMUL available for 32 bit */
887 static backend_params p = {
888 NULL, /* no additional opcodes */
889 NULL, /* will be set later */
890 1, /* need dword lowering */
891 NULL, /* but yet no creator function */
892 NULL, /* context for create_intrinsic_fkt */
899 const arch_isa_if_t ppc32_isa_if = {
902 ppc32_get_n_reg_class,
904 ppc32_get_reg_class_for_mode,
906 ppc32_get_irn_handler,
907 ppc32_get_code_generator_if,
908 ppc32_get_list_sched_selector,
909 ppc32_get_ilp_sched_selector,
910 ppc32_get_reg_class_alignment,
911 ppc32_get_libfirm_params,
912 ppc32_get_allowed_execution_units,
917 void be_init_arch_ppc32(void)
919 be_register_isa_if("ppc32", &ppc32_isa_if);
922 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);