1 /* The main ppc backend driver file. */
8 #include "pseudo_irg.h"
19 #include "../bearch.h" /* the general register allocator interface */
20 #include "../benode_t.h"
21 #include "../belower.h"
22 #include "../besched_t.h"
25 #include "../bemachine.h"
29 #include "bearch_ppc32_t.h"
31 #include "ppc32_new_nodes.h" /* ppc nodes interface */
32 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
33 #include "ppc32_gen_decls.h" /* interface declaration emitter */
34 #include "ppc32_transform.h"
35 #include "ppc32_transform_conv.h"
36 #include "ppc32_emitter.h"
37 #include "ppc32_map_regs.h"
39 #define DEBUG_MODULE "firm.be.ppc.isa"
42 pset *symbol_pset = NULL;
44 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
45 static set *cur_reg_set = NULL;
47 /**************************************************
50 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
51 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
52 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
53 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
56 **************************************************/
58 static ir_node *my_skip_proj(const ir_node *n) {
65 * Return register requirements for a ppc node.
66 * If the node returns a tuple (mode_T) then the proj's
67 * will be asked for this information.
69 static const arch_register_req_t *ppc32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
70 const ppc32_register_req_t *irn_req;
71 long node_pos = pos == -1 ? 0 : pos;
72 ir_mode *mode = get_irn_mode(irn);
73 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
75 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
76 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
80 if (mode == mode_T && pos < 0) {
81 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
85 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
88 /* in case of a proj, we need to get the correct OUT slot */
89 /* of the node corresponding to the proj number */
91 node_pos = ppc32_translate_proj_pos(irn);
97 irn = my_skip_proj(irn);
99 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
102 /* get requirements for our own nodes */
103 if (is_ppc32_irn(irn)) {
105 irn_req = get_ppc32_in_req(irn, pos);
108 irn_req = get_ppc32_out_req(irn, node_pos);
111 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
113 memcpy(req, &(irn_req->req), sizeof(*req));
115 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
116 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
117 req->other_same = get_irn_n(irn, irn_req->same_pos);
120 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
121 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
122 req->other_different = get_irn_n(irn, irn_req->different_pos);
125 /* get requirements for FIRM nodes */
127 /* treat Phi like Const with default requirements */
129 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
131 if (mode_is_float(mode)) {
132 memcpy(req, &(ppc32_default_req_ppc32_fp.req), sizeof(*req));
134 else if (mode_is_int(mode) || mode_is_reference(mode)) {
135 memcpy(req, &(ppc32_default_req_ppc32_gp.req), sizeof(*req));
137 else if (mode == mode_T || mode == mode_M) {
138 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
142 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
154 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
159 if (get_irn_mode(irn) == mode_X) {
163 pos = ppc32_translate_proj_pos(irn);
164 irn = my_skip_proj(irn);
167 if (is_ppc32_irn(irn)) {
168 const arch_register_t **slots;
170 slots = get_ppc32_slots(irn);
174 /* here we set the registers for the Phi nodes */
175 ppc32_set_firm_reg(irn, reg, cur_reg_set);
179 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
181 const arch_register_t *reg = NULL;
185 if (get_irn_mode(irn) == mode_X) {
189 pos = ppc32_translate_proj_pos(irn);
190 irn = my_skip_proj(irn);
193 if (is_ppc32_irn(irn)) {
194 const arch_register_t **slots;
195 slots = get_ppc32_slots(irn);
199 reg = ppc32_get_firm_reg(irn, cur_reg_set);
205 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
206 irn = my_skip_proj(irn);
209 return arch_irn_class_branch;
211 else if (is_ppc32_irn(irn)) {
212 return arch_irn_class_normal;
218 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
219 irn = my_skip_proj(irn);
221 if (is_ppc32_irn(irn)) {
222 return get_ppc32_flags(irn);
224 else if (is_Unknown(irn)) {
225 return arch_irn_flags_ignore;
231 static entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
232 if(!is_ppc32_irn(irn)) return NULL;
233 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
234 return get_ppc32_frame_entity(irn);
237 static void ppc32_set_frame_entity(const void *self, const ir_node *irn, entity *ent) {
238 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
240 set_ppc32_frame_entity(irn, ent);
244 * This function is called by the generic backend to correct offsets for
245 * nodes accessing the stack.
247 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
248 set_ppc32_offset(irn, bias);
251 static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
257 const be_abi_call_t *call;
262 * Initialize the callback object.
263 * @param call The call object.
264 * @param aenv The architecture environment.
265 * @param irg The graph with the method.
266 * @return Some pointer. This pointer is passed to all other callback functions as self object.
268 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
270 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
277 * Destroy the callback object.
278 * @param self The callback object.
280 static void ppc32_abi_done(void *self)
286 * Get the between type for that call.
287 * @param self The callback object.
288 * @return The between type of for that call.
290 static ir_type *ppc32_abi_get_between_type(void *self)
292 static ir_type *between_type = NULL;
293 static entity *old_bp_ent = NULL;
296 entity *ret_addr_ent;
297 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
298 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
300 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
301 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
302 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
304 set_entity_offset_bytes(old_bp_ent, 0);
305 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
306 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
313 * Put all registers which are saved by the prologue/epilogue in a set.
314 * @param self The callback object.
317 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
322 * Generate the prologue.
323 * @param self The callback object.
324 * @param mem A pointer to the mem node. Update this if you define new memory.
325 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
326 * @return The register which shall be used as a stack frame base.
328 * All nodes which define registers in @p reg_map must keep @p reg_map current.
330 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
332 ppc32_abi_env *env = (ppc32_abi_env *) self;
333 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
334 isleaf = flags.bits.irg_is_leaf;
336 if(flags.bits.try_omit_fp)
337 return &ppc32_gp_regs[REG_R1];
339 return &ppc32_gp_regs[REG_R31];
343 * Generate the epilogue.
344 * @param self The callback object.
345 * @param mem Memory one can attach to.
346 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
348 * All nodes which define registers in @p reg_map must keep @p reg_map current.
349 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
351 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
355 static const be_abi_callbacks_t ppc32_abi_callbacks = {
358 ppc32_abi_get_between_type,
359 ppc32_abi_regs_saved_by_me,
364 /* fill register allocator interface */
366 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
367 ppc32_get_irn_reg_req,
372 ppc32_get_frame_entity,
373 ppc32_set_frame_entity,
374 ppc32_set_stack_bias,
376 NULL, /* get_inverse */
377 NULL, /* get_op_estimated_cost */
378 NULL, /* possible_memory_operand */
379 NULL, /* perform_memory_operand */
382 ppc32_irn_ops_t ppc32_irn_ops = {
389 /**************************************************
392 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
393 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
394 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
395 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
398 **************************************************/
400 static void ppc32_before_abi(void *self) {
401 ppc32_code_gen_t *cg = self;
402 ir_type *frame_type = get_irg_frame_type(cg->irg);
404 frame_alloc_area(frame_type, 24, 4, 1);
406 ppc32_init_conv_walk();
407 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
410 if(cg->area_size < 32) cg->area_size = 32;
411 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
415 static void ppc32_search_start_successor(ir_node *block, void *env) {
416 ppc32_code_gen_t *cg = env;
417 int n = get_Block_n_cfgpreds(block);
418 ir_node *startblock = get_irg_start_block(cg->irg);
419 if(block == startblock) return;
421 for (n--; n >= 0; n--) {
422 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
423 if(predblock == startblock)
425 cg->start_succ_block = block;
432 * Transforms the standard firm graph into
435 static void ppc32_prepare_graph(void *self) {
436 ppc32_code_gen_t *cg = self;
438 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
439 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
440 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
442 ppc32_register_transformers();
443 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
444 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
445 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
451 * Called immediatly before emit phase.
453 static void ppc32_finish_irg(void *self) {
454 /* TODO: - fix offsets for nodes accessing stack
461 * These are some hooks which must be filled but are probably not needed.
463 static void ppc32_before_sched(void *self) {
464 /* Some stuff you need to do after scheduling but before register allocation */
468 * Called before the register allocator.
469 * Calculate a block schedule here. We need it for the x87
470 * simulator and the emitter.
472 static void ppc32_before_ra(void *self) {
473 ppc32_code_gen_t *cg = self;
474 cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
477 static void ppc32_transform_spill(ir_node *node, void *env)
479 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
481 if(be_is_Spill(node))
483 ir_node *store, *proj;
484 dbg_info *dbg = get_irn_dbg_info(node);
485 ir_node *block = get_nodes_block(node);
487 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
489 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
491 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
492 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
494 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
496 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
497 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
499 else assert(0 && "Spill for register class not supported yet!");
501 set_ppc32_frame_entity(store, be_get_frame_entity(node));
503 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
505 if (sched_is_scheduled(node)) {
506 sched_add_after(sched_prev(node), store);
507 sched_add_after(store, proj);
512 exchange(node, proj);
515 if(be_is_Reload(node))
517 ir_node *load, *proj;
518 const arch_register_t *reg;
519 dbg_info *dbg = get_irn_dbg_info(node);
520 ir_node *block = get_nodes_block(node);
521 ir_mode *mode = get_irn_mode(node);
523 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
525 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
527 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
529 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
531 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
533 else assert(0 && "Reload for register class not supported yet!");
535 set_ppc32_frame_entity(load, be_get_frame_entity(node));
537 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
539 if (sched_is_scheduled(node)) {
540 sched_add_after(sched_prev(node), load);
541 sched_add_after(load, proj);
546 /* copy the register from the old node to the new Load */
547 reg = arch_get_irn_register(cgenv->arch_env, node);
548 arch_set_irn_register(cgenv->arch_env, load, reg);
550 exchange(node, proj);
555 * Some stuff to do immediately after register allocation
557 static void ppc32_after_ra(void *self) {
558 ppc32_code_gen_t *cg = self;
559 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
563 * Emits the code, closes the output file and frees
564 * the code generator interface.
566 static void ppc32_emit_and_done(void *self) {
567 ppc32_code_gen_t *cg = self;
568 ir_graph *irg = cg->irg;
569 FILE *out = cg->isa->out;
571 if (cg->emit_decls) {
572 ppc32_gen_decls(out);
576 dump_ir_block_graph_sched(irg, "-ppc-finished");
577 ppc32_gen_routine(out, irg, cg);
581 /* de-allocate code generator */
582 del_set(cg->reg_set);
587 del_pset(symbol_pset);
592 int is_direct_entity(entity *ent);
595 * Collects all SymConsts which need to be accessed "indirectly"
597 * @param node the firm node
598 * @param env the debug module
600 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
601 if(get_irn_op(node) == op_SymConst)
603 entity *ent = get_SymConst_entity(node);
604 if(!is_direct_entity(ent))
605 pset_insert_ptr(symbol_pset, ent);
609 static void *ppc32_cg_init(const be_irg_t *birg);
611 static const arch_code_generator_if_t ppc32_code_gen_if = {
615 ppc32_before_sched, /* before scheduling hook */
616 ppc32_before_ra, /* before register allocation hook */
623 * Initializes the code generator.
625 static void *ppc32_cg_init(const be_irg_t *birg) {
626 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
627 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
629 cg->impl = &ppc32_code_gen_if;
631 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
632 cg->arch_env = birg->main_env->arch_env;
637 cg->start_succ_block = NULL;
638 cg->blk_sched = NULL;
639 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
643 if (isa->num_codegens > 1)
649 symbol_pset = pset_new_ptr(8);
650 for(i=0; i<get_irp_n_irgs(); i++)
652 cg->irg = get_irp_irg(i);
653 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
658 cur_reg_set = cg->reg_set;
660 ppc32_irn_ops.cg = cg;
662 return (arch_code_generator_t *)cg;
667 /*****************************************************************
668 * ____ _ _ _____ _____
669 * | _ \ | | | | |_ _|/ ____| /\
670 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
671 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
672 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
673 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
675 *****************************************************************/
677 static ppc32_isa_t ppc32_isa_template = {
679 &ppc32_gp_regs[REG_R1], // stack pointer
680 &ppc32_gp_regs[REG_R31], // base pointer
681 -1, // stack is decreasing
682 0, // num codegens... ??
687 * Initializes the backend ISA and opens the output file.
689 static void *ppc32_init(FILE *file_handle) {
690 static int inited = 0;
696 isa = xmalloc(sizeof(*isa));
697 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
699 isa->out = file_handle;
701 ppc32_register_init(isa);
702 ppc32_create_opcodes();
712 * Closes the output file and frees the ISA structure.
714 static void ppc32_done(void *self) {
720 static int ppc32_get_n_reg_class(const void *self) {
724 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
725 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
726 return &ppc32_reg_classes[i];
732 * Get the register class which shall be used to store a value of a given mode.
733 * @param self The this pointer.
734 * @param mode The mode in question.
735 * @return A register class which can hold values of the given mode.
737 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
738 if (mode_is_float(mode))
739 return &ppc32_reg_classes[CLASS_ppc32_fp];
741 return &ppc32_reg_classes[CLASS_ppc32_gp];
746 * Get the ABI restrictions for procedure calls.
747 * @param self The this pointer.
748 * @param method_type The type of the method (procedure) in question.
749 * @param abi The abi object to be modified
751 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
754 int i, n = get_method_n_params(method_type);
755 int stackoffs = 0, lastoffs = 0, stackparamsize;
760 const arch_register_t *reg;
761 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
763 if(get_type_visibility(method_type)!=visibility_external_allocated)
764 call_flags.bits.call_has_imm = 1;
766 /* set stack parameter passing style */
767 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
769 for (i = 0; i < n; i++) {
770 tp = get_method_param_type(method_type, i);
771 if(is_atomic_type(tp))
773 mode = get_type_mode(tp);
775 if(mode_is_float(mode))
777 if(fpregi <= REG_F13)
779 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
780 else gpregi += 2, stackparamsize=8; // mode == irm_D
781 reg = &ppc32_fp_regs[fpregi++];
785 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
786 else stackparamsize=8; // mode == irm_D
792 if(gpregi <= REG_R10)
793 reg = &ppc32_gp_regs[gpregi++];
800 be_abi_call_param_reg(abi, i, reg);
803 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
804 lastoffs = stackoffs+stackparamsize;
806 stackoffs += stackparamsize;
810 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
811 stackoffs += (get_type_size_bytes(tp)+3) & -4;
812 lastoffs = stackoffs;
816 /* explain where result can be found if any */
817 if (get_method_n_ress(method_type) > 0) {
818 tp = get_method_res_type(method_type, 0);
819 mode = get_type_mode(tp);
821 be_abi_call_res_reg(abi, 0,
822 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
826 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
827 return &ppc32_irn_ops;
830 const arch_irn_handler_t ppc32_irn_handler = {
834 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
835 return &ppc32_irn_handler;
838 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
839 return is_ppc32_irn(irn);
843 * Initializes the code generator interface.
845 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
846 return &ppc32_code_gen_if;
849 list_sched_selector_t ppc32_sched_selector;
852 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
854 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
855 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
856 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
857 return &ppc32_sched_selector;
861 * Returns the necessary byte alignment for storing a register of given class.
863 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
864 ir_mode *mode = arch_register_class_mode(cls);
865 return get_mode_size_bytes(mode);
868 static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
874 static const be_machine_t *ppc32_get_machine(const void *self) {
881 * Returns the libFirm configuration parameter for this backend.
883 static const backend_params *ppc32_get_libfirm_params(void) {
884 static arch_dep_params_t ad = {
886 0, /* Muls are fast enough on ARM */
887 31, /* shift would be ok */
888 0, /* SMUL is needed, only in Arch M*/
889 0, /* UMUL is needed, only in Arch M */
890 32, /* SMUL & UMUL available for 32 bit */
892 static backend_params p = {
893 NULL, /* no additional opcodes */
894 NULL, /* will be set later */
895 1, /* need dword lowering */
896 NULL, /* but yet no creator function */
897 NULL, /* context for create_intrinsic_fkt */
905 static void ppc32_register_options(lc_opt_entry_t *ent)
908 #endif /* WITH_LIBCORE */
910 const arch_isa_if_t ppc32_isa_if = {
913 ppc32_get_n_reg_class,
915 ppc32_get_reg_class_for_mode,
917 ppc32_get_irn_handler,
918 ppc32_get_code_generator_if,
919 ppc32_get_list_sched_selector,
920 ppc32_get_reg_class_alignment,
921 ppc32_get_libfirm_params,
922 ppc32_get_allowed_execution_units,
925 ppc32_register_options