1 /* The main ppc backend driver file. */
7 #include "pseudo_irg.h"
18 #include "../bearch_t.h" /* the general register allocator interface */
19 #include "../benode_t.h"
20 #include "../belower.h"
21 #include "../besched_t.h"
24 #include "../bemachine.h"
25 #include "../bemodule.h"
26 #include "../beblocksched.h"
27 #include "../beirg_t.h"
31 #include "bearch_ppc32_t.h"
33 #include "ppc32_new_nodes.h" /* ppc nodes interface */
34 #include "gen_ppc32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
35 #include "ppc32_gen_decls.h" /* interface declaration emitter */
36 #include "ppc32_transform.h"
37 #include "ppc32_transform_conv.h"
38 #include "ppc32_emitter.h"
39 #include "ppc32_map_regs.h"
41 #define DEBUG_MODULE "firm.be.ppc.isa"
44 pset *symbol_pset = NULL;
46 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
47 static set *cur_reg_set = NULL;
49 /**************************************************
52 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
53 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
54 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
55 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
58 **************************************************/
61 * Return register requirements for a ppc node.
62 * If the node returns a tuple (mode_T) then the proj's
63 * will be asked for this information.
66 arch_register_req_t *ppc32_get_irn_reg_req(const void *self,
67 const ir_node *irn, int pos) {
68 long node_pos = pos == -1 ? 0 : pos;
69 ir_mode *mode = get_irn_mode(irn);
70 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
72 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
73 DBG((mod, LEVEL_1, "ignoring block, mode_X or mode_M node %+F\n", irn));
74 return arch_no_register_req;
77 if (mode == mode_T && pos < 0) {
78 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F", irn));
79 return arch_no_register_req;
82 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
85 /* in case of a proj, we need to get the correct OUT slot */
86 /* of the node corresponding to the proj number */
88 node_pos = ppc32_translate_proj_pos(irn);
93 irn = skip_Proj_const(irn);
95 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
98 /* get requirements for our own nodes */
99 if (is_ppc32_irn(irn)) {
100 const arch_register_req_t *req;
102 req = get_ppc32_in_req(irn, pos);
104 req = get_ppc32_out_req(irn, node_pos);
107 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
111 /* unknowns should be transformed by now */
112 assert(!is_Unknown(irn));
114 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
115 return arch_no_register_req;
118 static void ppc32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
123 if (get_irn_mode(irn) == mode_X) {
127 pos = ppc32_translate_proj_pos(irn);
128 irn = skip_Proj(irn);
131 if (is_ppc32_irn(irn)) {
132 const arch_register_t **slots;
134 slots = get_ppc32_slots(irn);
138 /* here we set the registers for the Phi nodes */
139 ppc32_set_firm_reg(irn, reg, cur_reg_set);
143 static const arch_register_t *ppc32_get_irn_reg(const void *self, const ir_node *irn) {
145 const arch_register_t *reg = NULL;
149 if (get_irn_mode(irn) == mode_X) {
153 pos = ppc32_translate_proj_pos(irn);
154 irn = skip_Proj_const(irn);
157 if (is_ppc32_irn(irn)) {
158 const arch_register_t **slots;
159 slots = get_ppc32_slots(irn);
163 reg = ppc32_get_firm_reg(irn, cur_reg_set);
169 static arch_irn_class_t ppc32_classify(const void *self, const ir_node *irn) {
170 irn = skip_Proj_const(irn);
173 return arch_irn_class_branch;
175 else if (is_ppc32_irn(irn)) {
176 return arch_irn_class_normal;
182 static arch_irn_flags_t ppc32_get_flags(const void *self, const ir_node *irn) {
183 irn = skip_Proj_const(irn);
185 if (is_ppc32_irn(irn)) {
186 return get_ppc32_flags(irn);
188 else if (is_Unknown(irn)) {
189 return arch_irn_flags_ignore;
195 static ir_entity *ppc32_get_frame_entity(const void *self, const ir_node *irn) {
196 if(!is_ppc32_irn(irn)) return NULL;
197 if(get_ppc32_type(irn)!=ppc32_ac_FrameEntity) return NULL;
198 return get_ppc32_frame_entity(irn);
201 static void ppc32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
202 if (! is_ppc32_irn(irn) || get_ppc32_type(irn) != ppc32_ac_FrameEntity)
204 set_ppc32_frame_entity(irn, ent);
208 * This function is called by the generic backend to correct offsets for
209 * nodes accessing the stack.
211 static void ppc32_set_stack_bias(const void *self, ir_node *irn, int bias) {
212 set_ppc32_offset(irn, bias);
215 static int ppc32_get_sp_bias(const void *self, const ir_node *irn) {
221 const be_abi_call_t *call;
226 * Initialize the callback object.
227 * @param call The call object.
228 * @param aenv The architecture environment.
229 * @param irg The graph with the method.
230 * @return Some pointer. This pointer is passed to all other callback functions as self object.
232 static void *ppc32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
234 ppc32_abi_env *env = xmalloc(sizeof(ppc32_abi_env));
241 * Destroy the callback object.
242 * @param self The callback object.
244 static void ppc32_abi_done(void *self)
250 * Get the between type for that call.
251 * @param self The callback object.
252 * @return The between type of for that call.
254 static ir_type *ppc32_abi_get_between_type(void *self)
256 static ir_type *between_type = NULL;
257 static ir_entity *old_bp_ent = NULL;
260 ir_entity *ret_addr_ent;
261 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
262 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
264 between_type = new_type_class(new_id_from_str("ppc32_between_type"));
265 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
266 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
268 set_entity_offset(old_bp_ent, 0);
269 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
270 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
277 * Put all registers which are saved by the prologue/epilogue in a set.
278 * @param self The callback object.
281 static void ppc32_abi_regs_saved_by_me(void *self, pset *regs)
286 * Generate the prologue.
287 * @param self The callback object.
288 * @param mem A pointer to the mem node. Update this if you define new memory.
289 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
290 * @return The register which shall be used as a stack frame base.
292 * All nodes which define registers in @p reg_map must keep @p reg_map current.
294 static const arch_register_t *ppc32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
296 ppc32_abi_env *env = (ppc32_abi_env *) self;
297 be_abi_call_flags_t flags = be_abi_call_get_flags(env->call);
298 isleaf = flags.bits.irg_is_leaf;
300 if(flags.bits.try_omit_fp)
301 return &ppc32_gp_regs[REG_R1];
303 return &ppc32_gp_regs[REG_R31];
307 * Generate the epilogue.
308 * @param self The callback object.
309 * @param mem Memory one can attach to.
310 * @param reg_map A mapping mapping all callee_save/ignore/return registers to their defining nodes.
312 * All nodes which define registers in @p reg_map must keep @p reg_map current.
313 * Also, the @p mem variable must be updated, if memory producing nodes are inserted.
315 static void ppc32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
319 static const be_abi_callbacks_t ppc32_abi_callbacks = {
322 ppc32_abi_get_between_type,
323 ppc32_abi_regs_saved_by_me,
328 /* fill register allocator interface */
330 static const arch_irn_ops_if_t ppc32_irn_ops_if = {
331 ppc32_get_irn_reg_req,
336 ppc32_get_frame_entity,
337 ppc32_set_frame_entity,
338 ppc32_set_stack_bias,
340 NULL, /* get_inverse */
341 NULL, /* get_op_estimated_cost */
342 NULL, /* possible_memory_operand */
343 NULL, /* perform_memory_operand */
346 ppc32_irn_ops_t ppc32_irn_ops = {
353 /**************************************************
356 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
357 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
358 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
359 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
362 **************************************************/
364 static void ppc32_before_abi(void *self) {
365 ppc32_code_gen_t *cg = self;
366 ir_type *frame_type = get_irg_frame_type(cg->irg);
368 frame_alloc_area(frame_type, 24, 4, 1);
370 ppc32_init_conv_walk();
371 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_conv_walk, cg);
374 if(cg->area_size < 32) cg->area_size = 32;
375 cg->area = frame_alloc_area(get_irg_frame_type(cg->irg), cg->area_size+24, 16, 1);
379 static void ppc32_search_start_successor(ir_node *block, void *env) {
380 ppc32_code_gen_t *cg = env;
381 int n = get_Block_n_cfgpreds(block);
382 ir_node *startblock = get_irg_start_block(cg->irg);
383 if(block == startblock) return;
385 for (n--; n >= 0; n--) {
386 ir_node *predblock = get_irn_n(get_Block_cfgpred(block, n), -1);
387 if(predblock == startblock)
389 cg->start_succ_block = block;
396 * Transforms the standard firm graph into
399 static void ppc32_prepare_graph(void *self) {
400 ppc32_code_gen_t *cg = self;
402 irg_block_walk_graph(cg->irg, NULL, ppc32_search_start_successor, cg);
403 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_pretransform_walk, cg);
404 be_dump(cg->irg, "-pretransformed", dump_ir_block_graph);
406 ppc32_register_transformers();
407 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_node, cg);
408 be_dump(cg->irg, "-transformed", dump_ir_block_graph);
409 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_const, cg);
415 * Called immediatly before emit phase.
417 static void ppc32_finish_irg(void *self) {
418 /* TODO: - fix offsets for nodes accessing stack
425 * These are some hooks which must be filled but are probably not needed.
427 static void ppc32_before_sched(void *self) {
428 /* Some stuff you need to do after scheduling but before register allocation */
432 * Called before the register allocator.
433 * Calculate a block schedule here. We need it for the x87
434 * simulator and the emitter.
436 static void ppc32_before_ra(void *self) {
437 ppc32_code_gen_t *cg = self;
438 cg->blk_sched = be_create_block_schedule(cg->irg, cg->birg->exec_freq);
441 static void ppc32_transform_spill(ir_node *node, void *env)
443 ppc32_code_gen_t *cgenv = (ppc32_code_gen_t *)env;
445 if(be_is_Spill(node))
447 ir_node *store, *proj;
448 dbg_info *dbg = get_irn_dbg_info(node);
449 ir_node *block = get_nodes_block(node);
451 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, 1);
453 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
455 store = new_rd_ppc32_Stw(dbg, current_ir_graph, block,
456 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
458 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
460 store = new_rd_ppc32_Stfd(dbg, current_ir_graph, block,
461 get_irn_n(node, 0), get_irn_n(node, 1), new_rd_NoMem(current_ir_graph));
463 else assert(0 && "Spill for register class not supported yet!");
465 set_ppc32_frame_entity(store, be_get_frame_entity(node));
467 proj = new_rd_Proj(dbg, current_ir_graph, block, store, mode_M, pn_Store_M);
469 if (sched_is_scheduled(node)) {
470 sched_add_after(sched_prev(node), store);
471 sched_add_after(store, proj);
476 exchange(node, proj);
479 if(be_is_Reload(node))
481 ir_node *load, *proj;
482 const arch_register_t *reg;
483 dbg_info *dbg = get_irn_dbg_info(node);
484 ir_node *block = get_nodes_block(node);
485 ir_mode *mode = get_irn_mode(node);
487 const arch_register_class_t *regclass = arch_get_irn_reg_class(cgenv->arch_env, node, -1);
489 if (regclass == &ppc32_reg_classes[CLASS_ppc32_gp])
491 load = new_rd_ppc32_Lwz(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
493 else if (regclass == &ppc32_reg_classes[CLASS_ppc32_fp])
495 load = new_rd_ppc32_Lfd(dbg, current_ir_graph, block, get_irn_n(node, 0), get_irn_n(node, 1));
497 else assert(0 && "Reload for register class not supported yet!");
499 set_ppc32_frame_entity(load, be_get_frame_entity(node));
501 proj = new_rd_Proj(dbg, current_ir_graph, block, load, mode, pn_Load_res);
503 if (sched_is_scheduled(node)) {
504 sched_add_after(sched_prev(node), load);
505 sched_add_after(load, proj);
510 /* copy the register from the old node to the new Load */
511 reg = arch_get_irn_register(cgenv->arch_env, node);
512 arch_set_irn_register(cgenv->arch_env, load, reg);
514 exchange(node, proj);
519 * Some stuff to do immediately after register allocation
521 static void ppc32_after_ra(void *self) {
522 ppc32_code_gen_t *cg = self;
523 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_transform_spill, cg);
527 * Emits the code, closes the output file and frees
528 * the code generator interface.
530 static void ppc32_emit_and_done(void *self) {
531 ppc32_code_gen_t *cg = self;
532 ir_graph *irg = cg->irg;
533 FILE *out = cg->isa->out;
535 if (cg->emit_decls) {
536 ppc32_gen_decls(out);
540 dump_ir_block_graph_sched(irg, "-ppc-finished");
541 ppc32_gen_routine(out, irg, cg);
545 /* de-allocate code generator */
546 del_set(cg->reg_set);
551 del_pset(symbol_pset);
556 int is_direct_entity(ir_entity *ent);
559 * Collects all SymConsts which need to be accessed "indirectly"
561 * @param node the firm node
562 * @param env the debug module
564 void ppc32_collect_symconsts_walk(ir_node *node, void *env) {
565 if(get_irn_op(node) == op_SymConst)
567 ir_entity *ent = get_SymConst_entity(node);
568 if(!is_direct_entity(ent))
569 pset_insert_ptr(symbol_pset, ent);
573 static void *ppc32_cg_init(be_irg_t *birg);
575 static const arch_code_generator_if_t ppc32_code_gen_if = {
580 ppc32_before_sched, /* before scheduling hook */
581 ppc32_before_ra, /* before register allocation hook */
588 * Initializes the code generator.
590 static void *ppc32_cg_init(be_irg_t *birg) {
591 ppc32_isa_t *isa = (ppc32_isa_t *)birg->main_env->arch_env->isa;
592 ppc32_code_gen_t *cg = xmalloc(sizeof(*cg));
594 cg->impl = &ppc32_code_gen_if;
596 cg->reg_set = new_set(ppc32_cmp_irn_reg_assoc, 1024);
597 cg->arch_env = birg->main_env->arch_env;
602 cg->start_succ_block = NULL;
603 cg->blk_sched = NULL;
604 FIRM_DBG_REGISTER(cg->mod, "firm.be.ppc.cg");
608 if (isa->num_codegens > 1)
614 symbol_pset = pset_new_ptr(8);
615 for(i=0; i<get_irp_n_irgs(); i++)
617 cg->irg = get_irp_irg(i);
618 irg_walk_blkwise_graph(cg->irg, NULL, ppc32_collect_symconsts_walk, cg);
623 cur_reg_set = cg->reg_set;
625 ppc32_irn_ops.cg = cg;
627 return (arch_code_generator_t *)cg;
632 /*****************************************************************
633 * ____ _ _ _____ _____
634 * | _ \ | | | | |_ _|/ ____| /\
635 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
636 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
637 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
638 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
640 *****************************************************************/
642 static ppc32_isa_t ppc32_isa_template = {
644 &ppc32_gp_regs[REG_R1], // stack pointer
645 &ppc32_gp_regs[REG_R31], // base pointer
646 -1, // stack is decreasing
647 0, // num codegens... ??
652 * Initializes the backend ISA and opens the output file.
654 static void *ppc32_init(FILE *file_handle) {
655 static int inited = 0;
661 isa = xmalloc(sizeof(*isa));
662 memcpy(isa, &ppc32_isa_template, sizeof(*isa));
664 isa->out = file_handle;
666 ppc32_register_init(isa);
667 ppc32_create_opcodes();
677 * Closes the output file and frees the ISA structure.
679 static void ppc32_done(void *self) {
685 static int ppc32_get_n_reg_class(const void *self) {
689 static const arch_register_class_t *ppc32_get_reg_class(const void *self, int i) {
690 assert(i >= 0 && i < N_CLASSES && "Invalid ppc register class requested.");
691 return &ppc32_reg_classes[i];
697 * Get the register class which shall be used to store a value of a given mode.
698 * @param self The this pointer.
699 * @param mode The mode in question.
700 * @return A register class which can hold values of the given mode.
702 const arch_register_class_t *ppc32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
703 if (mode_is_float(mode))
704 return &ppc32_reg_classes[CLASS_ppc32_fp];
706 return &ppc32_reg_classes[CLASS_ppc32_gp];
711 * Get the ABI restrictions for procedure calls.
712 * @param self The this pointer.
713 * @param method_type The type of the method (procedure) in question.
714 * @param abi The abi object to be modified
716 static void ppc32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
719 int i, n = get_method_n_params(method_type);
720 int stackoffs = 0, lastoffs = 0, stackparamsize;
725 const arch_register_t *reg;
726 be_abi_call_flags_t call_flags = { { 0, 0, 1, 0, 0, 0, 1 } };
728 if(get_type_visibility(method_type)!=visibility_external_allocated)
729 call_flags.bits.call_has_imm = 1;
731 /* set stack parameter passing style */
732 be_abi_call_set_flags(abi, call_flags, &ppc32_abi_callbacks);
734 for (i = 0; i < n; i++) {
735 tp = get_method_param_type(method_type, i);
736 if(is_atomic_type(tp))
738 mode = get_type_mode(tp);
740 if(mode_is_float(mode))
742 if(fpregi <= REG_F13)
744 if(get_mode_size_bits(mode) == 32) gpregi++, stackparamsize=4;
745 else gpregi += 2, stackparamsize=8; // mode == irm_D
746 reg = &ppc32_fp_regs[fpregi++];
750 if(get_mode_size_bits(mode) == 32) stackparamsize=4;
751 else stackparamsize=8; // mode == irm_D
757 if(gpregi <= REG_R10)
758 reg = &ppc32_gp_regs[gpregi++];
765 be_abi_call_param_reg(abi, i, reg);
768 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
769 lastoffs = stackoffs+stackparamsize;
771 stackoffs += stackparamsize;
775 be_abi_call_param_stack(abi, i, 4, stackoffs-lastoffs, 0);
776 stackoffs += (get_type_size_bytes(tp)+3) & -4;
777 lastoffs = stackoffs;
781 /* explain where result can be found if any */
782 if (get_method_n_ress(method_type) > 0) {
783 tp = get_method_res_type(method_type, 0);
784 mode = get_type_mode(tp);
786 be_abi_call_res_reg(abi, 0,
787 mode_is_float(mode) ? &ppc32_fp_regs[REG_F1] : &ppc32_gp_regs[REG_R3]);
791 static const void *ppc32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
792 return &ppc32_irn_ops;
795 const arch_irn_handler_t ppc32_irn_handler = {
799 const arch_irn_handler_t *ppc32_get_irn_handler(const void *self) {
800 return &ppc32_irn_handler;
803 int ppc32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
804 return is_ppc32_irn(irn);
808 * Initializes the code generator interface.
810 static const arch_code_generator_if_t *ppc32_get_code_generator_if(void *self) {
811 return &ppc32_code_gen_if;
814 list_sched_selector_t ppc32_sched_selector;
817 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
819 static const list_sched_selector_t *ppc32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
820 memcpy(&ppc32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
821 ppc32_sched_selector.to_appear_in_schedule = ppc32_to_appear_in_schedule;
822 return &ppc32_sched_selector;
825 static const ilp_sched_selector_t *ppc32_get_ilp_sched_selector(const void *self) {
830 * Returns the necessary byte alignment for storing a register of given class.
832 static int ppc32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
833 ir_mode *mode = arch_register_class_mode(cls);
834 return get_mode_size_bytes(mode);
837 static const be_execution_unit_t ***ppc32_get_allowed_execution_units(const void *self, const ir_node *irn) {
843 static const be_machine_t *ppc32_get_machine(const void *self) {
850 * Return irp irgs in the desired order.
852 static ir_graph **ppc32_get_irg_list(const void *self, ir_graph ***irg_list) {
857 * Returns the libFirm configuration parameter for this backend.
859 static const backend_params *ppc32_get_libfirm_params(void) {
860 static arch_dep_params_t ad = {
862 0, /* Muls are fast enough on ARM */
863 31, /* shift would be ok */
864 0, /* SMUL is needed, only in Arch M*/
865 0, /* UMUL is needed, only in Arch M */
866 32, /* SMUL & UMUL available for 32 bit */
868 static backend_params p = {
869 NULL, /* no additional opcodes */
870 NULL, /* will be set later */
871 1, /* need dword lowering */
872 NULL, /* but yet no creator function */
873 NULL, /* context for create_intrinsic_fkt */
880 const arch_isa_if_t ppc32_isa_if = {
883 ppc32_get_n_reg_class,
885 ppc32_get_reg_class_for_mode,
887 ppc32_get_irn_handler,
888 ppc32_get_code_generator_if,
889 ppc32_get_list_sched_selector,
890 ppc32_get_ilp_sched_selector,
891 ppc32_get_reg_class_alignment,
892 ppc32_get_libfirm_params,
893 ppc32_get_allowed_execution_units,
898 void be_init_arch_ppc32(void)
900 be_register_isa_if("ppc32", &ppc32_isa_if);
903 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ppc32);