2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The codegenrator (transform FIRM into mips FIRM
23 * @author Matthias Braun, Mehdi
33 #include "irgraph_t.h"
44 #include "../benode_t.h"
46 #include "../besched.h"
47 #include "../besched_t.h"
48 #include "../beirg_t.h"
49 #include "bearch_mips_t.h"
51 #include "mips_nodes_attr.h"
53 #include "mips_transform.h"
54 #include "mips_new_nodes.h"
55 #include "mips_map_regs.h"
56 #include "mips_util.h"
57 #include "mips_emitter.h"
59 #include "gen_mips_regalloc_if.h"
61 /****************************************************************************************************
63 * | | | | / _| | | (_)
64 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
65 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
66 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
67 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
69 ****************************************************************************************************/
71 #define MIPS_GENBINFUNC(mips_nodetype) \
72 static ir_node* mips_gen_##mips_nodetype(mips_transform_env_t *env, ir_node *op1, ir_node *op2) {\
73 ASSERT_NO_FLOAT(env->mode); \
74 /*assert(get_irn_mode(op1) == get_irn_mode(op2));*/ \
75 /*assert(get_irn_mode(op1) == env->mode);*/ \
76 assert(get_mode_size_bits(env->mode) == 32); \
77 return new_rd_mips_##mips_nodetype(env->dbg, env->irg, env->block, op1, op2); \
89 #define MIPS_GENUNFUNC(mips_nodetype) \
90 static ir_node *mips_gen_##mips_nodetype(mips_transform_env_t *env, ir_node *op) { \
91 ASSERT_NO_FLOAT(env->mode); \
92 assert(get_irn_mode(op) == env->mode); \
93 assert(get_mode_size_bits(env->mode) == 32); \
94 return new_rd_mips_##mips_nodetype(env->dbg, env->irg, env->block, op); \
100 ir_node* gen_zero(mips_transform_env_t *env)
102 ir_graph *irg = env->irg;
103 ir_node *block = get_irg_start_block(irg);
104 ir_node *zero = new_rd_mips_zero(NULL, irg, block);
106 arch_set_irn_register(env->cg->arch_env, zero, &mips_gp_regs[REG_ZERO]);
112 ir_node* gen_node_for_Const(mips_transform_env_t *env, dbg_info *dbg, ir_graph *irg, ir_node *block, ir_node *constant)
114 tarval* tv = get_Const_tarval(constant);
118 ir_mode* mode = get_irn_mode(constant);
119 unsigned long val, lower, upper;
121 val = get_tarval_long(tv);
123 lower = val & 0xffff;
124 upper = (val >> 16) & 0xffff;
126 upper_node = gen_zero(env);
128 upper_node = new_rd_mips_lui(dbg, irg, block);
129 attr = get_mips_attr(upper_node);
130 attr->tv = new_tarval_from_long(val, mode);
136 lower_node = new_rd_mips_ori(dbg, irg, block, upper_node);
137 attr = get_mips_attr(lower_node);
138 attr->tv = new_tarval_from_long(lower, mode);
143 static ir_node* exchange_node_for_Const(mips_transform_env_t *env, ir_node* pred, int n) {
144 ir_node *node = env->irn;
145 dbg_info *dbg = get_irn_dbg_info(pred);
146 ir_graph *irg = get_irn_irg(node);
149 if(get_irn_opcode(node) == iro_Phi) {
150 ir_node *phipred = get_nodes_block(node);
151 block = get_Block_cfgpred_block(phipred, n);
153 block = get_nodes_block(node);
156 return gen_node_for_Const(env, dbg, irg, block, pred);
159 static ir_node* gen_node_for_SymConst(mips_transform_env_t *env, ir_node* pred)
162 ir_node *node = env->irn;
163 dbg_info *dbg = get_irn_dbg_info(pred);
164 ir_graph *irg = get_irn_irg(node);
169 block = get_nodes_block(pred);
171 if(get_SymConst_kind(pred) != symconst_addr_ent) {
172 panic("Only address entity symconsts supported in mips backend");
175 entity = get_SymConst_entity(pred);
177 lui = new_rd_mips_lui(dbg, irg, block);
178 attr = get_mips_attr(lui);
179 attr->symconst = entity;
181 ori = new_rd_mips_ori(dbg, irg, block, lui);
182 attr = get_mips_attr(ori);
183 attr->symconst = entity;
188 typedef ir_node* (*gen_load_func) (dbg_info *dbg, ir_graph *irg,
189 ir_node *block, ir_node *mem, ir_node *ptr);
192 * Generates a mips node for a firm Load node
194 static ir_node *gen_node_for_Load(mips_transform_env_t *env) {
195 ir_graph *irg = env->irg;
196 ir_node *node = env->irn;
197 dbg_info *dbg = get_irn_dbg_info(node);
198 ir_node *block = get_nodes_block(node);
199 ir_node *mem = get_Load_mem(node);
200 ir_node *ptr = get_Load_ptr(node);
201 ir_mode *mode = get_Load_mode(node);
202 int sign = get_mode_sign(mode);
206 ASSERT_NO_FLOAT(get_irn_mode(node));
208 assert(mode->vector_elem == 1);
209 assert(mode->sort == irms_int_number || mode->sort == irms_reference);
211 switch(get_mode_size_bits(mode)) {
213 func = new_rd_mips_lw;
216 func = sign ? new_rd_mips_lh : new_rd_mips_lhu;
219 func = sign ? new_rd_mips_lb : new_rd_mips_lbu;
222 panic("mips backend only support 32, 16, 8 bit loads");
225 result = func(dbg, irg, block, mem, ptr);
229 typedef ir_node* (*gen_store_func) (dbg_info *dbg, ir_graph *irg,
230 ir_node *block, ir_node *mem, ir_node *ptr,
234 * Generates a mips node for a firm Store node
236 static ir_node *gen_node_for_Store(mips_transform_env_t *env) {
237 ir_graph *irg = env->irg;
238 ir_node *node = env->irn;
239 dbg_info *dbg = get_irn_dbg_info(node);
240 ir_node *block = get_nodes_block(node);
241 ir_node *mem = get_Store_mem(node);
242 ir_node *ptr = get_Store_ptr(node);
243 ir_node *val = get_Store_value(node);
244 ir_mode *mode = get_irn_mode(val);
248 ASSERT_NO_FLOAT(mode);
250 assert(mode->vector_elem == 1);
251 assert(mode->sort == irms_int_number || mode->sort == irms_reference);
253 switch(get_mode_size_bits(mode)) {
255 func = new_rd_mips_sw;
258 func = new_rd_mips_sh;
261 func = new_rd_mips_sb;
264 panic("store only supported for 32, 16, 8 bit values in mips backend");
267 result = func(dbg, irg, block, mem, ptr, val);
271 static ir_node *gen_node_for_div_Proj(mips_transform_env_t *env) {
272 ir_node *proj = env->irn;
274 ir_node *pred = get_irn_n(proj, 0);
278 n = get_Proj_proj(proj);
280 // set the div mode to the DivMod node
281 attr = get_mips_attr(pred);
282 assert(attr->original_mode == NULL || attr->original_mode == env->mode);
283 attr->original_mode = env->mode;
285 // we have to construct a new proj here, to avoid circular refs that
286 // happen when we reuse the old one
287 new_proj = new_ir_node(env->dbg, env->irg, env->block, op_Proj, mode_ANY, 1, &pred);
288 set_Proj_proj(new_proj, n);
290 if(n == pn_DivMod_res_div) {
291 return new_rd_mips_mflo(env->dbg, env->irg, env->block, new_proj);
292 } else if(n == pn_DivMod_res_mod) {
293 return new_rd_mips_mfhi(env->dbg, env->irg, env->block, new_proj);
300 ir_node *gen_node_for_Proj(mips_transform_env_t *env)
302 ir_node *proj = env->irn;
303 ir_mode *mode = get_irn_mode(proj);
304 ir_node *predecessor = get_Proj_pred(proj);
306 // all DivMods, Div, Mod should be replaced by now
307 assert(get_irn_opcode(predecessor) != iro_DivMod);
308 assert(get_irn_opcode(predecessor) != iro_Div);
309 assert(get_irn_opcode(predecessor) != iro_Mod);
311 if(is_mips_div(predecessor))
312 return gen_node_for_div_Proj(env);
314 if(is_mips_lw(predecessor) || is_mips_lh(predecessor)
315 || is_mips_lhu(predecessor) || is_mips_lb(predecessor)
316 || is_mips_lbu(predecessor)) {
318 long pn = get_Proj_proj(proj);
319 if(pn == pn_Load_M) {
320 set_Proj_proj(proj, pn_mips_lw_M);
321 } else if(pn == pn_Load_res) {
322 set_Proj_proj(proj, pn_mips_lw_res);
327 if(get_irn_opcode(predecessor) == iro_Cond) {
328 ir_node *selector = get_Cond_selector(predecessor);
329 ir_mode *mode = get_irn_mode(selector);
330 n = get_Proj_proj(proj);
332 if(get_mode_sort(mode) == irms_internal_boolean) {
333 assert(n == pn_Cond_true || n == pn_Cond_false);
334 return gen_node_for_Cond_Proj(env, predecessor, n == pn_Cond_true);
339 if(get_mode_sort(mode) == irms_int_number) {
340 set_irn_mode(proj, mode_Iu);
347 ir_node *gen_node_for_Phi(mips_transform_env_t *env)
349 ir_node *node = env->irn;
350 ir_mode *mode = get_irn_mode(node);
352 if(get_mode_sort(mode) == irms_int_number) {
353 set_irn_mode(node, mode_Iu);
361 ir_node *gen_node_for_SwitchCond(mips_transform_env_t *env)
363 ir_node *selector = get_Cond_selector(env->irn);
364 ir_mode *selector_mode = get_irn_mode(selector);
365 ir_node *node = env->irn;
366 dbg_info *dbg = env->dbg;
367 ir_graph *irg = env->irg;
368 ir_node *block = env->block;
369 ir_node *sub, *sltu, *minval_const, *max_const, *switchjmp;
370 ir_node *defaultproj, *defaultproj_succ;
372 long pn, minval, maxval, defaultprojn;
373 const ir_edge_t *edge;
374 ir_node *zero, *two_const, *add, *la, *load, *proj;
375 ir_mode *unsigned_mode;
378 // mode_b conds are handled by gen_node_for_Proj
379 if(get_mode_sort(selector_mode) != irms_int_number)
382 assert(get_mode_size_bits(selector_mode) == 32);
385 defaultprojn = get_Cond_defaultProj(node);
387 // go over all projs to find min-&maxval of the switch
390 foreach_out_edge(node, edge) {
391 ir_node* proj = get_edge_src_irn(edge);
392 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
394 pn = get_Proj_proj(proj);
395 if(pn == defaultprojn) {
405 assert(defaultproj != NULL);
407 // subtract minval from the switch value
410 minval_const = new_rd_Const(dbg, irg, block, selector_mode, new_tarval_from_long(minval, selector_mode));
411 minval_const = gen_node_for_Const(env, dbg, irg, block, minval_const);
412 sub = new_rd_mips_sub(dbg, irg, block, selector, minval_const);
417 // compare if we're above maxval-minval or below zero.
418 // we can do this with 1 compare because we use unsigned mode
419 unsigned_mode = new_ir_mode(get_mode_name(selector_mode),
420 get_mode_sort(selector_mode), get_mode_size_bits(selector_mode),
421 0, get_mode_arithmetic(selector_mode), get_mode_modulo_shift(selector_mode));
423 max_const = new_rd_Const(dbg, irg, block, unsigned_mode, new_tarval_from_long(maxval - minval + 1, unsigned_mode));
424 max_const = gen_node_for_Const(env, dbg, irg, block, max_const);
425 sltu = new_rd_mips_slt(dbg, irg, block, sub, max_const);
427 zero = gen_zero_node(env, dbg, irg, block);
428 beq = new_rd_mips_beq(dbg, irg, block, sltu, zero, mode_T);
430 // attach defaultproj to beq now
431 set_irn_n(defaultproj, 0, beq);
432 set_Proj_proj(defaultproj, 1);
434 two_const = new_rd_Const(dbg, irg, block, unsigned_mode, new_tarval_from_long(2, unsigned_mode));
435 two_const = gen_node_for_Const(env, dbg, irg, block, two_const);
436 sl = new_rd_mips_sl(dbg, irg, block, sub, two_const);
438 la = new_rd_mips_la(dbg, irg, block);
439 add = new_rd_mips_addu(dbg, irg, block, sl, la);
440 load = new_rd_mips_load_r(dbg, irg, block, new_rd_NoMem(irg), add, mode_T);
441 attr = get_mips_attr(load);
442 attr->modes.load_store_mode = mode_Iu;
443 attr->tv = new_tarval_from_long(0, mode_Iu);
445 proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_Load_res);
447 switchjmp = new_rd_mips_SwitchJump(dbg, irg, block, proj, mode_T);
448 attr = get_mips_attr(switchjmp);
449 attr->switch_default_pn = defaultprojn;
451 edge = get_irn_out_edge_first(defaultproj);
452 defaultproj_succ = get_edge_src_irn(edge);
453 attr->symconst_id = new_id_from_str(mips_get_block_label(defaultproj_succ));
455 attr = get_mips_attr(la);
456 attr->symconst_id = new_id_from_str(mips_get_jumptbl_label(switchjmp));
463 ir_node *gen_node_for_Cond(mips_transform_env_t *env)
465 ir_graph *irg = env->irg;
466 ir_node *node = env->irn;
467 dbg_info *dbg = get_irn_dbg_info(node);
468 ir_node *block = get_nodes_block(node);
469 ir_node *sel_proj = get_Cond_selector(node);
470 ir_node *cmp = get_Proj_pred(sel_proj);
475 long pn = get_Proj_proj(sel_proj);
477 op1 = get_Cmp_left(cmp);
478 op2 = get_Cmp_right(cmp);
483 panic("mips backend can't handle unoptimized constant Cond");
486 res = new_rd_mips_beq(dbg, irg, block, op1, op2);
490 zero = gen_zero(env);
491 slt = new_rd_mips_slt(dbg, irg, block, op1, op2);
492 res = new_rd_mips_bne(dbg, irg, block, slt, zero);
496 zero = gen_zero(env);
497 slt = new_rd_mips_slt(dbg, irg, block, op2, op1);
498 res = new_rd_mips_beq(dbg, irg, block, slt, zero);
502 zero = gen_zero(env);
503 slt = new_rd_mips_slt(dbg, irg, block, op2, op1);
504 res = new_rd_mips_bne(dbg, irg, block, slt, zero);
508 zero = gen_zero(env);
509 slt = new_rd_mips_slt(dbg, irg, block, op2, op1);
510 res = new_rd_mips_bne(dbg, irg, block, slt, zero);
514 res = new_rd_mips_bne(dbg, irg, block, op1, op2);
518 panic("mips backend doesn't handle unordered compares yet");
524 static ir_node *create_conv_and(mips_transform_env_t *env, long immediate) {
525 ir_node *node = env->irn;
530 pred = get_Conv_op(node);
531 result = new_rd_mips_andi(env->dbg, env->irg, env->block, pred);
532 attr = get_mips_attr(result);
533 attr->tv = new_tarval_from_long(immediate, mode_Iu);
538 static ir_node *gen_node_for_Conv(mips_transform_env_t *env) {
539 ir_node *node = env->irn;
543 int dst_size, src_size;
545 pred = get_Conv_op(node);
546 srcmode = get_irn_mode(pred);
547 destmode = get_irn_mode(node);
549 dst_size = get_mode_size_bits(destmode);
550 src_size = get_mode_size_bits(srcmode);
552 if(src_size == dst_size) {
553 /* unnecessary conv */
558 if(srcmode->size >= destmode->size) {
559 assert(srcmode->size > destmode->size || srcmode->sign != destmode->sign);
560 return new_rd_mips_reinterpret_conv(env->dbg, env->irg, env->block, pred);
567 return create_conv_and(env, 0xff);
568 } else if(src_size == 16) {
569 return create_conv_and(env, 0xffff);
577 static ir_node *gen_node_mips_div(mips_transform_env_t *env, ir_node* op1, ir_node* op2, long p_div, long p_mod,
580 ir_node *node = env->irn;
582 const ir_edge_t *edge;
583 ir_mode *mode = get_irn_mode(node);
585 if(mode_is_signed(mode)) {
586 div = new_rd_mips_div(env->dbg, env->irg, env->block, op1, op2);
588 div = new_rd_mips_divu(env->dbg, env->irg, env->block, op1, op2);
592 foreach_out_edge(node, edge) {
593 ir_node *proj = get_edge_src_irn(edge);
594 long n = get_Proj_proj(proj);
595 assert(is_Proj(proj) && "non-Proj from Mod node");
597 set_Proj_proj(proj, pn_DivMod_res_div);
598 } else if (n == p_mod) {
599 set_Proj_proj(proj, pn_DivMod_res_mod);
600 } else if(n == p_m) {
601 set_Proj_proj(proj, pn_DivMod_M);
602 } else if(n == p_x) {
603 set_Proj_proj(proj, pn_DivMod_X_except);
605 assert(!"invalid proj");
612 static ir_node *gen_node_for_DivMod(mips_transform_env_t *env) {
613 ir_node *node = env->irn;
615 return gen_node_mips_div(env, get_DivMod_left(node), get_DivMod_right(node), pn_DivMod_res_div,
616 pn_DivMod_res_mod, pn_DivMod_M, pn_DivMod_X_except);
619 static ir_node *gen_node_for_Div(mips_transform_env_t *env) {
620 ir_node *node = env->irn;
622 return gen_node_mips_div(env, get_Div_left(node), get_Div_right(node), pn_Div_res, -1,
623 pn_Div_M, pn_Div_X_except);
626 static ir_node *gen_node_for_Mod(mips_transform_env_t *env) {
627 ir_node *node = env->irn;
629 return gen_node_mips_div(env, get_Mod_left(node), get_Mod_right(node), -1, pn_Mod_res,
630 pn_Mod_M, pn_Mod_X_except);
633 static ir_node *gen_node_for_Mul(mips_transform_env_t *env) {
634 ir_node *node = env->irn;
638 ir_mode *mode = get_irn_mode(node);
640 op1 = get_Mul_left(node);
641 op2 = get_Mul_right(node);
643 assert(get_mode_size_bits(env->mode) == 32);
644 assert(get_mode_size_bits(get_irn_mode(op1)) == get_mode_size_bits(env->mode));
645 assert(get_mode_size_bits(get_irn_mode(op2)) == get_mode_size_bits(env->mode));
647 if(mode_is_signed(mode)) {
648 mul = new_rd_mips_mult(env->dbg, env->irg, env->block, get_Mul_left(node), get_Mul_right(node));
650 mul = new_rd_mips_multu(env->dbg, env->irg, env->block, get_Mul_left(node), get_Mul_right(node));
652 mflo = new_rd_mips_mflo(env->dbg, env->irg, env->block, mul);
658 ir_node *gen_node_for_IJmp(mips_transform_env_t *env) {
659 ir_graph *irg = env->irg;
660 ir_node *node = env->irn;
661 dbg_info *dbg = get_irn_dbg_info(node);
662 ir_node *block = get_nodes_block(node);
663 ir_node *target = get_IJmp_target(node);
665 return new_rd_mips_jr(dbg, irg, block, target);
669 ir_node *gen_node_for_Jmp(mips_transform_env_t *env) {
670 ir_graph *irg = env->irg;
671 ir_node *node = env->irn;
672 dbg_info *dbg = get_irn_dbg_info(node);
673 ir_node *block = get_nodes_block(node);
675 return new_rd_mips_b(dbg, irg, block);
679 ir_node *gen_node_for_Abs(mips_transform_env_t *env) {
680 ir_node *node = env->irn;
681 ir_node *sra, *add, *xor;
684 // TODO for other bit sizes...
685 assert(get_mode_size_bits(env->mode) == 32);
686 sra = new_rd_mips_srai(env->dbg, env->irg, env->block, get_Abs_op(node));
687 attr = get_mips_attr(sra);
688 attr->tv = new_tarval_from_long(31, mode_Iu);
689 add = new_rd_mips_addu(env->dbg, env->irg, env->block, get_Abs_op(node), sra);
690 xor = new_rd_mips_xor(env->dbg, env->irg, env->block, sra, add);
696 ir_node *gen_node_for_Rot(mips_transform_env_t *env) {
697 ir_node *node = env->irn;
698 ir_node *subu, *srlv, *sllv, *or;
700 subu = new_rd_mips_subuzero(env->dbg, env->irg, env->block, get_Rot_right(node));
701 srlv = new_rd_mips_srlv(env->dbg, env->irg, env->block, get_Rot_left(node), subu);
702 sllv = new_rd_mips_sllv(env->dbg, env->irg, env->block, get_Rot_left(node), get_Rot_right(node));
703 or = new_rd_mips_or(env->dbg, env->irg, env->block, sllv, srlv);
708 static ir_node *gen_node_for_Unknown(mips_transform_env_t *env)
710 return gen_zero(env);
715 * lower a copyB into standard Firm assembler :-)
717 ir_node *gen_code_for_CopyB(ir_node *block, ir_node *node) {
719 ir_node *dst = get_CopyB_dst(node);
720 ir_node *src = get_CopyB_src(node);
721 ir_type *type = get_CopyB_type(node);
722 ir_node *mem = get_CopyB_mem(node);
724 ir_node *result = NULL;
725 int size = get_type_size_bytes(type);
726 dbg_info *dbg = get_irn_dbg_info(node);
727 ir_graph *irg = get_irn_irg(block);
732 ir_node *phi, *projT, *projF, *cmp, *proj, *cond, *jmp, *in[2];
733 ir_node *new_bl, *src_phi, *dst_phi, *mem_phi, *add;
734 ir_mode *p_mode = get_irn_mode(src);
737 /* build the control loop */
738 in[0] = in[1] = new_r_Unknown(irg, mode_X);
740 new_bl = new_r_Block(irg, 2, in);
742 in[0] = cnt = new_Const_long(mode_Is, (size >> 4));
743 in[1] = new_r_Unknown(irg, mode_Is);
744 phi = new_r_Phi(irg, new_bl, 2, in, mode_Is);
746 sub = new_rd_Sub(dbg, irg, new_bl, phi, new_Const_long(mode_Is, -1), mode_Is);
747 set_Phi_pred(phi, 1, sub);
749 cmp = new_rd_Cmp(dbg, irg, new_bl, sub, new_Const_long(mode_Is, 0));
750 proj = new_r_Proj(irg, new_bl, cmp, mode_b, pn_Cmp_Lg);
751 cond = new_rd_Cond(dbg, irg, new_bl, proj);
753 projT = new_r_Proj(irg, new_bl, cond, mode_X, pn_Cond_true);
754 projF = new_r_Proj(irg, new_bl, cond, mode_X, pn_Cond_false);
756 jmp = get_Block_cfgpred(block, 0);
757 set_Block_cfgpred(block, 0, projF);
759 set_Block_cfgpred(new_bl, 0, jmp);
760 set_Block_cfgpred(new_bl, 1, projT);
766 in[1] = new_r_Unknown(irg, p_mode);
767 src_phi = new_r_Phi(irg, new_bl, 2, in, p_mode);
770 dst_phi = new_r_Phi(irg, new_bl, 2, in, p_mode);
772 add = new_rd_Add(dbg, irg, new_bl, src_phi, new_Const_long(mode_Is, 16), p_mode);
773 set_Phi_pred(src_phi, 1, add);
774 add = new_rd_Add(dbg, irg, new_bl, dst_phi, new_Const_long(mode_Is, 16), p_mode);
775 set_Phi_pred(dst_phi, 1, add);
778 in[1] = new_r_Unknown(irg, mode_M);
779 mem_phi = new_r_Phi(irg, new_bl, 2, in, mode_M);
784 /* create 4 parallel loads */
785 for (i = 0; i < 4; ++i) {
788 load = new_rd_mips_load_r(dbg, irg, new_bl, mem_phi, src, mode_T);
789 attr = get_mips_attr(load);
790 attr->modes.load_store_mode = mode_Iu;
791 attr->tv = new_tarval_from_long(i * 4, mode_Iu);
793 ld[i] = new_rd_Proj(dbg, irg, new_bl, load, mode_Iu, pn_Load_res);
796 /* create 4 parallel stores */
797 for (i = 0; i < 4; ++i) {
800 store = new_rd_mips_store_r(dbg, irg, new_bl, mem_phi, dst, ld[i], mode_T);
801 attr = get_mips_attr(store);
802 attr->modes.load_store_mode = mode_Iu;
803 attr->tv = new_tarval_from_long(i * 4, mode_Iu);
805 mm[i] = new_rd_Proj(dbg, irg, new_bl, store, mode_M, pn_Store_M);
807 mem = new_r_Sync(irg, new_bl, 4, mm);
809 set_Phi_pred(mem_phi, 1, mem);
812 // output store/loads manually
814 for(i = size; i > 0; ) {
816 ir_node *load, *store, *projv;
817 int offset = size - i;
829 load = new_rd_mips_load_r(dbg, irg, block, mem, src, mode_T);
830 attr = get_mips_attr(load);
831 attr->modes.load_store_mode = mode;
832 attr->tv = new_tarval_from_long(offset, mode_Iu);
834 projv = new_rd_Proj(dbg, irg, block, load, mode, pn_Load_res);
836 store = new_rd_mips_store_r(dbg, irg, block, mem, dst, projv, mode_T);
837 attr = get_mips_attr(store);
838 attr->modes.load_store_mode = mode;
839 attr->tv = new_tarval_from_long(offset, mode_Iu);
841 mm[n] = new_rd_Proj(dbg, irg, block, store, mode_M, pn_Store_M);
846 result = new_r_Sync(irg, block, n, mm);
854 static void mips_fix_CopyB_Proj(mips_transform_env_t* env) {
855 ir_node *node = env->irn;
856 long n = get_Proj_proj(node);
858 if(n == pn_CopyB_M_except) {
860 } else if(n == pn_CopyB_M_regular) {
861 set_Proj_proj(node, pn_Store_M);
862 } else if(n == pn_CopyB_M_except) {
863 set_Proj_proj(node, pn_Store_X_except);
868 static void mips_transform_Spill(mips_transform_env_t* env) {
869 ir_node *node = env->irn;
870 ir_node *sched_point = NULL;
872 ir_node *nomem = new_rd_NoMem(env->irg);
873 ir_node *ptr = get_irn_n(node, 0);
874 ir_node *val = get_irn_n(node, 1);
875 ir_entity *ent = be_get_frame_entity(node);
878 if(sched_is_scheduled(node)) {
879 sched_point = sched_prev(node);
882 store = new_rd_mips_sw(env->dbg, env->irg, env->block, nomem, ptr, val);
883 attr = get_mips_attr(store);
884 attr->stack_entity = ent;
887 sched_add_after(sched_point, store);
891 exchange(node, store);
894 static void mips_transform_Reload(mips_transform_env_t* env) {
895 ir_node *node = env->irn;
896 ir_node *sched_point = NULL;
897 ir_node *load, *proj;
898 ir_node *ptr = get_irn_n(node, 0);
899 ir_node *mem = get_irn_n(node, 1);
900 ir_entity *ent = be_get_frame_entity(node);
901 const arch_register_t* reg;
904 if(sched_is_scheduled(node)) {
905 sched_point = sched_prev(node);
908 load = new_rd_mips_lw(env->dbg, env->irg, env->block, mem, ptr);
909 attr = get_mips_attr(load);
910 attr->stack_entity = ent;
912 proj = new_rd_Proj(env->dbg, env->irg, env->block, load, mode_Iu, pn_mips_lw_res);
915 sched_add_after(sched_point, load);
916 sched_add_after(load, proj);
921 /* copy the register from the old node to the new Load */
922 reg = arch_get_irn_register(env->cg->arch_env, node);
923 arch_set_irn_register(env->cg->arch_env, proj, reg);
925 exchange(node, proj);
929 static ir_node *gen_node_for_StackParam(mips_transform_env_t *env)
931 ir_node *node = env->irn;
932 ir_node *sp = get_irn_n(node, 0);
934 ir_node *nomem = new_rd_NoMem(env->irg);
938 load = new_rd_mips_load_r(env->dbg, env->irg, env->block, nomem, sp, mode_T);
939 attr = get_mips_attr(load);
940 attr->stack_entity = be_get_frame_entity(node);
941 attr->modes.load_store_mode = env->mode;
943 proj = new_rd_Proj(env->dbg, env->irg, env->block, load, env->mode, pn_Load_res);
949 static ir_node *gen_node_for_AddSP(mips_transform_env_t *env)
951 ir_node *node = env->irn;
954 const arch_register_t *reg;
956 op1 = get_irn_n(node, 0);
957 op2 = get_irn_n(node, 1);
959 add = new_rd_mips_addu(env->dbg, env->irg, env->block, op1, op2);
961 /* copy the register requirements from the old node to the new node */
962 reg = arch_get_irn_register(env->cg->arch_env, node);
963 arch_set_irn_register(env->cg->arch_env, add, reg);
968 /*********************************************************
971 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
972 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
973 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
974 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
976 *********************************************************/
980 * Transforms the given firm node (and maybe some other related nodes)
981 * into one or more assembler nodes.
983 * @param node the firm node
984 * @param env the debug module
986 void mips_transform_node(ir_node *node, void *env) {
987 mips_code_gen_t *cgenv = (mips_code_gen_t *)env;
988 ir_opcode code = get_irn_opcode(node);
989 ir_node *asm_node = node;
990 mips_transform_env_t tenv;
995 tenv.block = get_nodes_block(node);
996 tenv.dbg = get_irn_dbg_info(node);
997 tenv.irg = current_ir_graph;
999 tenv.mode = get_irn_mode(node);
1002 #define UNOP(firm_opcode, mips_nodetype) case iro_##firm_opcode: asm_node = mips_gen_##mips_nodetype(&tenv, get_##firm_opcode##_op(node)); break
1003 #define BINOP(firm_opcode, mips_nodetype) case iro_##firm_opcode: asm_node = mips_gen_##mips_nodetype(&tenv, get_##firm_opcode##_left(node), get_##firm_opcode##_right(node)); break
1004 #define IGN(a) case iro_##a: break
1005 #define BAD(a) case iro_##a: goto bad
1019 asm_node = gen_node_for_Abs(&tenv);
1023 asm_node = gen_node_for_Rot(&tenv);
1027 asm_node = gen_node_for_Div(&tenv);
1031 asm_node = gen_node_for_Mod(&tenv);
1035 asm_node = gen_node_for_Load(&tenv);
1039 asm_node = gen_node_for_Store(&tenv);
1043 asm_node = gen_node_for_Proj(&tenv);
1047 asm_node = gen_node_for_Conv(&tenv);
1051 asm_node = gen_node_for_DivMod(&tenv);
1055 asm_node = gen_node_for_Mul(&tenv);
1059 asm_node = gen_node_for_Jmp(&tenv);
1063 asm_node = gen_node_for_IJmp(&tenv);
1067 asm_node = gen_node_for_Unknown(&tenv);
1071 asm_node = gen_node_for_Cond(&tenv);
1075 asm_node = gen_node_for_Phi(&tenv);
1078 /* TODO: implement these nodes */
1081 /* You probably don't need to handle the following nodes */
1083 // call is handled in the emit phase
1085 // Cmp is handled together with Cond
1114 if(be_is_StackParam(node)) {
1115 //asm_node = gen_node_for_StackParam(&tenv);
1116 } else if(be_is_AddSP(node)) {
1117 asm_node = gen_node_for_AddSP(&tenv);
1122 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1126 if (asm_node != node) {
1127 exchange(node, asm_node);
1131 void mips_pre_transform_node(ir_node *node, void *env) {
1132 mips_code_gen_t *cgenv = (mips_code_gen_t *)env;
1135 mips_transform_env_t tenv;
1140 tenv.block = get_nodes_block(node);
1141 tenv.dbg = get_irn_dbg_info(node);
1142 tenv.irg = current_ir_graph;
1144 tenv.mode = get_irn_mode(node);
1149 ir_node* pred = get_Proj_pred(node);
1150 if(get_irn_opcode(pred) == iro_CopyB) {
1151 mips_fix_CopyB_Proj(&tenv);
1156 for(i = 0; i < get_irn_arity(node); ++i) {
1157 ir_node* pred = get_irn_n(node, i);
1159 if (is_Const(pred)) {
1160 ir_node* constnode = exchange_node_for_Const(&tenv, pred, i);
1161 set_irn_n(node, i, constnode);
1162 } else if (get_irn_op(pred) == op_SymConst) {
1163 ir_node* constnode = gen_node_for_SymConst(&tenv, pred);
1164 set_irn_n(node, i, constnode);
1170 * Calls the transform functions for Spill and Reload.
1172 void mips_after_ra_walker(ir_node *node, void *env) {
1173 mips_code_gen_t *cg = env;
1174 mips_transform_env_t tenv;
1179 tenv.block = get_nodes_block(node);
1180 tenv.dbg = get_irn_dbg_info(node);
1181 tenv.irg = current_ir_graph;
1183 tenv.mode = get_irn_mode(node);
1186 if (be_is_Reload(node)) {
1187 mips_transform_Reload(&tenv);
1188 } else if (be_is_Spill(node)) {
1189 mips_transform_Spill(&tenv);