1 /* The codegenrator (transform FIRM into mips FIRM */
11 #include "irgraph_t.h"
21 #include "../benode_t.h"
23 #include "../besched.h"
24 #include "../besched_t.h"
25 #include "bearch_mips_t.h"
27 #include "mips_nodes_attr.h"
28 #include "../arch/archop.h" /* we need this for Min and Max nodes */
29 #include "mips_transform.h"
30 #include "mips_new_nodes.h"
31 #include "mips_map_regs.h"
32 #include "mips_util.h"
33 #include "mips_emitter.h"
35 #include "gen_mips_regalloc_if.h"
37 /****************************************************************************************************
39 * | | | | / _| | | (_)
40 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
41 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
42 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
43 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
45 ****************************************************************************************************/
47 #define MIPS_GENBINFUNC(mips_nodetype) \
48 static ir_node* mips_gen_##mips_nodetype(mips_transform_env_t *env, ir_node *op1, ir_node *op2) {\
49 ASSERT_NO_FLOAT(env->mode); \
50 /*assert(get_irn_mode(op1) == get_irn_mode(op2));*/ \
51 /*assert(get_irn_mode(op1) == env->mode);*/ \
52 assert(get_mode_size_bits(env->mode) == 32); \
53 return new_rd_mips_##mips_nodetype(env->dbg, env->irg, env->block, op1, op2, env->mode);\
65 #define MIPS_GENUNFUNC(mips_nodetype) \
66 static ir_node *mips_gen_##mips_nodetype(mips_transform_env_t *env, ir_node *op) { \
67 ASSERT_NO_FLOAT(env->mode); \
68 assert(get_irn_mode(op) == env->mode); \
69 assert(get_mode_size_bits(env->mode) == 32); \
70 return new_rd_mips_##mips_nodetype(env->dbg, env->irg, env->block, op, env->mode); \
75 static ir_node* mips_get_reg_node(mips_transform_env_t *env, const arch_register_t *reg) {
76 return be_abi_get_callee_save_irn(env->cg->birg->abi, reg);
79 static ir_node* gen_zero_node(mips_transform_env_t *env, dbg_info *ebg, ir_graph *irg, ir_node *block)
81 ir_node *zero = be_abi_get_callee_save_irn(env->cg->birg->abi, &mips_gp_regs[REG_ZERO]);
82 // TODO make zero nodes work
83 //ir_node *unknown = new_rd_mips_zero(dbg, irg, block, mode);
88 static ir_node* gen_node_for_Const(mips_transform_env_t *env, dbg_info *dbg, ir_graph *irg, ir_node *block, ir_node *constant)
90 tarval* tv = get_Const_tarval(constant);
94 ir_mode* mode = get_irn_mode(constant);
95 unsigned long val, lower, upper;
97 val = get_tarval_long(tv);
99 return gen_zero_node(env, dbg, irg, block);
101 lower = val & 0xffff;
102 upper = (val >> 16) & 0xffff;
104 ir_node *zero = gen_zero_node(env, dbg, irg, block);
105 ir_node *lli = new_rd_mips_lli(dbg, irg, block, zero, mode);
106 attr = get_mips_attr(lli);
107 attr->tv = new_tarval_from_long(val, mode);
112 lui = new_rd_mips_lui(dbg, irg, block, mode);
113 attr = get_mips_attr(lui);
114 attr->tv = new_tarval_from_long(val, mode);
119 lli = new_rd_mips_lli(dbg, irg, block, lui, mode);
120 attr = get_mips_attr(lli);
121 attr->tv = new_tarval_from_long(val, mode);
126 static ir_node* exchange_node_for_Const(mips_transform_env_t *env, ir_node* pred, int n) {
127 ir_node *node = env->irn;
128 dbg_info *dbg = get_irn_dbg_info(pred);
129 ir_graph *irg = get_irn_irg(node);
132 if(get_irn_opcode(node) == iro_Phi) {
133 ir_node *phipred = get_nodes_block(node);
134 block = get_Block_cfgpred_block(phipred, n);
136 block = get_nodes_block(node);
139 return gen_node_for_Const(env, dbg, irg, block, pred);
142 static ir_node* gen_node_for_SymConst(mips_transform_env_t *env, ir_node* pred, int n) {
146 ir_node *node = env->irn;
147 dbg_info *dbg = get_irn_dbg_info(pred);
148 ir_graph *irg = get_irn_irg(node);
149 ir_mode* mode = get_irn_mode(pred);
153 ir_node *phipred = get_nodes_block(node);
154 block = get_Block_cfgpred_block(phipred, n);
156 block = get_nodes_block(node);
159 kind = get_SymConst_kind(pred);
160 if(kind == symconst_addr_ent) {
161 result = new_rd_mips_la(dbg, irg, block, mode);
162 attr = get_mips_attr(result);
163 attr->symconst_id = get_entity_ld_ident(get_SymConst_entity(pred));
165 } else if(kind == symconst_addr_name) {
166 result = new_rd_mips_la(dbg, irg, block, mode);
167 attr = get_mips_attr(result);
168 attr->symconst_id = get_SymConst_name(pred);
178 * Generates a mips node for a firm Load node
180 static ir_node *gen_node_for_Load(mips_transform_env_t *env) {
181 ir_node *node = env->irn;
182 ir_node *result = NULL;
187 ASSERT_NO_FLOAT(get_irn_mode(node));
189 mode = get_Load_mode(node);
190 assert(mode->vector_elem == 1);
191 assert(mode->sort == irms_int_number || mode->sort == irms_reference);
193 load_ptr = get_Load_ptr(node);
194 assert(get_mode_sort(mode) == irms_reference || get_mode_sort(mode) == irms_int_number);
195 result = new_rd_mips_load_r(env->dbg, env->irg, env->block,
196 get_Load_mem(node), load_ptr, get_irn_mode(node));
198 attr = get_mips_attr(result);
199 attr->tv = new_tarval_from_long(0, mode_Iu);
200 attr->modes.load_store_mode = mode;
206 * Generates a mips node for a firm Store node
208 static ir_node *gen_node_for_Store(mips_transform_env_t *env) {
209 ir_node *node = env->irn;
210 ir_node *result = NULL;
215 ASSERT_NO_FLOAT(env->mode);
217 store_ptr = get_Store_ptr(node);
218 mode = get_irn_mode(store_ptr);
219 assert(mode->vector_elem == 1);
220 assert(mode->sort == irms_int_number || mode->sort == irms_reference);
222 if(get_irn_opcode(store_ptr) == iro_SymConst) {
223 result = new_rd_mips_store_i(env->dbg, env->irg, env->block, get_Store_mem(node),
224 get_Store_ptr(node), get_Store_value(node), env->mode);
226 result = new_rd_mips_store_r(env->dbg, env->irg, env->block, get_Store_mem(node),
227 get_Store_ptr(node), get_Store_value(node), env->mode);
229 attr = get_mips_attr(result);
230 attr->tv = new_tarval_from_long(0, mode_Iu);
231 attr->modes.load_store_mode = mode;
236 static ir_node *gen_node_for_div_Proj(mips_transform_env_t *env) {
237 ir_node *proj = env->irn;
239 ir_node *pred = get_irn_n(proj, 0);
243 n = get_Proj_proj(proj);
245 // set the div mode to the DivMod node
246 attr = get_mips_attr(pred);
247 assert(attr->modes.original_mode == NULL || attr->modes.original_mode == env->mode);
248 attr->modes.original_mode = env->mode;
250 // we have to construct a new proj here, to avoid circular refs that
251 // happen when we reuse the old one
252 new_proj = new_ir_node(env->dbg, env->irg, env->block, op_Proj, mode_ANY, 1, &pred);
253 set_Proj_proj(new_proj, n);
255 if(n == pn_DivMod_res_div) {
256 return new_rd_mips_mflo(env->dbg, env->irg, env->block, new_proj, env->mode);
257 } else if(n == pn_DivMod_res_mod) {
258 return new_rd_mips_mfhi(env->dbg, env->irg, env->block, new_proj, env->mode);
264 static ir_node *make_jmp_or_fallthrough(mips_transform_env_t *env)
266 const ir_edge_t *edge;
267 ir_node *node = env->irn;
269 int our_block_sched_nr = mips_get_block_sched_nr(get_nodes_block(node));
271 edge = get_irn_out_edge_first(node);
272 next_block = get_edge_src_irn(edge);
274 if(mips_get_sched_block(env->cg, our_block_sched_nr + 1) == next_block) {
275 return new_rd_mips_fallthrough(env->dbg, env->irg, env->block, mode_X);
278 return new_rd_mips_b(env->dbg, env->irg, env->block, mode_X);
281 static ir_node *gen_node_for_Cond_Proj(mips_transform_env_t *env, ir_node* node, int true_false)
283 // we can't use get_Cond_selector here because the selector is already
284 // replaced by a mips_ compare node
285 ir_node *proj = get_Cond_selector(node);
286 ir_node *original_cmp = get_irn_n(proj, 0);
290 dbg_info *dbg = env->dbg;
291 ir_graph *irg = env->irg;
292 ir_node *block = env->block;
295 n = get_Proj_proj(proj);
296 assert(n < 8 && "Only ordered comps supported");
298 assert(get_irn_opcode(original_cmp) == iro_Cmp);
299 op1 = get_Cmp_left(original_cmp);
300 op2 = get_Cmp_right(original_cmp);
307 return make_jmp_or_fallthrough(env);
311 return make_jmp_or_fallthrough(env);
313 condjmp = new_rd_mips_beq(dbg, irg, block, op1, op2, mode_T);
314 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
318 return make_jmp_or_fallthrough(env);
320 cmp = new_rd_mips_slt(dbg, irg, block, op1, op2, get_irn_mode(op1));
321 condjmp = new_rd_mips_bgtz(dbg, irg, block, cmp, mode_T);
322 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
326 return make_jmp_or_fallthrough(env);
328 cmp = new_rd_mips_slt(dbg, irg, block, op2, op1, get_irn_mode(op1));
329 condjmp = new_rd_mips_blez(dbg, irg, block, cmp, mode_T);
330 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
334 return make_jmp_or_fallthrough(env);
336 cmp = new_rd_mips_slt(dbg, irg, block, op2, op1, get_irn_mode(op1));
337 condjmp = new_rd_mips_bgtz(dbg, irg, block, cmp, mode_T);
338 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
342 return make_jmp_or_fallthrough(env);
344 cmp = new_rd_mips_slt(dbg, irg, block, op1, op2, get_irn_mode(op1));
345 condjmp = new_rd_mips_blez(dbg, irg, block, cmp, mode_T);
346 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
350 return make_jmp_or_fallthrough(env);
352 condjmp = new_rd_mips_bne(dbg, irg, block, op1, op2, mode_T);
353 return new_rd_Proj(dbg, irg, block, condjmp, mode_X, 1);
359 return make_jmp_or_fallthrough(env);
368 static ir_node *gen_node_for_Proj(mips_transform_env_t *env)
370 ir_node *proj = env->irn;
372 ir_node *predecessor = get_Proj_pred(proj);
374 // all DivMods, Div, Mod should be replaced by now
375 assert(get_irn_opcode(predecessor) != iro_DivMod);
376 assert(get_irn_opcode(predecessor) != iro_Div);
377 assert(get_irn_opcode(predecessor) != iro_Mod);
379 if(is_mips_div(predecessor))
380 return gen_node_for_div_Proj(env);
382 if(get_irn_opcode(predecessor) == iro_Cond) {
383 ir_node *selector = get_Cond_selector(predecessor);
384 ir_mode *mode = get_irn_mode(selector);
385 n = get_Proj_proj(proj);
387 if(get_mode_sort(mode) == irms_internal_boolean) {
388 assert(n == pn_Cond_true || n == pn_Cond_false);
389 return gen_node_for_Cond_Proj(env, predecessor, n == pn_Cond_true);
396 static ir_node *gen_node_for_Cond(mips_transform_env_t *env)
398 ir_node *selector = get_Cond_selector(env->irn);
399 ir_mode *selector_mode = get_irn_mode(selector);
400 ir_node *node = env->irn;
401 dbg_info *dbg = env->dbg;
402 ir_graph *irg = env->irg;
403 ir_node *block = env->block;
404 ir_node *sub, *sltu, *minval_const, *max_const, *switchjmp;
405 ir_node *defaultproj, *defaultproj_succ;
407 long pn, minval, maxval, defaultprojn;
408 const ir_edge_t *edge;
409 ir_node *zero, *two_const, *add, *la, *load, *proj;
410 ir_mode *unsigned_mode;
413 // mode_b conds are handled by gen_node_for_Proj
414 if(get_mode_sort(selector_mode) != irms_int_number)
417 assert(get_mode_size_bits(selector_mode) == 32);
419 defaultprojn = get_Cond_defaultProj(node);
421 // go over all projs to find min-&maxval of the switch
424 foreach_out_edge(node, edge) {
425 ir_node* proj = get_edge_src_irn(edge);
426 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
428 pn = get_Proj_proj(proj);
429 if(pn == defaultprojn) {
439 assert(defaultproj != NULL);
441 // subtract minval from the switch value
444 minval_const = new_rd_Const(dbg, irg, block, selector_mode, new_tarval_from_long(minval, selector_mode));
445 minval_const = gen_node_for_Const(env, dbg, irg, block, minval_const);
446 sub = new_rd_mips_sub(dbg, irg, block, selector, minval_const, selector_mode);
451 // compare if we're above maxval-minval or below zero.
452 // we can do this with 1 compare because we use unsigned mode
453 unsigned_mode = new_ir_mode(get_mode_name(selector_mode),
454 get_mode_sort(selector_mode), get_mode_size_bits(selector_mode),
455 0, get_mode_arithmetic(selector_mode), get_mode_modulo_shift(selector_mode));
457 max_const = new_rd_Const(dbg, irg, block, unsigned_mode, new_tarval_from_long(maxval - minval + 1, unsigned_mode));
458 max_const = gen_node_for_Const(env, dbg, irg, block, max_const);
459 sltu = new_rd_mips_slt(dbg, irg, block, sub, max_const, unsigned_mode);
461 zero = gen_zero_node(env, dbg, irg, block);
462 beq = new_rd_mips_beq(dbg, irg, block, sltu, zero, mode_T);
464 // attach defaultproj to beq now
465 set_irn_n(defaultproj, 0, beq);
466 set_Proj_proj(defaultproj, 1);
468 two_const = new_rd_Const(dbg, irg, block, unsigned_mode, new_tarval_from_long(2, unsigned_mode));
469 two_const = gen_node_for_Const(env, dbg, irg, block, two_const);
470 sl = new_rd_mips_sl(dbg, irg, block, sub, two_const, unsigned_mode);
472 la = new_rd_mips_la(dbg, irg, block, mode_Iu);
473 add = new_rd_mips_add(dbg, irg, block, sl, la, mode_Iu);
474 load = new_rd_mips_load_r(dbg, irg, block, new_rd_NoMem(irg), add, mode_T);
475 attr = get_mips_attr(load);
476 attr->modes.load_store_mode = mode_Iu;
477 attr->tv = new_tarval_from_long(0, mode_Iu);
479 proj = new_rd_Proj(dbg, irg, block, load, mode_Iu, pn_Load_res);
481 switchjmp = new_rd_mips_SwitchJump(dbg, irg, block, proj, mode_T);
482 attr = get_mips_attr(switchjmp);
483 attr->switch_default_pn = defaultprojn;
485 edge = get_irn_out_edge_first(defaultproj);
486 defaultproj_succ = get_edge_src_irn(edge);
487 attr->symconst_id = new_id_from_str(mips_get_block_label(defaultproj_succ));
489 attr = get_mips_attr(la);
490 attr->symconst_id = new_id_from_str(mips_get_jumptbl_label(switchjmp));
495 static ir_node *create_conv_store_load(mips_transform_env_t *env, ir_mode* srcmode, ir_mode* dstmode) {
496 ir_node *nomem, *store, *mem_proj, *value_proj, *load;
498 ir_node *node = env->irn;
499 ir_node *pred = get_Conv_op(node);
501 // TODO HACK make this global...
504 ir_type *ptr_i32type;
507 id = new_id_from_str("__conv0");
508 i32type = new_type_primitive(new_id_from_str("ptr32"), mode_Iu);
509 ptr_i32type = new_d_type_pointer(id, i32type, mode_P, env->dbg);
510 mem_entity = new_d_entity(get_irg_frame_type(env->irg), id, ptr_i32type, env->dbg);
512 sp = mips_get_reg_node(env, &mips_gp_regs[REG_SP]);
513 nomem = new_ir_node(env->dbg, env->irg, env->block, op_NoMem, mode_M, 0, NULL);
515 store = new_rd_mips_store_r(env->dbg, env->irg, env->block, nomem, sp, pred, mode_T);
516 attr = get_mips_attr(store);
517 attr->tv = new_tarval_from_long(0, mode_Iu);
518 attr->modes.load_store_mode = srcmode;
519 attr->stack_entity = mem_entity;
521 mem_proj = new_ir_node(env->dbg, env->irg, env->block, op_Proj, mode_M, 1, &store);
522 set_Proj_proj(mem_proj, pn_Store_M);
524 load = new_rd_mips_load_r(env->dbg, env->irg, env->block, mem_proj, sp, mode_T);
525 attr = get_mips_attr(load);
526 attr->tv = new_tarval_from_long(0, mode_Iu);
527 attr->modes.load_store_mode = dstmode;
528 attr->stack_entity = mem_entity;
530 value_proj = new_ir_node(env->dbg, env->irg, env->block, op_Proj, env->mode, 1, &load);
531 set_Proj_proj(value_proj, pn_Load_res);
536 static ir_node *create_conv_and(mips_transform_env_t *env, long immediate) {
537 ir_node *node = env->irn;
542 pred = get_Conv_op(node);
543 result = new_rd_mips_andi(env->dbg, env->irg, env->block, pred, node->mode);
544 attr = get_mips_attr(result);
545 attr->tv = new_tarval_from_long(immediate, mode_Iu);
550 static ir_node *gen_node_for_Conv(mips_transform_env_t *env) {
551 ir_node *node = env->irn;
555 int dst_size, src_size;
557 pred = get_Conv_op(node);
558 srcmode = get_irn_mode(pred);
559 destmode = get_irn_mode(node);
561 dst_size = get_mode_size_bits(destmode);
562 src_size = get_mode_size_bits(srcmode);
564 if(srcmode->size >= destmode->size) {
565 assert(srcmode->size > destmode->size || srcmode->sign != destmode->sign);
566 return new_rd_mips_reinterpret_conv(env->dbg, env->irg, env->block, pred, node->mode);
569 if(srcmode->size == 8) {
570 return create_conv_store_load(env, mode_Bs, mode_Bs);
571 } else if(srcmode->size == 16) {
572 return create_conv_store_load(env, mode_Hs, mode_Hs);
576 return create_conv_and(env, 0xff);
577 } else if(src_size == 16) {
578 return create_conv_and(env, 0xffff);
586 static ir_node *gen_node_mips_div(mips_transform_env_t *env, ir_node* op1, ir_node* op2, long p_div, long p_mod,
589 ir_node *node = env->irn;
591 const ir_edge_t *edge;
593 div = new_rd_mips_div(env->dbg, env->irg, env->block, op1, op2, mode_T);
596 foreach_out_edge(node, edge) {
597 ir_node *proj = get_edge_src_irn(edge);
598 long n = get_Proj_proj(proj);
599 assert(is_Proj(proj) && "non-Proj from Mod node");
601 set_Proj_proj(proj, pn_DivMod_res_div);
602 } else if (n == p_mod) {
603 set_Proj_proj(proj, pn_DivMod_res_mod);
604 } else if(n == p_m) {
605 set_Proj_proj(proj, pn_DivMod_M);
606 } else if(n == p_x) {
607 set_Proj_proj(proj, pn_DivMod_X_except);
609 assert(!"invalid proj");
616 static ir_node *gen_node_for_DivMod(mips_transform_env_t *env) {
617 ir_node *node = env->irn;
619 return gen_node_mips_div(env, get_DivMod_left(node), get_DivMod_right(node), pn_DivMod_res_div,
620 pn_DivMod_res_mod, pn_DivMod_M, pn_DivMod_X_except);
623 static ir_node *gen_node_for_Div(mips_transform_env_t *env) {
624 ir_node *node = env->irn;
626 return gen_node_mips_div(env, get_Div_left(node), get_Div_right(node), pn_Div_res, -1,
627 pn_Div_M, pn_Div_X_except);
630 static ir_node *gen_node_for_Mod(mips_transform_env_t *env) {
631 ir_node *node = env->irn;
633 return gen_node_mips_div(env, get_Mod_left(node), get_Mod_right(node), -1, pn_Mod_res,
634 pn_Mod_M, pn_Mod_X_except);
637 static ir_node *gen_node_for_Mul(mips_transform_env_t *env) {
638 ir_node *node = env->irn;
643 op1 = get_Mul_left(node);
644 op2 = get_Mul_right(node);
646 assert(get_mode_size_bits(env->mode) == 32);
647 assert(get_mode_size_bits(get_irn_mode(op1)) == get_mode_size_bits(env->mode));
648 assert(get_mode_size_bits(get_irn_mode(op2)) == get_mode_size_bits(env->mode));
650 mul = new_rd_mips_mult(env->dbg, env->irg, env->block, get_Mul_left(node), get_Mul_right(node), env->mode);
651 mflo = new_rd_mips_mflo(env->dbg, env->irg, env->block, mul, env->mode);
656 static ir_node *gen_node_for_IJmp(mips_transform_env_t *env) {
657 ir_node *node = env->irn;
659 return new_rd_mips_j(env->dbg, env->irg, env->block, get_IJmp_target(node), node->mode);
662 static ir_node *gen_node_for_Jmp(mips_transform_env_t *env) {
663 return make_jmp_or_fallthrough(env);
666 static ir_node *gen_node_for_Abs(mips_transform_env_t *env) {
667 ir_node *node = env->irn;
668 ir_node *sra, *add, *xor;
671 // TODO for other bit sizes...
672 assert(get_mode_size_bits(env->mode) == 32);
673 sra = new_rd_mips_srai(env->dbg, env->irg, env->block, get_Abs_op(node), node->mode);
674 attr = get_mips_attr(sra);
675 attr->tv = new_tarval_from_long(31, mode_Iu);
676 add = new_rd_mips_add(env->dbg, env->irg, env->block, get_Abs_op(node), sra, node->mode);
677 xor = new_rd_mips_xor(env->dbg, env->irg, env->block, sra, add, node->mode);
682 static ir_node *gen_node_for_Rot(mips_transform_env_t *env) {
683 ir_node *node = env->irn;
684 ir_node *subu, *srlv, *sllv, *or;
686 subu = new_rd_mips_subuzero(env->dbg, env->irg, env->block, get_Rot_right(node), env->mode);
687 srlv = new_rd_mips_srlv(env->dbg, env->irg, env->block, get_Rot_left(node), subu, env->mode);
688 sllv = new_rd_mips_sllv(env->dbg, env->irg, env->block, get_Rot_left(node), get_Rot_right(node), env->mode);
689 or = new_rd_mips_or(env->dbg, env->irg, env->block, sllv, srlv, env->mode);
694 static ir_node *gen_node_for_Unknown(mips_transform_env_t *env)
696 return gen_zero_node(env, env->dbg, env->irg, env->block);
700 * lower a copyB into standard Firm assembler :-)
702 ir_node *gen_code_for_CopyB(ir_node *block, ir_node *node) {
704 ir_node *dst = get_CopyB_dst(node);
705 ir_node *src = get_CopyB_src(node);
706 ir_type *type = get_CopyB_type(node);
707 ir_node *mem = get_CopyB_mem(node);
709 ir_node *result = NULL;
710 int size = get_type_size_bytes(type);
711 dbg_info *dbg = get_irn_dbg_info(node);
712 ir_graph *irg = get_irn_irg(block);
717 ir_node *phi, *projT, *projF, *cmp, *proj, *cond, *jmp, *in[2];
718 ir_node *new_bl, *src_phi, *dst_phi, *mem_phi, *add;
719 ir_mode *p_mode = get_irn_mode(src);
722 /* build the control loop */
723 in[0] = in[1] = new_r_Unknown(irg, mode_X);
725 new_bl = new_r_Block(irg, 2, in);
727 in[0] = cnt = new_Const_long(mode_Is, (size >> 4));
728 in[1] = new_r_Unknown(irg, mode_Is);
729 phi = new_r_Phi(irg, new_bl, 2, in, mode_Is);
731 sub = new_rd_Sub(dbg, irg, new_bl, phi, new_Const_long(mode_Is, -1), mode_Is);
732 set_Phi_pred(phi, 1, sub);
734 cmp = new_rd_Cmp(dbg, irg, new_bl, sub, new_Const_long(mode_Is, 0));
735 proj = new_r_Proj(irg, new_bl, cmp, mode_b, pn_Cmp_Lg);
736 cond = new_rd_Cond(dbg, irg, new_bl, proj);
738 projT = new_r_Proj(irg, new_bl, cond, mode_X, pn_Cond_true);
739 projF = new_r_Proj(irg, new_bl, cond, mode_X, pn_Cond_false);
741 jmp = get_Block_cfgpred(block, 0);
742 set_Block_cfgpred(block, 0, projF);
744 set_Block_cfgpred(new_bl, 0, jmp);
745 set_Block_cfgpred(new_bl, 1, projT);
751 in[1] = new_r_Unknown(irg, p_mode);
752 src_phi = new_r_Phi(irg, new_bl, 2, in, p_mode);
755 dst_phi = new_r_Phi(irg, new_bl, 2, in, p_mode);
757 add = new_rd_Add(dbg, irg, new_bl, src_phi, new_Const_long(mode_Is, 16), p_mode);
758 set_Phi_pred(src_phi, 1, add);
759 add = new_rd_Add(dbg, irg, new_bl, dst_phi, new_Const_long(mode_Is, 16), p_mode);
760 set_Phi_pred(dst_phi, 1, add);
763 in[1] = new_r_Unknown(irg, mode_M);
764 mem_phi = new_r_Phi(irg, new_bl, 2, in, mode_M);
769 /* create 4 parallel loads */
770 for (i = 0; i < 4; ++i) {
773 load = new_rd_mips_load_r(dbg, irg, new_bl, mem_phi, src, mode_T);
774 attr = get_mips_attr(load);
775 attr->modes.load_store_mode = mode_Iu;
776 attr->tv = new_tarval_from_long(i * 4, mode_Iu);
778 ld[i] = new_rd_Proj(dbg, irg, new_bl, load, mode_Iu, pn_Load_res);
781 /* create 4 parallel stores */
782 for (i = 0; i < 4; ++i) {
785 store = new_rd_mips_store_r(dbg, irg, new_bl, mem_phi, dst, ld[i], mode_T);
786 attr = get_mips_attr(store);
787 attr->modes.load_store_mode = mode_Iu;
788 attr->tv = new_tarval_from_long(i * 4, mode_Iu);
790 mm[i] = new_rd_Proj(dbg, irg, new_bl, store, mode_M, pn_Store_M);
792 mem = new_r_Sync(irg, new_bl, 4, mm);
794 set_Phi_pred(mem_phi, 1, mem);
797 // output store/loads manually
799 for(i = size; i > 0; ) {
801 ir_node *load, *store, *projv;
802 int offset = size - i;
814 load = new_rd_mips_load_r(dbg, irg, block, mem, src, mode_T);
815 attr = get_mips_attr(load);
816 attr->modes.load_store_mode = mode;
817 attr->tv = new_tarval_from_long(offset, mode_Iu);
819 projv = new_rd_Proj(dbg, irg, block, load, mode, pn_Load_res);
821 store = new_rd_mips_store_r(dbg, irg, block, mem, dst, projv, mode_T);
822 attr = get_mips_attr(store);
823 attr->modes.load_store_mode = mode;
824 attr->tv = new_tarval_from_long(offset, mode_Iu);
826 mm[n] = new_rd_Proj(dbg, irg, block, store, mode_M, pn_Store_M);
831 result = new_r_Sync(irg, block, n, mm);
839 static void mips_fix_CopyB_Proj(mips_transform_env_t* env) {
840 ir_node *node = env->irn;
841 long n = get_Proj_proj(node);
843 if(n == pn_CopyB_M_except) {
845 } else if(n == pn_CopyB_M_regular) {
846 set_Proj_proj(node, pn_Store_M);
847 } else if(n == pn_CopyB_M_except) {
848 set_Proj_proj(node, pn_Store_X_except);
852 static void mips_transform_Spill(mips_transform_env_t* env) {
853 ir_node *node = env->irn;
854 ir_node *sched_point = NULL;
855 ir_node *store, *proj;
856 ir_node *nomem = new_rd_NoMem(env->irg);
857 ir_node *ptr = get_irn_n(node, 0);
858 ir_node *val = get_irn_n(node, 1);
859 entity *ent = be_get_frame_entity(node);
862 if(sched_is_scheduled(node)) {
863 sched_point = sched_prev(node);
866 store = new_rd_mips_store_r(env->dbg, env->irg, env->block, nomem, ptr, val, mode_T);
867 attr = get_mips_attr(store);
868 attr->stack_entity = ent;
869 attr->modes.load_store_mode = get_irn_mode(val);
871 proj = new_rd_Proj(env->dbg, env->irg, env->block, store, mode_M, pn_Store_M);
874 sched_add_after(sched_point, store);
875 sched_add_after(store, proj);
880 exchange(node, proj);
883 static void mips_transform_Reload(mips_transform_env_t* env) {
884 ir_node *node = env->irn;
885 ir_node *sched_point = NULL;
886 ir_node *load, *proj;
887 ir_node *ptr = get_irn_n(node, 0);
888 ir_node *mem = get_irn_n(node, 1);
889 ir_mode *mode = get_irn_mode(node);
890 entity *ent = be_get_frame_entity(node);
891 const arch_register_t* reg;
894 if(sched_is_scheduled(node)) {
895 sched_point = sched_prev(node);
898 load = new_rd_mips_load_r(env->dbg, env->irg, env->block, mem, ptr, mode_T);
899 attr = get_mips_attr(load);
900 attr->stack_entity = ent;
901 attr->modes.load_store_mode = mode;
903 proj = new_rd_Proj(env->dbg, env->irg, env->block, load, mode, pn_Load_res);
906 sched_add_after(sched_point, load);
907 sched_add_after(load, proj);
912 /* copy the register from the old node to the new Load */
913 reg = arch_get_irn_register(env->cg->arch_env, node);
914 arch_set_irn_register(env->cg->arch_env, proj, reg);
916 exchange(node, proj);
919 static ir_node *gen_node_for_StackParam(mips_transform_env_t *env)
921 ir_node *node = env->irn;
922 ir_node *sp = get_irn_n(node, 0);
924 ir_node *nomem = new_rd_NoMem(env->irg);
928 load = new_rd_mips_load_r(env->dbg, env->irg, env->block, nomem, sp, mode_T);
929 attr = get_mips_attr(load);
930 attr->stack_entity = be_get_frame_entity(node);
931 attr->modes.load_store_mode = env->mode;
933 proj = new_rd_Proj(env->dbg, env->irg, env->block, load, env->mode, pn_Load_res);
938 static ir_node *gen_node_for_AddSP(mips_transform_env_t *env)
940 ir_node *node = env->irn;
943 const arch_register_t *reg;
945 op1 = get_irn_n(node, 0);
946 op2 = get_irn_n(node, 1);
948 add = new_rd_mips_add(env->dbg, env->irg, env->block, op1, op2, mode_Iu);
950 /* copy the register requirements from the old node to the new node */
951 reg = arch_get_irn_register(env->cg->arch_env, node);
952 arch_set_irn_register(env->cg->arch_env, add, reg);
957 /*********************************************************
960 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
961 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
962 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
963 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
965 *********************************************************/
969 * Transforms the given firm node (and maybe some other related nodes)
970 * into one or more assembler nodes.
972 * @param node the firm node
973 * @param env the debug module
975 void mips_transform_node(ir_node *node, void *env) {
976 mips_code_gen_t *cgenv = (mips_code_gen_t *)env;
977 opcode code = get_irn_opcode(node);
978 ir_node *asm_node = node;
979 mips_transform_env_t tenv;
984 tenv.block = get_nodes_block(node);
985 tenv.dbg = get_irn_dbg_info(node);
986 tenv.irg = current_ir_graph;
988 DEBUG_ONLY(tenv.mod = cgenv->mod;)
989 tenv.mode = get_irn_mode(node);
992 #define UNOP(firm_opcode, mips_nodetype) case iro_##firm_opcode: asm_node = mips_gen_##mips_nodetype(&tenv, get_##firm_opcode##_op(node)); break
993 #define BINOP(firm_opcode, mips_nodetype) case iro_##firm_opcode: asm_node = mips_gen_##mips_nodetype(&tenv, get_##firm_opcode##_left(node), get_##firm_opcode##_right(node)); break
994 #define IGN(a) case iro_##a: break
995 #define BAD(a) case iro_##a: goto bad
997 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1011 asm_node = gen_node_for_Abs(&tenv);
1015 asm_node = gen_node_for_Rot(&tenv);
1019 asm_node = gen_node_for_Div(&tenv);
1023 asm_node = gen_node_for_Mod(&tenv);
1027 asm_node = gen_node_for_Load(&tenv);
1031 asm_node = gen_node_for_Store(&tenv);
1035 asm_node = gen_node_for_Proj(&tenv);
1039 asm_node = gen_node_for_Conv(&tenv);
1043 asm_node = gen_node_for_DivMod(&tenv);
1047 asm_node = gen_node_for_Mul(&tenv);
1051 asm_node = gen_node_for_Jmp(&tenv);
1055 asm_node = gen_node_for_IJmp(&tenv);
1059 asm_node = gen_node_for_Unknown(&tenv);
1063 asm_node = gen_node_for_Cond(&tenv);
1066 /* TODO: implement these nodes */
1069 /* You probably don't need to handle the following nodes */
1071 // call is handled in the emit phase
1073 // Cmp is handled together with Cond
1103 if(be_is_StackParam(node)) {
1104 asm_node = gen_node_for_StackParam(&tenv);
1105 } else if(be_is_AddSP(node)) {
1106 asm_node = gen_node_for_AddSP(&tenv);
1111 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1115 if (asm_node != node) {
1116 exchange(node, asm_node);
1117 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1119 DB((tenv.mod, LEVEL_1, "ignored\n"));
1123 void mips_pre_transform_node(ir_node *node, void *env) {
1124 mips_code_gen_t *cgenv = (mips_code_gen_t *)env;
1127 mips_transform_env_t tenv;
1132 tenv.block = get_nodes_block(node);
1133 tenv.dbg = get_irn_dbg_info(node);
1134 tenv.irg = current_ir_graph;
1136 DEBUG_ONLY(tenv.mod = cgenv->mod;)
1137 tenv.mode = get_irn_mode(node);
1141 ir_node* pred = get_Proj_pred(node);
1143 if(get_irn_opcode(pred) == iro_CopyB) {
1144 mips_fix_CopyB_Proj(&tenv);
1148 for(i = 0; i < get_irn_arity(node); ++i) {
1149 ir_node* pred = get_irn_n(node, i);
1151 if (is_Const(pred)) {
1152 ir_node* constnode = exchange_node_for_Const(&tenv, pred, i);
1153 set_irn_n(node, i, constnode);
1154 } else if (get_irn_op(pred) == op_SymConst) {
1155 ir_node* constnode = gen_node_for_SymConst(&tenv, pred, i);
1156 set_irn_n(node, i, constnode);
1162 * Calls the transform functions for Spill and Reload.
1164 void mips_after_ra_walker(ir_node *node, void *env) {
1165 mips_code_gen_t *cg = env;
1166 mips_transform_env_t tenv;
1171 tenv.block = get_nodes_block(node);
1172 tenv.dbg = get_irn_dbg_info(node);
1173 tenv.irg = current_ir_graph;
1175 DEBUG_ONLY(tenv.mod = cg->mod;)
1176 tenv.mode = get_irn_mode(node);
1179 /* be_is_StackParam(node) || */
1180 if (be_is_Reload(node)) {
1181 mips_transform_Reload(&tenv);
1182 } else if (be_is_Spill(node)) {
1183 mips_transform_Spill(&tenv);