2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch_t.h"
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a mips node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
91 arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X || mode == mode_M) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
105 /* in case of a proj, we need to get the correct OUT slot */
106 /* of the node corresponding to the proj number */
108 node_pos = mips_translate_proj_pos(node);
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_mips_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_mips_in_req(node, pos);
123 req = get_mips_out_req(node, node_pos);
129 /* unknown should be translated by now */
130 assert(!is_Unknown(node));
132 return arch_no_register_req;
135 static arch_irn_class_t mips_classify(const ir_node *irn)
137 irn = skip_Proj_const(irn);
140 return arch_irn_class_branch;
146 int mips_is_Load(const ir_node *node)
148 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
149 is_mips_lb(node) || is_mips_lbu(node);
152 int mips_is_Store(const ir_node *node)
154 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
157 static ir_entity *mips_get_frame_entity(const ir_node *node)
159 const mips_load_store_attr_t *attr;
161 if(!is_mips_irn(node))
163 if(!mips_is_Load(node) && !mips_is_Store(node))
166 attr = get_mips_load_store_attr_const(node);
167 return attr->stack_entity;
170 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
172 mips_load_store_attr_t *attr;
174 if(!is_mips_irn(node)) {
175 panic("trying to set frame entity on non load/store node %+F", node);
177 if(!mips_is_Load(node) && !mips_is_Store(node)) {
178 panic("trying to set frame entity on non load/store node %+F", node);
181 attr = get_irn_generic_attr(node);
182 attr->stack_entity = entity;
186 * This function is called by the generic backend to correct offsets for
187 * nodes accessing the stack.
189 static void mips_set_frame_offset(ir_node *node, int offset)
191 mips_load_store_attr_t *attr;
193 if(!is_mips_irn(node)) {
194 panic("trying to set frame offset on non load/store node %+F", node);
196 if(!mips_is_Load(node) && !mips_is_Store(node)) {
197 panic("trying to set frame offset on non load/store node %+F", node);
200 attr = get_irn_generic_attr(node);
201 attr->offset += offset;
203 if(attr->offset < -32768 || attr->offset > 32767) {
204 panic("Out of stack space! (mips supports only 16bit offsets)");
208 static int mips_get_sp_bias(const ir_node *irn)
214 /* fill register allocator interface */
216 static const arch_irn_ops_t mips_irn_ops = {
217 mips_get_irn_reg_req,
219 mips_get_frame_entity,
220 mips_set_frame_entity,
221 mips_set_frame_offset,
223 NULL, /* get_inverse */
224 NULL, /* get_op_estimated_cost */
225 NULL, /* possible_memory_operand */
226 NULL, /* perform_memory_operand */
229 /**************************************************
232 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
233 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
234 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
235 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
238 **************************************************/
241 * Transforms the standard firm graph into
244 static void mips_prepare_graph(void *self) {
245 mips_code_gen_t *cg = self;
247 /* do local optimizations */
248 optimize_graph_df(cg->irg);
250 /* TODO: we often have dead code reachable through out-edges here. So for
251 * now we rebuild edges (as we need correct user count for code selection)
254 edges_deactivate(cg->irg);
255 edges_activate(cg->irg);
258 // walk the graph and transform firm nodes into mips nodes where possible
259 mips_transform_graph(cg);
260 dump_ir_block_graph_sched(cg->irg, "-transformed");
262 /* do local optimizations (mainly CSE) */
263 optimize_graph_df(cg->irg);
265 /* do code placement, to optimize the position of constants */
268 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
272 * Called immediately before emit phase.
274 static void mips_finish_irg(void *self) {
275 mips_code_gen_t *cg = self;
276 ir_graph *irg = cg->irg;
278 /* create block schedule, this also removes empty blocks which might
279 * produce critical edges */
280 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
282 dump_ir_block_graph_sched(irg, "-mips-finished");
286 static void mips_before_ra(void *self)
291 static void mips_after_ra(void* self)
293 mips_code_gen_t *cg = self;
294 be_coalesce_spillslots(cg->birg);
295 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
299 * Emits the code, closes the output file and frees
300 * the code generator interface.
302 static void mips_emit_and_done(void *self)
304 mips_code_gen_t *cg = self;
305 ir_graph *irg = cg->irg;
308 mips_gen_routine(cg, irg);
312 /* de-allocate code generator */
313 del_set(cg->reg_set);
317 static void *mips_cg_init(be_irg_t *birg);
319 static const arch_code_generator_if_t mips_code_gen_if = {
321 NULL, /* get_pic_base */
322 NULL, /* before abi introduce */
325 mips_before_ra, /* before register allocation hook */
332 * Initializes the code generator.
334 static void *mips_cg_init(be_irg_t *birg)
336 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
337 mips_isa_t *isa = (mips_isa_t *) arch_env;
338 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
340 cg->impl = &mips_code_gen_if;
341 cg->irg = be_get_birg_irg(birg);
342 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
346 cur_reg_set = cg->reg_set;
350 return (arch_code_generator_t *)cg;
354 /*****************************************************************
355 * ____ _ _ _____ _____
356 * | _ \ | | | | |_ _|/ ____| /\
357 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
358 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
359 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
360 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
362 *****************************************************************/
364 static mips_isa_t mips_isa_template = {
367 &mips_gp_regs[REG_SP],
368 &mips_gp_regs[REG_FP],
369 &mips_reg_classes[CLASS_mips_gp],
370 -1, /* stack direction */
371 2, /* power of two stack alignment for calls, 2^2 == 4 */
372 NULL, /* main environment */
374 5, /* reload costs */
380 * Initializes the backend ISA and opens the output file.
382 static arch_env_t *mips_init(FILE *file_handle) {
383 static int inited = 0;
390 isa = XMALLOC(mips_isa_t);
391 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
393 be_emit_init(file_handle);
395 mips_register_init();
396 mips_create_opcodes(&mips_irn_ops);
397 // mips_init_opcode_transforms();
399 /* we mark referenced global entities, so we can only emit those which
400 * are actually referenced. (Note: you mustn't use the type visited flag
401 * elsewhere in the backend)
403 inc_master_type_visited();
405 return &isa->arch_env;
409 * Closes the output file and frees the ISA structure.
411 static void mips_done(void *self)
413 mips_isa_t *isa = self;
415 be_gas_emit_decls(isa->arch_env.main_env, 1);
421 static unsigned mips_get_n_reg_class(const void *self)
427 static const arch_register_class_t *mips_get_reg_class(const void *self,
431 assert(i < N_CLASSES);
432 return &mips_reg_classes[i];
438 * Get the register class which shall be used to store a value of a given mode.
439 * @param self The this pointer.
440 * @param mode The mode in question.
441 * @return A register class which can hold values of the given mode.
443 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
448 ASSERT_NO_FLOAT(mode);
449 return &mips_reg_classes[CLASS_mips_gp];
453 be_abi_call_flags_bits_t flags;
454 const arch_env_t *arch_env;
456 // do special handling to support debuggers
460 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
462 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
463 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
464 env->flags = fl.bits;
466 env->arch_env = arch_env;
471 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
473 mips_abi_env_t *env = self;
474 ir_graph *irg = env->irg;
475 ir_node *block = get_irg_start_block(irg);
476 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
477 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
478 int initialstackframesize;
484 * The calling conventions wants a stack frame of at least 24bytes size with
485 * a0-a3 saved in offset 0-12
486 * fp saved in offset 16
487 * ra saved in offset 20
490 ir_node *sync, *reg, *store;
491 initialstackframesize = 24;
493 // - setup first part of stackframe
494 sp = new_bd_mips_addu(NULL, block, sp,
495 mips_create_Immediate(initialstackframesize));
496 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
497 panic("FIXME Use IncSP or set register requirement with ignore");
499 /* TODO: where to get an edge with a0-a3
501 for(i = 0; i < 4; ++i) {
502 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
503 ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
504 attr = get_mips_attr(store);
505 attr->load_store_mode = mode_Iu;
506 attr->tv = new_tarval_from_long(i * 4, mode_Is);
508 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
512 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
513 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
517 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
518 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
522 /* Note: ideally we would route these mem edges directly towards the
523 * epilogue, but this is currently not supported so we sync all mems
525 sync = new_r_Sync(block, 2, mm+4);
528 ir_node *reg, *store;
529 initialstackframesize = 4;
531 // save old framepointer
532 sp = new_bd_mips_addu(NULL, block, sp,
533 mips_create_Immediate(-initialstackframesize));
534 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
535 panic("FIXME Use IncSP or set register requirement with ignore");
537 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
538 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
543 // setup framepointer
544 fp = new_bd_mips_addu(NULL, block, sp,
545 mips_create_Immediate(-initialstackframesize));
546 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
547 panic("FIXME Use IncSP or set register requirement with ignore");
549 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
550 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
552 return &mips_gp_regs[REG_SP];
555 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
557 mips_abi_env_t *env = self;
559 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
560 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
562 int initial_frame_size = env->debug ? 24 : 4;
563 int fp_save_offset = env->debug ? 16 : 0;
566 sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
567 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
568 panic("FIXME Use be_Copy or set register requirement with ignore");
571 load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
572 fp_save_offset - initial_frame_size);
573 panic("FIXME register requirement with ignore");
575 fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
576 *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
577 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
579 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
580 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
584 * Produces the type which sits between the stack args and the locals on the stack.
585 * it will contain the return address and space to store the old frame pointer.
586 * @return The Firm type modelling the ABI between type.
588 static ir_type *mips_abi_get_between_type(void *self) {
589 mips_abi_env_t *env = self;
591 static ir_type *debug_between_type = NULL;
592 static ir_type *opt_between_type = NULL;
593 static ir_entity *old_fp_ent = NULL;
595 if(env->debug && debug_between_type == NULL) {
596 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
597 ir_entity *ret_addr_ent;
598 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
599 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
600 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
602 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
603 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
604 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
605 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
606 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
607 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
608 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
610 set_entity_offset(a0_ent, 0);
611 set_entity_offset(a1_ent, 4);
612 set_entity_offset(a2_ent, 8);
613 set_entity_offset(a3_ent, 12);
614 set_entity_offset(old_fp_ent, 16);
615 set_entity_offset(ret_addr_ent, 20);
617 set_type_size_bytes(debug_between_type, 24);
618 } else if(!env->debug && opt_between_type == NULL) {
619 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
620 ir_entity *old_fp_ent;
622 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
623 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
624 set_entity_offset(old_fp_ent, 0);
625 set_type_size_bytes(opt_between_type, 4);
628 return env->debug ? debug_between_type : opt_between_type;
631 static const be_abi_callbacks_t mips_abi_callbacks = {
634 mips_abi_get_between_type,
640 * Get the ABI restrictions for procedure calls.
641 * @param self The this pointer.
642 * @param method_type The type of the method (procedure) in question.
643 * @param abi The abi object to be modified
645 static void mips_get_call_abi(const void *self, ir_type *method_type,
650 int n = get_method_n_params(method_type);
654 const arch_register_t *reg;
655 be_abi_call_flags_t call_flags;
658 memset(&call_flags, 0, sizeof(call_flags));
659 call_flags.bits.left_to_right = 0;
660 call_flags.bits.store_args_sequential = 0;
661 call_flags.bits.try_omit_fp = 1;
662 call_flags.bits.fp_free = 0;
663 call_flags.bits.call_has_imm = 1;
665 /* set stack parameter passing style */
666 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
668 /* collect the mode for each type */
669 modes = ALLOCAN(ir_mode*, n);
670 for (i = 0; i < n; i++) {
671 tp = get_method_param_type(method_type, i);
672 modes[i] = get_type_mode(tp);
675 // assigns parameters to registers or stack
676 for (i = 0; i < n; i++) {
677 // first 4 params in $a0-$a3, the others on the stack
679 reg = &mips_gp_regs[REG_A0 + i];
680 be_abi_call_param_reg(abi, i, reg);
682 /* default: all parameters on stack */
683 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
687 /* set return register */
688 /* default: return value is in R0 (and maybe R1) */
689 result_count = get_method_n_ress(method_type);
690 assert(result_count <= 2 && "More than 2 result values not supported");
691 for(i = 0; i < result_count; ++i) {
692 const arch_register_t* reg;
693 tp = get_method_res_type(method_type, i);
694 mode = get_type_mode(tp);
695 ASSERT_NO_FLOAT(mode);
697 reg = &mips_gp_regs[REG_V0 + i];
698 be_abi_call_res_reg(abi, i, reg);
703 * Initializes the code generator interface.
705 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
708 return &mips_code_gen_if;
712 * Returns the necessary byte alignment for storing a register of given class.
714 static int mips_get_reg_class_alignment(const void *self,
715 const arch_register_class_t *cls)
717 ir_mode *mode = arch_register_class_mode(cls);
719 return get_mode_size_bytes(mode);
722 static const be_execution_unit_t ***mips_get_allowed_execution_units(
723 const void *self, const ir_node *irn)
728 panic("Unimplemented mips_get_allowed_execution_units()");
731 static const be_machine_t *mips_get_machine(const void *self)
735 panic("Unimplemented mips_get_machine()");
739 * Return irp irgs in the desired order.
741 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
749 * Returns the libFirm configuration parameter for this backend.
751 static const backend_params *mips_get_libfirm_params(void) {
752 static backend_params p = {
753 1, /* need dword lowering */
754 0, /* don't support inline assembler yet */
755 NULL, /* will be set later */
756 NULL, /* but yet no creator function */
757 NULL, /* context for create_intrinsic_fkt */
758 NULL, /* no if conversion settings */
759 NULL, /* float arithmetic mode (TODO) */
760 0, /* no trampoline support: size 0 */
761 0, /* no trampoline support: align 0 */
762 NULL, /* no trampoline support: no trampoline builder */
763 4 /* alignment of stack parameter */
769 static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
774 return ASM_CONSTRAINT_FLAG_INVALID;
777 static int mips_is_valid_clobber(const void *self, const char *clobber)
784 const arch_isa_if_t mips_isa_if = {
787 NULL, /* handle intrinsics */
788 mips_get_n_reg_class,
790 mips_get_reg_class_for_mode,
792 mips_get_code_generator_if,
793 mips_get_list_sched_selector,
794 mips_get_ilp_sched_selector,
795 mips_get_reg_class_alignment,
796 mips_get_libfirm_params,
797 mips_get_allowed_execution_units,
800 NULL, /* mark remat */
801 mips_parse_asm_constraint,
802 mips_is_valid_clobber
805 void be_init_arch_mips(void)
807 be_register_isa_if("mips", &mips_isa_if);
810 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);