2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch_t.h"
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a mips node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
91 arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X || mode == mode_M) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
105 /* in case of a proj, we need to get the correct OUT slot */
106 /* of the node corresponding to the proj number */
108 node_pos = mips_translate_proj_pos(node);
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_mips_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_mips_in_req(node, pos);
123 req = get_mips_out_req(node, node_pos);
129 /* unknown should be translated by now */
130 assert(!is_Unknown(node));
132 return arch_no_register_req;
135 static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg)
141 if (get_irn_mode(irn) == mode_X) {
145 pos = mips_translate_proj_pos(irn);
146 irn = skip_Proj(irn);
149 if (is_mips_irn(irn)) {
150 const arch_register_t **slots;
152 slots = get_mips_slots(irn);
155 /* here we set the registers for the Phi nodes */
156 mips_set_firm_reg(irn, reg, cur_reg_set);
160 static arch_irn_class_t mips_classify(const ir_node *irn)
162 irn = skip_Proj_const(irn);
165 return arch_irn_class_branch;
171 int mips_is_Load(const ir_node *node)
173 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
174 is_mips_lb(node) || is_mips_lbu(node);
177 int mips_is_Store(const ir_node *node)
179 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
182 static ir_entity *mips_get_frame_entity(const ir_node *node)
184 const mips_load_store_attr_t *attr;
186 if(!is_mips_irn(node))
188 if(!mips_is_Load(node) && !mips_is_Store(node))
191 attr = get_mips_load_store_attr_const(node);
192 return attr->stack_entity;
195 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
197 mips_load_store_attr_t *attr;
199 if(!is_mips_irn(node)) {
200 panic("trying to set frame entity on non load/store node %+F", node);
202 if(!mips_is_Load(node) && !mips_is_Store(node)) {
203 panic("trying to set frame entity on non load/store node %+F", node);
206 attr = get_irn_generic_attr(node);
207 attr->stack_entity = entity;
211 * This function is called by the generic backend to correct offsets for
212 * nodes accessing the stack.
214 static void mips_set_frame_offset(ir_node *node, int offset)
216 mips_load_store_attr_t *attr;
218 if(!is_mips_irn(node)) {
219 panic("trying to set frame offset on non load/store node %+F", node);
221 if(!mips_is_Load(node) && !mips_is_Store(node)) {
222 panic("trying to set frame offset on non load/store node %+F", node);
225 attr = get_irn_generic_attr(node);
226 attr->offset += offset;
228 if(attr->offset < -32768 || attr->offset > 32767) {
229 panic("Out of stack space! (mips supports only 16bit offsets)");
233 static int mips_get_sp_bias(const ir_node *irn)
239 /* fill register allocator interface */
241 static const arch_irn_ops_t mips_irn_ops = {
242 mips_get_irn_reg_req,
244 mips_get_frame_entity,
245 mips_set_frame_entity,
246 mips_set_frame_offset,
248 NULL, /* get_inverse */
249 NULL, /* get_op_estimated_cost */
250 NULL, /* possible_memory_operand */
251 NULL, /* perform_memory_operand */
254 /**************************************************
257 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
258 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
259 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
260 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
263 **************************************************/
266 * Transforms the standard firm graph into
269 static void mips_prepare_graph(void *self) {
270 mips_code_gen_t *cg = self;
272 /* do local optimizations */
273 optimize_graph_df(cg->irg);
275 /* TODO: we often have dead code reachable through out-edges here. So for
276 * now we rebuild edges (as we need correct user count for code selection)
279 edges_deactivate(cg->irg);
280 edges_activate(cg->irg);
283 // walk the graph and transform firm nodes into mips nodes where possible
284 mips_transform_graph(cg);
285 dump_ir_block_graph_sched(cg->irg, "-transformed");
287 /* do local optimizations (mainly CSE) */
288 optimize_graph_df(cg->irg);
290 /* do code placement, to optimize the position of constants */
293 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
297 * Called immediately before emit phase.
299 static void mips_finish_irg(void *self) {
300 mips_code_gen_t *cg = self;
301 ir_graph *irg = cg->irg;
303 /* create block schedule, this also removes empty blocks which might
304 * produce critical edges */
305 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
307 dump_ir_block_graph_sched(irg, "-mips-finished");
311 static void mips_before_ra(void *self)
316 static void mips_after_ra(void* self)
318 mips_code_gen_t *cg = self;
319 be_coalesce_spillslots(cg->birg);
320 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
324 * Emits the code, closes the output file and frees
325 * the code generator interface.
327 static void mips_emit_and_done(void *self)
329 mips_code_gen_t *cg = self;
330 ir_graph *irg = cg->irg;
333 mips_gen_routine(cg, irg);
337 /* de-allocate code generator */
338 del_set(cg->reg_set);
342 static void *mips_cg_init(be_irg_t *birg);
344 static const arch_code_generator_if_t mips_code_gen_if = {
346 NULL, /* get_pic_base */
347 NULL, /* before abi introduce */
350 mips_before_ra, /* before register allocation hook */
357 * Initializes the code generator.
359 static void *mips_cg_init(be_irg_t *birg)
361 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
362 mips_isa_t *isa = (mips_isa_t *) arch_env;
363 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
365 cg->impl = &mips_code_gen_if;
366 cg->irg = be_get_birg_irg(birg);
367 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
371 cur_reg_set = cg->reg_set;
375 return (arch_code_generator_t *)cg;
379 /*****************************************************************
380 * ____ _ _ _____ _____
381 * | _ \ | | | | |_ _|/ ____| /\
382 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
383 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
384 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
385 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
387 *****************************************************************/
389 static mips_isa_t mips_isa_template = {
392 &mips_gp_regs[REG_SP],
393 &mips_gp_regs[REG_FP],
394 -1, /* stack direction */
395 2, /* power of two stack alignment for calls, 2^2 == 4 */
396 NULL, /* main environment */
398 5, /* reload costs */
404 * Initializes the backend ISA and opens the output file.
406 static arch_env_t *mips_init(FILE *file_handle) {
407 static int inited = 0;
414 isa = XMALLOC(mips_isa_t);
415 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
417 be_emit_init(file_handle);
419 mips_register_init();
420 mips_create_opcodes(&mips_irn_ops);
421 // mips_init_opcode_transforms();
423 /* we mark referenced global entities, so we can only emit those which
424 * are actually referenced. (Note: you mustn't use the type visited flag
425 * elsewhere in the backend)
427 inc_master_type_visited();
429 return &isa->arch_env;
433 * Closes the output file and frees the ISA structure.
435 static void mips_done(void *self)
437 mips_isa_t *isa = self;
439 be_gas_emit_decls(isa->arch_env.main_env, 1);
445 static unsigned mips_get_n_reg_class(const void *self)
451 static const arch_register_class_t *mips_get_reg_class(const void *self,
455 assert(i < N_CLASSES);
456 return &mips_reg_classes[i];
462 * Get the register class which shall be used to store a value of a given mode.
463 * @param self The this pointer.
464 * @param mode The mode in question.
465 * @return A register class which can hold values of the given mode.
467 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
472 ASSERT_NO_FLOAT(mode);
473 return &mips_reg_classes[CLASS_mips_gp];
477 be_abi_call_flags_bits_t flags;
478 const arch_env_t *arch_env;
480 // do special handling to support debuggers
484 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
486 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
487 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
488 env->flags = fl.bits;
490 env->arch_env = arch_env;
495 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
497 mips_abi_env_t *env = self;
498 ir_graph *irg = env->irg;
499 ir_node *block = get_irg_start_block(irg);
500 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
501 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
502 int initialstackframesize;
508 * The calling conventions wants a stack frame of at least 24bytes size with
509 * a0-a3 saved in offset 0-12
510 * fp saved in offset 16
511 * ra saved in offset 20
514 ir_node *sync, *reg, *store;
515 initialstackframesize = 24;
517 // - setup first part of stackframe
518 sp = new_bd_mips_addu(NULL, block, sp,
519 mips_create_Immediate(initialstackframesize));
520 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
521 panic("FIXME Use IncSP or set register requirement with ignore");
523 /* TODO: where to get an edge with a0-a3
525 for(i = 0; i < 4; ++i) {
526 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
527 ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
528 attr = get_mips_attr(store);
529 attr->load_store_mode = mode_Iu;
530 attr->tv = new_tarval_from_long(i * 4, mode_Is);
532 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
536 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
537 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
541 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
542 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
546 /* Note: ideally we would route these mem edges directly towards the
547 * epilogue, but this is currently not supported so we sync all mems
549 sync = new_r_Sync(irg, block, 2, mm+4);
552 ir_node *reg, *store;
553 initialstackframesize = 4;
555 // save old framepointer
556 sp = new_bd_mips_addu(NULL, block, sp,
557 mips_create_Immediate(-initialstackframesize));
558 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
559 panic("FIXME Use IncSP or set register requirement with ignore");
561 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
562 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
567 // setup framepointer
568 fp = new_bd_mips_addu(NULL, block, sp,
569 mips_create_Immediate(-initialstackframesize));
570 mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]);
571 panic("FIXME Use IncSP or set register requirement with ignore");
573 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
574 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
576 return &mips_gp_regs[REG_SP];
579 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
581 mips_abi_env_t *env = self;
583 ir_graph *irg = env->irg;
584 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
585 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
587 int initial_frame_size = env->debug ? 24 : 4;
588 int fp_save_offset = env->debug ? 16 : 0;
591 sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
592 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
593 panic("FIXME Use be_Copy or set register requirement with ignore");
596 load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
597 fp_save_offset - initial_frame_size);
598 panic("FIXME register requirement with ignore");
600 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
601 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
602 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
604 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
605 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
609 * Produces the type which sits between the stack args and the locals on the stack.
610 * it will contain the return address and space to store the old frame pointer.
611 * @return The Firm type modelling the ABI between type.
613 static ir_type *mips_abi_get_between_type(void *self) {
614 mips_abi_env_t *env = self;
616 static ir_type *debug_between_type = NULL;
617 static ir_type *opt_between_type = NULL;
618 static ir_entity *old_fp_ent = NULL;
620 if(env->debug && debug_between_type == NULL) {
621 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
622 ir_entity *ret_addr_ent;
623 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
624 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
625 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
627 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
628 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
629 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
630 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
631 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
632 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
633 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
635 set_entity_offset(a0_ent, 0);
636 set_entity_offset(a1_ent, 4);
637 set_entity_offset(a2_ent, 8);
638 set_entity_offset(a3_ent, 12);
639 set_entity_offset(old_fp_ent, 16);
640 set_entity_offset(ret_addr_ent, 20);
642 set_type_size_bytes(debug_between_type, 24);
643 } else if(!env->debug && opt_between_type == NULL) {
644 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
645 ir_entity *old_fp_ent;
647 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
648 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
649 set_entity_offset(old_fp_ent, 0);
650 set_type_size_bytes(opt_between_type, 4);
653 return env->debug ? debug_between_type : opt_between_type;
656 static const be_abi_callbacks_t mips_abi_callbacks = {
659 mips_abi_get_between_type,
665 * Get the ABI restrictions for procedure calls.
666 * @param self The this pointer.
667 * @param method_type The type of the method (procedure) in question.
668 * @param abi The abi object to be modified
670 static void mips_get_call_abi(const void *self, ir_type *method_type,
675 int n = get_method_n_params(method_type);
679 const arch_register_t *reg;
680 be_abi_call_flags_t call_flags;
683 memset(&call_flags, 0, sizeof(call_flags));
684 call_flags.bits.left_to_right = 0;
685 call_flags.bits.store_args_sequential = 0;
686 call_flags.bits.try_omit_fp = 1;
687 call_flags.bits.fp_free = 0;
688 call_flags.bits.call_has_imm = 1;
690 /* set stack parameter passing style */
691 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
693 /* collect the mode for each type */
694 modes = ALLOCAN(ir_mode*, n);
695 for (i = 0; i < n; i++) {
696 tp = get_method_param_type(method_type, i);
697 modes[i] = get_type_mode(tp);
700 // assigns parameters to registers or stack
701 for (i = 0; i < n; i++) {
702 // first 4 params in $a0-$a3, the others on the stack
704 reg = &mips_gp_regs[REG_A0 + i];
705 be_abi_call_param_reg(abi, i, reg);
707 /* default: all parameters on stack */
708 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
712 /* set return register */
713 /* default: return value is in R0 (and maybe R1) */
714 result_count = get_method_n_ress(method_type);
715 assert(result_count <= 2 && "More than 2 result values not supported");
716 for(i = 0; i < result_count; ++i) {
717 const arch_register_t* reg;
718 tp = get_method_res_type(method_type, i);
719 mode = get_type_mode(tp);
720 ASSERT_NO_FLOAT(mode);
722 reg = &mips_gp_regs[REG_V0 + i];
723 be_abi_call_res_reg(abi, i, reg);
728 * Initializes the code generator interface.
730 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
733 return &mips_code_gen_if;
737 * Returns the necessary byte alignment for storing a register of given class.
739 static int mips_get_reg_class_alignment(const void *self,
740 const arch_register_class_t *cls)
742 ir_mode *mode = arch_register_class_mode(cls);
744 return get_mode_size_bytes(mode);
747 static const be_execution_unit_t ***mips_get_allowed_execution_units(
748 const void *self, const ir_node *irn)
753 panic("Unimplemented mips_get_allowed_execution_units()");
756 static const be_machine_t *mips_get_machine(const void *self)
760 panic("Unimplemented mips_get_machine()");
764 * Return irp irgs in the desired order.
766 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
774 * Returns the libFirm configuration parameter for this backend.
776 static const backend_params *mips_get_libfirm_params(void) {
777 static backend_params p = {
778 1, /* need dword lowering */
779 0, /* don't support inline assembler yet */
780 0, /* no immediate floating point mode. */
781 NULL, /* will be set later */
782 NULL, /* but yet no creator function */
783 NULL, /* context for create_intrinsic_fkt */
784 NULL, /* no if conversion settings */
785 NULL /* no immediate fp mode */
791 static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
796 return ASM_CONSTRAINT_FLAG_INVALID;
799 static int mips_is_valid_clobber(const void *self, const char *clobber)
806 const arch_isa_if_t mips_isa_if = {
809 NULL, /* handle intrinsics */
810 mips_get_n_reg_class,
812 mips_get_reg_class_for_mode,
814 mips_get_code_generator_if,
815 mips_get_list_sched_selector,
816 mips_get_ilp_sched_selector,
817 mips_get_reg_class_alignment,
818 mips_get_libfirm_params,
819 mips_get_allowed_execution_units,
822 NULL, /* mark remat */
823 mips_parse_asm_constraint,
824 mips_is_valid_clobber
827 void be_init_arch_mips(void)
829 be_register_isa_if("mips", &mips_isa_if);
832 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);