1 /* The main mips backend driver file. */
8 #include "pseudo_irg.h"
23 #include "../bearch.h" /* the general register allocator interface */
24 #include "../benode_t.h"
25 #include "../belower.h"
26 #include "../besched_t.h"
29 #include "../bemachine.h"
30 #include "../bemodule.h"
32 #include "bearch_mips_t.h"
34 #include "mips_new_nodes.h" /* mips nodes interface */
35 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
36 #include "mips_gen_decls.h" /* interface declaration emitter */
37 #include "mips_transform.h"
38 #include "mips_emitter.h"
39 #include "mips_map_regs.h"
40 #include "mips_util.h"
41 #include "mips_scheduler.h"
43 #define DEBUG_MODULE "firm.be.mips.isa"
45 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
46 static set *cur_reg_set = NULL;
48 /**************************************************
51 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
52 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
53 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
54 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
57 **************************************************/
59 static ir_node *my_skip_proj(const ir_node *n) {
66 * Return register requirements for a mips node.
67 * If the node returns a tuple (mode_T) then the proj's
68 * will be asked for this information.
70 static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
71 const mips_register_req_t *irn_req;
72 long node_pos = pos == -1 ? 0 : pos;
73 ir_mode *mode = get_irn_mode(irn);
74 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
76 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
77 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
81 if (mode == mode_T && pos < 0) {
82 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
86 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
89 /* in case of a proj, we need to get the correct OUT slot */
90 /* of the node corresponding to the proj number */
92 node_pos = mips_translate_proj_pos(irn);
98 irn = my_skip_proj(irn);
100 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
103 /* get requirements for our own nodes */
104 if (is_mips_irn(irn)) {
106 irn_req = get_mips_in_req(irn, pos);
109 irn_req = get_mips_out_req(irn, node_pos);
112 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
114 memcpy(req, &(irn_req->req), sizeof(*req));
116 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
117 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
118 req->other_same = get_irn_n(irn, irn_req->same_pos);
121 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
122 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
123 req->other_different = get_irn_n(irn, irn_req->different_pos);
126 /* get requirements for FIRM nodes */
128 /* treat Phi like Const with default requirements */
130 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
132 if (mode_is_float(mode)) {
133 //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req));
134 assert(0 && "floating point not supported (yet)");
136 else if (mode_is_int(mode) || mode_is_reference(mode)) {
137 memcpy(req, &(mips_default_req_mips_gp.req), sizeof(*req));
139 else if (mode == mode_T || mode == mode_M) {
140 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
144 assert(0 && "unsupported Phi-Mode");
148 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
156 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
161 if (get_irn_mode(irn) == mode_X) {
165 pos = mips_translate_proj_pos(irn);
166 irn = my_skip_proj(irn);
169 if (is_mips_irn(irn)) {
170 const arch_register_t **slots;
172 slots = get_mips_slots(irn);
176 /* here we set the registers for the Phi nodes */
177 mips_set_firm_reg(irn, reg, cur_reg_set);
181 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
183 const arch_register_t *reg = NULL;
187 if (get_irn_mode(irn) == mode_X) {
191 pos = mips_translate_proj_pos(irn);
192 irn = my_skip_proj(irn);
195 if (is_mips_irn(irn)) {
196 const arch_register_t **slots;
197 slots = get_mips_slots(irn);
201 reg = mips_get_firm_reg(irn, cur_reg_set);
207 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
208 irn = my_skip_proj(irn);
211 return arch_irn_class_branch;
212 } else if (is_mips_irn(irn)) {
213 return arch_irn_class_normal;
219 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
220 irn = my_skip_proj(irn);
222 if (is_mips_irn(irn)) {
223 return get_mips_flags(irn);
225 else if (is_Unknown(irn)) {
226 return arch_irn_flags_ignore;
232 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
233 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
234 mips_attr_t *attr = get_mips_attr(irn);
236 return attr->stack_entity;
242 static void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
243 mips_attr_t *attr = get_mips_attr(irn);
244 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
245 attr->stack_entity = ent;
249 * This function is called by the generic backend to correct offsets for
250 * nodes accessing the stack.
252 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
253 mips_attr_t *attr = get_mips_attr(irn);
254 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
256 attr->stack_entity_offset = offset;
259 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
263 /* fill register allocator interface */
265 static const arch_irn_ops_if_t mips_irn_ops_if = {
266 mips_get_irn_reg_req,
271 mips_get_frame_entity,
272 mips_set_frame_entity,
273 mips_set_frame_offset,
275 NULL, /* get_inverse */
276 NULL, /* get_op_estimated_cost */
277 NULL, /* possible_memory_operand */
278 NULL, /* perform_memory_operand */
281 mips_irn_ops_t mips_irn_ops = {
288 /**************************************************
291 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
292 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
293 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
294 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
297 **************************************************/
307 * Ext-Block walker: create a block schedule
309 static void create_block_list(ir_extblk *blk, void *env) {
313 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
314 ir_node *block = get_extbb_block(blk, i);
316 set_irn_link(block, NULL);
318 set_irn_link(list->end, block);
327 /* return the scheduled block at position pos */
328 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
329 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
330 return cg->bl_list[pos];
334 /* return the number of scheduled blocks */
335 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
336 return ARR_LEN(cg->bl_list);
339 /* set a block schedule number */
340 void mips_set_block_sched_nr(ir_node *block, int nr) {
341 set_irn_link(block, INT_TO_PTR(nr));
344 /* get a block schedule number */
345 int mips_get_block_sched_nr(ir_node *block) {
346 return PTR_TO_INT(get_irn_link(block));
350 * Creates a block schedule for the given graph.
352 static void mips_create_block_sched(mips_code_gen_t *cg) {
354 ir_node **bl_list, *block;
358 DEL_ARR_F(cg->bl_list);
359 free_survive_dce(cg->bl_list_sdce);
362 /* calculate the block schedule here */
363 compute_extbb(cg->irg);
368 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
371 bl_list = NEW_ARR_F(ir_node *, list.cnt);
372 cg->bl_list_sdce = new_survive_dce();
373 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
375 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
379 cg->bl_list = bl_list;
382 typedef struct _wenv_t {
387 * Walker: link all CopyB nodes
389 static void collect_copyb_nodes(ir_node *node, void *env) {
392 if (get_irn_op(node) == op_CopyB) {
393 set_irn_link(node, wenv->list);
398 static void replace_copyb_nodes(mips_code_gen_t *cg) {
400 ir_node *copy, *next;
401 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
402 const ir_edge_t *edge;
404 /* build code for all copyB */
406 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
408 for (copy = env.list; copy; copy = next) {
409 next = get_irn_link(copy);
411 old_bl = get_nodes_block(copy);
413 jmp = get_Block_cfgpred(old_bl, 0);
414 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
416 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
417 set_nodes_block(jmp, new_bl);
419 mem = gen_code_for_CopyB(new_bl, copy);
421 /* fix copyB's out edges */
422 foreach_out_edge(copy, edge) {
423 ir_node *succ = get_edge_src_irn(edge);
425 assert(is_Proj(succ));
426 switch (get_Proj_proj(succ)) {
427 case pn_CopyB_M_regular:
428 case pn_CopyB_M_except:
432 exchange(succ, get_irg_bad(cg->irg));
439 * Transforms the standard firm graph into
442 static void mips_prepare_graph(void *self) {
443 mips_code_gen_t *cg = self;
446 // replace all copyb nodes in the block with a loop
447 // and mips store/load nodes
448 replace_copyb_nodes(cg);
450 // Calculate block schedule
451 mips_create_block_sched(cg);
453 /* enter the block number into every blocks link field */
454 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
455 ir_node *bl = mips_get_sched_block(cg, bl_nr);
456 mips_set_block_sched_nr(bl, bl_nr);
459 // walk the graph and transform firm nodes into mips nodes where possible
460 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
462 dump_ir_block_graph_sched(cg->irg, "-transformed");
466 * Called immediately before emit phase.
468 static void mips_finish_irg(void *self) {
469 mips_code_gen_t *cg = self;
470 ir_graph *irg = cg->irg;
472 dump_ir_block_graph_sched(irg, "-mips-finished");
477 * These are some hooks which must be filled but are probably not needed.
479 static void mips_before_sched(void *self) {
480 /* Some stuff you need to do after scheduling but before register allocation */
483 static void mips_before_ra(void *self) {
484 /* Some stuff you need to do immediately after register allocation */
487 static void mips_after_ra(void* self) {
488 mips_code_gen_t *cg = self;
489 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
493 * Emits the code, closes the output file and frees
494 * the code generator interface.
496 static void mips_emit_and_done(void *self) {
497 mips_code_gen_t *cg = self;
498 ir_graph *irg = cg->irg;
499 FILE *out = cg->isa->out;
501 mips_register_emitters();
503 if (cg->emit_decls) {
508 mips_gen_routine(out, irg, cg);
512 /* de-allocate code generator */
513 del_set(cg->reg_set);
515 DEL_ARR_F(cg->bl_list);
516 free_survive_dce(cg->bl_list_sdce);
521 static void *mips_cg_init(be_irg_t *birg);
523 static const arch_code_generator_if_t mips_code_gen_if = {
525 NULL, /* before abi introduce */
528 mips_before_sched, /* before scheduling hook */
529 mips_before_ra, /* before register allocation hook */
536 * Initializes the code generator.
538 static void *mips_cg_init(be_irg_t *birg) {
539 mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
540 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
542 cg->impl = &mips_code_gen_if;
544 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
545 cg->arch_env = birg->main_env->arch_env;
549 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
553 if (isa->num_codegens > 1)
558 cur_reg_set = cg->reg_set;
560 mips_irn_ops.cg = cg;
562 return (arch_code_generator_t *)cg;
566 /*****************************************************************
567 * ____ _ _ _____ _____
568 * | _ \ | | | | |_ _|/ ____| /\
569 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
570 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
571 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
572 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
574 *****************************************************************/
576 static mips_isa_t mips_isa_template = {
578 &mips_gp_regs[REG_SP],
579 &mips_gp_regs[REG_FP],
580 -1, // stack direction
581 0, // num codegens?!? TODO what is this?
586 * Initializes the backend ISA and opens the output file.
588 static void *mips_init(FILE *file_handle) {
589 static int inited = 0;
595 isa = xcalloc(1, sizeof(*isa));
596 memcpy(isa, &mips_isa_template, sizeof(*isa));
598 isa->out = file_handle;
600 mips_register_init(isa);
601 mips_create_opcodes();
602 mips_init_opcode_transforms();
610 * Closes the output file and frees the ISA structure.
612 static void mips_done(void *self) {
616 static int mips_get_n_reg_class(const void *self) {
620 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
621 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
622 return &mips_reg_classes[i];
628 * Get the register class which shall be used to store a value of a given mode.
629 * @param self The this pointer.
630 * @param mode The mode in question.
631 * @return A register class which can hold values of the given mode.
633 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
634 ASSERT_NO_FLOAT(mode);
635 return &mips_reg_classes[CLASS_mips_gp];
639 be_abi_call_flags_bits_t flags;
640 const mips_isa_t *isa;
641 const arch_env_t *arch_env;
643 // do special handling to support debuggers
647 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
649 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
650 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
651 env->flags = fl.bits;
653 env->arch_env = arch_env;
654 env->isa = (const mips_isa_t*) arch_env->isa;
659 static void mips_abi_dont_save_regs(void *self, pset *s)
661 mips_abi_env_t *env = self;
662 if(env->flags.try_omit_fp)
663 pset_insert_ptr(s, env->isa->fp);
666 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
668 mips_abi_env_t *env = self;
669 ir_graph *irg = env->irg;
670 dbg_info *dbg = NULL; // TODO where can I get this from?
671 ir_node *block = get_irg_start_block(env->irg);
673 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
674 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
675 int initialstackframesize;
679 * The calling conventions wants a stack frame of at least 24bytes size with
680 * a0-a3 saved in offset 0-12
681 * fp saved in offset 16
682 * ra saved in offset 20
685 ir_node *sync, *reg, *store;
686 initialstackframesize = 24;
688 // - setup first part of stackframe
689 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
690 attr = get_mips_attr(sp);
691 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
692 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
693 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
695 /* TODO: where to get an edge with a0-a3
697 for(i = 0; i < 4; ++i) {
698 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
699 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
700 attr = get_mips_attr(store);
701 attr->load_store_mode = mode_Iu;
702 attr->tv = new_tarval_from_long(i * 4, mode_Is);
704 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
708 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
709 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
710 attr = get_mips_attr(store);
711 attr->modes.load_store_mode = mode_Iu;
712 attr->tv = new_tarval_from_long(16, mode_Is);
714 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
716 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
717 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
718 attr = get_mips_attr(store);
719 attr->modes.load_store_mode = mode_Iu;
720 attr->tv = new_tarval_from_long(20, mode_Is);
722 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
724 // TODO ideally we would route these mem edges directly towards the epilogue
725 sync = new_r_Sync(irg, block, 2, mm+4);
728 ir_node *reg, *store;
729 initialstackframesize = 4;
731 // save old framepointer
732 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
733 attr = get_mips_attr(sp);
734 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
735 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
736 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
738 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
739 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
740 attr = get_mips_attr(store);
741 attr->modes.load_store_mode = mode_Iu;
742 attr->tv = new_tarval_from_long(0, mode_Is);
744 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
747 // setup framepointer
748 fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
749 attr = get_mips_attr(fp);
750 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
751 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
752 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
754 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
755 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
757 return &mips_gp_regs[REG_SP];
760 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
762 mips_abi_env_t *env = self;
763 ir_graph *irg = env->irg;
764 dbg_info *dbg = NULL; // TODO where can I get this from?
766 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
767 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
769 int initial_frame_size = env->debug ? 24 : 4;
770 int fp_save_offset = env->debug ? 16 : 0;
773 sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
774 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
775 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
778 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
779 attr = get_mips_attr(load);
780 attr->modes.load_store_mode = mode_Iu;
781 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
782 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
784 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
785 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
786 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
788 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
789 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
793 * Produces the type which sits between the stack args and the locals on the stack.
794 * it will contain the return address and space to store the old frame pointer.
795 * @return The Firm type modelling the ABI between type.
797 static ir_type *mips_abi_get_between_type(void *self) {
798 mips_abi_env_t *env = self;
800 static ir_type *debug_between_type = NULL;
801 static ir_type *opt_between_type = NULL;
802 static ir_entity *old_fp_ent = NULL;
804 if(env->debug && debug_between_type == NULL) {
805 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
806 ir_entity *ret_addr_ent;
807 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
808 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
809 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
811 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
812 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
813 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
814 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
815 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
816 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
817 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
819 set_entity_offset(a0_ent, 0);
820 set_entity_offset(a1_ent, 4);
821 set_entity_offset(a2_ent, 8);
822 set_entity_offset(a3_ent, 12);
823 set_entity_offset(old_fp_ent, 16);
824 set_entity_offset(ret_addr_ent, 20);
826 set_type_size_bytes(debug_between_type, 24);
827 } else if(!env->debug && opt_between_type == NULL) {
828 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
829 ir_entity *old_fp_ent;
831 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
832 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
833 set_entity_offset(old_fp_ent, 0);
834 set_type_size_bytes(opt_between_type, 4);
837 return env->debug ? debug_between_type : opt_between_type;
840 static const be_abi_callbacks_t mips_abi_callbacks = {
843 mips_abi_get_between_type,
844 mips_abi_dont_save_regs,
850 * Get the ABI restrictions for procedure calls.
851 * @param self The this pointer.
852 * @param method_type The type of the method (procedure) in question.
853 * @param abi The abi object to be modified
855 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
858 int n = get_method_n_params(method_type);
862 const arch_register_t *reg;
863 be_abi_call_flags_t call_flags;
865 memset(&call_flags, 0, sizeof(call_flags));
866 call_flags.bits.left_to_right = 0;
867 call_flags.bits.store_args_sequential = 0;
868 call_flags.bits.try_omit_fp = 1;
869 call_flags.bits.fp_free = 0;
870 call_flags.bits.call_has_imm = 1;
872 /* set stack parameter passing style */
873 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
875 /* collect the mode for each type */
876 modes = alloca(n * sizeof(modes[0]));
877 for (i = 0; i < n; i++) {
878 tp = get_method_param_type(method_type, i);
879 modes[i] = get_type_mode(tp);
882 // assigns parameters to registers or stack
883 for (i = 0; i < n; i++) {
884 // first 4 params in $a0-$a3, the others on the stack
886 reg = &mips_gp_regs[REG_A0 + i];
887 be_abi_call_param_reg(abi, i, reg);
889 /* default: all parameters on stack */
890 be_abi_call_param_stack(abi, i, 4, 0, 0);
894 /* set return register */
895 /* default: return value is in R0 (and maybe R1) */
896 result_count = get_method_n_ress(method_type);
897 assert(result_count <= 2 && "More than 2 result values not supported");
898 for(i = 0; i < result_count; ++i) {
899 const arch_register_t* reg;
900 tp = get_method_res_type(method_type, i);
901 mode = get_type_mode(tp);
902 ASSERT_NO_FLOAT(mode);
904 reg = &mips_gp_regs[REG_V0 + i];
905 be_abi_call_res_reg(abi, i, reg);
909 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
910 return &mips_irn_ops;
913 const arch_irn_handler_t mips_irn_handler = {
917 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
918 return &mips_irn_handler;
922 * Initializes the code generator interface.
924 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
925 return &mips_code_gen_if;
929 * Returns the necessary byte alignment for storing a register of given class.
931 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
932 ir_mode *mode = arch_register_class_mode(cls);
933 return get_mode_size_bytes(mode);
936 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
942 static const be_machine_t *mips_get_machine(const void *self) {
949 * Returns the libFirm configuration parameter for this backend.
951 static const backend_params *mips_get_libfirm_params(void) {
952 static arch_dep_params_t ad = {
954 0, /* Muls are fast enough on Mips */
955 31, /* shift would be ok */
958 32, /* Mulhs & Mulhu available for 32 bit */
960 static backend_params p = {
961 NULL, /* no additional opcodes */
962 NULL, /* will be set later */
963 1, /* need dword lowering */
964 NULL, /* but yet no creator function */
965 NULL, /* context for create_intrinsic_fkt */
973 void be_init_arch_mips(void)
976 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);
977 #endif /* WITH_LIBCORE */
979 const arch_isa_if_t mips_isa_if = {
982 mips_get_n_reg_class,
984 mips_get_reg_class_for_mode,
986 mips_get_irn_handler,
987 mips_get_code_generator_if,
988 mips_get_list_sched_selector,
989 mips_get_ilp_sched_selector,
990 mips_get_reg_class_alignment,
991 mips_get_libfirm_params,
992 mips_get_allowed_execution_units,