2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
47 #include "../bearch_t.h"
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a mips node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
91 arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X || mode == mode_M) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
105 /* in case of a proj, we need to get the correct OUT slot */
106 /* of the node corresponding to the proj number */
108 node_pos = mips_translate_proj_pos(node);
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_mips_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_mips_in_req(node, pos);
123 req = get_mips_out_req(node, node_pos);
129 /* unknown should be translated by now */
130 assert(!is_Unknown(node));
132 return arch_no_register_req;
135 static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg)
141 if (get_irn_mode(irn) == mode_X) {
145 pos = mips_translate_proj_pos(irn);
146 irn = skip_Proj(irn);
149 if (is_mips_irn(irn)) {
150 const arch_register_t **slots;
152 slots = get_mips_slots(irn);
155 /* here we set the registers for the Phi nodes */
156 mips_set_firm_reg(irn, reg, cur_reg_set);
160 static const arch_register_t *mips_get_irn_reg(const ir_node *irn)
163 const arch_register_t *reg = NULL;
167 if (get_irn_mode(irn) == mode_X) {
171 pos = mips_translate_proj_pos(irn);
172 irn = skip_Proj_const(irn);
175 if (is_mips_irn(irn)) {
176 const arch_register_t **slots;
177 slots = get_mips_slots(irn);
181 reg = mips_get_firm_reg(irn, cur_reg_set);
187 static arch_irn_class_t mips_classify(const ir_node *irn)
189 irn = skip_Proj_const(irn);
192 return arch_irn_class_branch;
193 } else if (is_mips_irn(irn)) {
194 return arch_irn_class_normal;
200 static arch_irn_flags_t mips_get_flags(const ir_node *irn)
202 irn = skip_Proj_const(irn);
204 if (!is_mips_irn(irn))
207 return get_mips_flags(irn);
210 int mips_is_Load(const ir_node *node)
212 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
213 is_mips_lb(node) || is_mips_lbu(node);
216 int mips_is_Store(const ir_node *node)
218 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
221 static ir_entity *mips_get_frame_entity(const ir_node *node)
223 const mips_load_store_attr_t *attr;
225 if(!is_mips_irn(node))
227 if(!mips_is_Load(node) && !mips_is_Store(node))
230 attr = get_mips_load_store_attr_const(node);
231 return attr->stack_entity;
234 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
236 mips_load_store_attr_t *attr;
238 if(!is_mips_irn(node)) {
239 panic("trying to set frame entity on non load/store node %+F", node);
241 if(!mips_is_Load(node) && !mips_is_Store(node)) {
242 panic("trying to set frame entity on non load/store node %+F", node);
245 attr = get_irn_generic_attr(node);
246 attr->stack_entity = entity;
250 * This function is called by the generic backend to correct offsets for
251 * nodes accessing the stack.
253 static void mips_set_frame_offset(ir_node *node, int offset)
255 mips_load_store_attr_t *attr;
257 if(!is_mips_irn(node)) {
258 panic("trying to set frame offset on non load/store node %+F", node);
260 if(!mips_is_Load(node) && !mips_is_Store(node)) {
261 panic("trying to set frame offset on non load/store node %+F", node);
264 attr = get_irn_generic_attr(node);
265 attr->offset += offset;
267 if(attr->offset < -32768 || attr->offset > 32767) {
268 panic("Out of stack space! (mips supports only 16bit offsets)");
272 static int mips_get_sp_bias(const ir_node *irn)
278 /* fill register allocator interface */
280 static const arch_irn_ops_t mips_irn_ops = {
281 mips_get_irn_reg_req,
286 mips_get_frame_entity,
287 mips_set_frame_entity,
288 mips_set_frame_offset,
290 NULL, /* get_inverse */
291 NULL, /* get_op_estimated_cost */
292 NULL, /* possible_memory_operand */
293 NULL, /* perform_memory_operand */
296 /**************************************************
299 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
300 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
301 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
302 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
305 **************************************************/
315 * Ext-Block walker: create a block schedule
317 static void create_block_list(ir_extblk *blk, void *env) {
321 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
322 ir_node *block = get_extbb_block(blk, i);
324 set_irn_link(block, NULL);
326 set_irn_link(list->end, block);
335 /* return the scheduled block at position pos */
336 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
337 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
338 return cg->bl_list[pos];
342 /* return the number of scheduled blocks */
343 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
344 return ARR_LEN(cg->bl_list);
347 /* set a block schedule number */
348 void mips_set_block_sched_nr(ir_node *block, int nr) {
349 set_irn_link(block, INT_TO_PTR(nr));
352 /* get a block schedule number */
353 int mips_get_block_sched_nr(ir_node *block) {
354 return PTR_TO_INT(get_irn_link(block));
358 * Creates a block schedule for the given graph.
360 static void mips_create_block_sched(mips_code_gen_t *cg) {
362 ir_node **bl_list, *block;
366 DEL_ARR_F(cg->bl_list);
367 free_survive_dce(cg->bl_list_sdce);
370 /* calculate the block schedule here */
371 compute_extbb(cg->irg);
376 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
379 bl_list = NEW_ARR_F(ir_node *, list.cnt);
380 cg->bl_list_sdce = new_survive_dce();
381 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
383 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
387 cg->bl_list = bl_list;
391 typedef struct _wenv_t {
396 * Walker: link all CopyB nodes
398 static void collect_copyb_nodes(ir_node *node, void *env) {
401 if (is_CopyB(node)) {
402 set_irn_link(node, wenv->list);
408 static void replace_copyb_nodes(mips_code_gen_t *cg) {
411 ir_node *copy, *next;
412 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
413 const ir_edge_t *edge;
415 /* build code for all copyB */
417 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
419 for (copy = env.list; copy; copy = next) {
420 next = get_irn_link(copy);
422 old_bl = get_nodes_block(copy);
424 jmp = get_Block_cfgpred(old_bl, 0);
425 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
427 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
428 set_nodes_block(jmp, new_bl);
430 mem = gen_code_for_CopyB(new_bl, copy);
432 /* fix copyB's out edges */
433 foreach_out_edge(copy, edge) {
434 ir_node *succ = get_edge_src_irn(edge);
436 assert(is_Proj(succ));
437 switch (get_Proj_proj(succ)) {
438 case pn_CopyB_M_regular:
439 case pn_CopyB_M_except:
443 exchange(succ, get_irg_bad(cg->irg));
452 * Transforms the standard firm graph into
455 static void mips_prepare_graph(void *self) {
456 mips_code_gen_t *cg = self;
459 // replace all copyb nodes in the block with a loop
460 // and mips store/load nodes
461 replace_copyb_nodes(cg);
463 // Calculate block schedule
464 mips_create_block_sched(cg);
466 /* enter the block number into every blocks link field */
467 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
468 ir_node *bl = mips_get_sched_block(cg, bl_nr);
469 mips_set_block_sched_nr(bl, bl_nr);
472 // walk the graph and transform firm nodes into mips nodes where possible
473 mips_transform_graph(cg);
474 dump_ir_block_graph_sched(cg->irg, "-transformed");
478 * Called immediately before emit phase.
480 static void mips_finish_irg(void *self) {
481 mips_code_gen_t *cg = self;
482 ir_graph *irg = cg->irg;
484 dump_ir_block_graph_sched(irg, "-mips-finished");
489 * These are some hooks which must be filled but are probably not needed.
491 static void mips_before_sched(void *self)
496 static void mips_before_ra(void *self)
501 static void mips_after_ra(void* self)
503 mips_code_gen_t *cg = self;
504 be_coalesce_spillslots(cg->birg);
505 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
509 * Emits the code, closes the output file and frees
510 * the code generator interface.
512 static void mips_emit_and_done(void *self)
514 mips_code_gen_t *cg = self;
515 ir_graph *irg = cg->irg;
518 mips_gen_routine(cg, irg);
522 /* de-allocate code generator */
523 del_set(cg->reg_set);
525 DEL_ARR_F(cg->bl_list);
526 free_survive_dce(cg->bl_list_sdce);
531 static void *mips_cg_init(be_irg_t *birg);
533 static const arch_code_generator_if_t mips_code_gen_if = {
535 NULL, /* get_pic_base */
536 NULL, /* before abi introduce */
539 mips_before_sched, /* before scheduling hook */
540 mips_before_ra, /* before register allocation hook */
547 * Initializes the code generator.
549 static void *mips_cg_init(be_irg_t *birg)
551 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
552 mips_isa_t *isa = (mips_isa_t *) arch_env;
553 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
555 cg->impl = &mips_code_gen_if;
556 cg->irg = be_get_birg_irg(birg);
557 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
558 cg->arch_env = arch_env;
563 cur_reg_set = cg->reg_set;
567 return (arch_code_generator_t *)cg;
571 /*****************************************************************
572 * ____ _ _ _____ _____
573 * | _ \ | | | | |_ _|/ ____| /\
574 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
575 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
576 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
577 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
579 *****************************************************************/
581 static mips_isa_t mips_isa_template = {
584 &mips_gp_regs[REG_SP],
585 &mips_gp_regs[REG_FP],
586 -1, /* stack direction */
587 2, /* power of two stack alignment for calls, 2^2 == 4 */
588 NULL, /* main environment */
590 5, /* reload costs */
596 * Initializes the backend ISA and opens the output file.
598 static arch_env_t *mips_init(FILE *file_handle) {
599 static int inited = 0;
606 isa = xcalloc(1, sizeof(isa[0]));
607 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
609 be_emit_init(file_handle);
611 mips_register_init();
612 mips_create_opcodes(&mips_irn_ops);
613 // mips_init_opcode_transforms();
615 /* we mark referenced global entities, so we can only emit those which
616 * are actually referenced. (Note: you mustn't use the type visited flag
617 * elsewhere in the backend)
619 inc_master_type_visited();
621 return &isa->arch_env;
625 * Closes the output file and frees the ISA structure.
627 static void mips_done(void *self)
629 mips_isa_t *isa = self;
631 be_gas_emit_decls(isa->arch_env.main_env, 1);
637 static unsigned mips_get_n_reg_class(const void *self)
643 static const arch_register_class_t *mips_get_reg_class(const void *self,
647 assert(i < N_CLASSES);
648 return &mips_reg_classes[i];
654 * Get the register class which shall be used to store a value of a given mode.
655 * @param self The this pointer.
656 * @param mode The mode in question.
657 * @return A register class which can hold values of the given mode.
659 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
664 ASSERT_NO_FLOAT(mode);
665 return &mips_reg_classes[CLASS_mips_gp];
669 be_abi_call_flags_bits_t flags;
670 const arch_env_t *arch_env;
672 // do special handling to support debuggers
676 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
678 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
679 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
680 env->flags = fl.bits;
682 env->arch_env = arch_env;
687 static void mips_abi_dont_save_regs(void *self, pset *s)
689 mips_abi_env_t *env = self;
691 if(env->flags.try_omit_fp)
692 pset_insert_ptr(s, env->arch_env->bp);
695 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
697 mips_abi_env_t *env = self;
698 ir_graph *irg = env->irg;
699 ir_node *block = get_irg_start_block(env->irg);
700 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
701 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
702 int initialstackframesize;
708 * The calling conventions wants a stack frame of at least 24bytes size with
709 * a0-a3 saved in offset 0-12
710 * fp saved in offset 16
711 * ra saved in offset 20
714 ir_node *sync, *reg, *store;
715 initialstackframesize = 24;
717 // - setup first part of stackframe
718 sp = new_rd_mips_addu(NULL, irg, block, sp,
719 mips_create_Immediate(initialstackframesize));
720 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
721 set_mips_flags(sp, arch_irn_flags_ignore);
723 /* TODO: where to get an edge with a0-a3
725 for(i = 0; i < 4; ++i) {
726 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
727 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
728 attr = get_mips_attr(store);
729 attr->load_store_mode = mode_Iu;
730 attr->tv = new_tarval_from_long(i * 4, mode_Is);
732 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
736 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
737 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16);
741 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
742 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20);
746 /* Note: ideally we would route these mem edges directly towards the
747 * epilogue, but this is currently not supported so we sync all mems
749 sync = new_r_Sync(irg, block, 2, mm+4);
752 ir_node *reg, *store;
753 initialstackframesize = 4;
755 // save old framepointer
756 sp = new_rd_mips_addu(NULL, irg, block, sp,
757 mips_create_Immediate(-initialstackframesize));
758 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
759 set_mips_flags(sp, arch_irn_flags_ignore);
761 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
762 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0);
767 // setup framepointer
768 fp = new_rd_mips_addu(NULL, irg, block, sp,
769 mips_create_Immediate(-initialstackframesize));
770 mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]);
771 set_mips_flags(fp, arch_irn_flags_ignore);
773 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
774 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
776 return &mips_gp_regs[REG_SP];
779 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
781 mips_abi_env_t *env = self;
783 ir_graph *irg = env->irg;
784 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
785 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
787 int initial_frame_size = env->debug ? 24 : 4;
788 int fp_save_offset = env->debug ? 16 : 0;
791 sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero());
792 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
793 set_mips_flags(sp, arch_irn_flags_ignore);
796 load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL,
797 fp_save_offset - initial_frame_size);
798 set_mips_flags(load, arch_irn_flags_ignore);
800 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
801 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
802 arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]);
804 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
805 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
809 * Produces the type which sits between the stack args and the locals on the stack.
810 * it will contain the return address and space to store the old frame pointer.
811 * @return The Firm type modelling the ABI between type.
813 static ir_type *mips_abi_get_between_type(void *self) {
814 mips_abi_env_t *env = self;
816 static ir_type *debug_between_type = NULL;
817 static ir_type *opt_between_type = NULL;
818 static ir_entity *old_fp_ent = NULL;
820 if(env->debug && debug_between_type == NULL) {
821 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
822 ir_entity *ret_addr_ent;
823 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
824 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
825 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
827 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
828 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
829 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
830 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
831 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
832 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
833 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
835 set_entity_offset(a0_ent, 0);
836 set_entity_offset(a1_ent, 4);
837 set_entity_offset(a2_ent, 8);
838 set_entity_offset(a3_ent, 12);
839 set_entity_offset(old_fp_ent, 16);
840 set_entity_offset(ret_addr_ent, 20);
842 set_type_size_bytes(debug_between_type, 24);
843 } else if(!env->debug && opt_between_type == NULL) {
844 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
845 ir_entity *old_fp_ent;
847 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
848 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
849 set_entity_offset(old_fp_ent, 0);
850 set_type_size_bytes(opt_between_type, 4);
853 return env->debug ? debug_between_type : opt_between_type;
856 static const be_abi_callbacks_t mips_abi_callbacks = {
859 mips_abi_get_between_type,
860 mips_abi_dont_save_regs,
866 * Get the ABI restrictions for procedure calls.
867 * @param self The this pointer.
868 * @param method_type The type of the method (procedure) in question.
869 * @param abi The abi object to be modified
871 static void mips_get_call_abi(const void *self, ir_type *method_type,
876 int n = get_method_n_params(method_type);
880 const arch_register_t *reg;
881 be_abi_call_flags_t call_flags;
884 memset(&call_flags, 0, sizeof(call_flags));
885 call_flags.bits.left_to_right = 0;
886 call_flags.bits.store_args_sequential = 0;
887 call_flags.bits.try_omit_fp = 1;
888 call_flags.bits.fp_free = 0;
889 call_flags.bits.call_has_imm = 1;
891 /* set stack parameter passing style */
892 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
894 /* collect the mode for each type */
895 modes = alloca(n * sizeof(modes[0]));
896 for (i = 0; i < n; i++) {
897 tp = get_method_param_type(method_type, i);
898 modes[i] = get_type_mode(tp);
901 // assigns parameters to registers or stack
902 for (i = 0; i < n; i++) {
903 // first 4 params in $a0-$a3, the others on the stack
905 reg = &mips_gp_regs[REG_A0 + i];
906 be_abi_call_param_reg(abi, i, reg);
908 /* default: all parameters on stack */
909 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
913 /* set return register */
914 /* default: return value is in R0 (and maybe R1) */
915 result_count = get_method_n_ress(method_type);
916 assert(result_count <= 2 && "More than 2 result values not supported");
917 for(i = 0; i < result_count; ++i) {
918 const arch_register_t* reg;
919 tp = get_method_res_type(method_type, i);
920 mode = get_type_mode(tp);
921 ASSERT_NO_FLOAT(mode);
923 reg = &mips_gp_regs[REG_V0 + i];
924 be_abi_call_res_reg(abi, i, reg);
929 * Initializes the code generator interface.
931 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
934 return &mips_code_gen_if;
938 * Returns the necessary byte alignment for storing a register of given class.
940 static int mips_get_reg_class_alignment(const void *self,
941 const arch_register_class_t *cls)
943 ir_mode *mode = arch_register_class_mode(cls);
945 return get_mode_size_bytes(mode);
948 static const be_execution_unit_t ***mips_get_allowed_execution_units(
949 const void *self, const ir_node *irn)
954 panic("Unimplemented mips_get_allowed_execution_units()");
957 static const be_machine_t *mips_get_machine(const void *self)
961 panic("Unimplemented mips_get_machine()");
965 * Return irp irgs in the desired order.
967 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
975 * Returns the libFirm configuration parameter for this backend.
977 static const backend_params *mips_get_libfirm_params(void) {
978 static backend_params p = {
979 1, /* need dword lowering */
980 0, /* don't support inline assembler yet */
981 0, /* no immediate floating point mode. */
982 NULL, /* no additional opcodes */
983 NULL, /* will be set later */
984 NULL, /* but yet no creator function */
985 NULL, /* context for create_intrinsic_fkt */
986 NULL, /* no if conversion settings */
987 NULL /* no immediate fp mode */
993 static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
998 return ASM_CONSTRAINT_FLAG_INVALID;
1001 static int mips_is_valid_clobber(const void *self, const char *clobber)
1008 const arch_isa_if_t mips_isa_if = {
1011 mips_get_n_reg_class,
1013 mips_get_reg_class_for_mode,
1015 mips_get_code_generator_if,
1016 mips_get_list_sched_selector,
1017 mips_get_ilp_sched_selector,
1018 mips_get_reg_class_alignment,
1019 mips_get_libfirm_params,
1020 mips_get_allowed_execution_units,
1023 mips_parse_asm_constraint,
1024 mips_is_valid_clobber
1027 void be_init_arch_mips(void)
1029 be_register_isa_if("mips", &mips_isa_if);
1032 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);