2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
46 #include "../bearch_t.h"
47 #include "../benode_t.h"
48 #include "../belower.h"
49 #include "../besched_t.h"
52 #include "../bemachine.h"
53 #include "../bemodule.h"
54 #include "../bespillslots.h"
55 #include "../beemitter.h"
56 #include "../begnuas.h"
58 #include "bearch_mips_t.h"
60 #include "mips_new_nodes.h"
61 #include "gen_mips_regalloc_if.h"
62 #include "mips_transform.h"
63 #include "mips_emitter.h"
64 #include "mips_map_regs.h"
65 #include "mips_util.h"
66 #include "mips_scheduler.h"
68 #define DEBUG_MODULE "firm.be.mips.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a mips node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
90 arch_register_req_t *mips_get_irn_reg_req(const void *self,
91 const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X || mode == mode_M) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
106 /* in case of a proj, we need to get the correct OUT slot */
107 /* of the node corresponding to the proj number */
109 node_pos = mips_translate_proj_pos(node);
115 node = skip_Proj_const(node);
118 /* get requirements for our own nodes */
119 if (is_mips_irn(node)) {
120 const arch_register_req_t *req;
122 req = get_mips_in_req(node, pos);
124 req = get_mips_out_req(node, node_pos);
130 /* unknown should be translated by now */
131 assert(!is_Unknown(node));
133 return arch_no_register_req;
136 static void mips_set_irn_reg(const void *self, ir_node *irn,
137 const arch_register_t *reg)
144 if (get_irn_mode(irn) == mode_X) {
148 pos = mips_translate_proj_pos(irn);
149 irn = skip_Proj(irn);
152 if (is_mips_irn(irn)) {
153 const arch_register_t **slots;
155 slots = get_mips_slots(irn);
159 /* here we set the registers for the Phi nodes */
160 mips_set_firm_reg(irn, reg, cur_reg_set);
164 static const arch_register_t *mips_get_irn_reg(const void *self,
168 const arch_register_t *reg = NULL;
173 if (get_irn_mode(irn) == mode_X) {
177 pos = mips_translate_proj_pos(irn);
178 irn = skip_Proj_const(irn);
181 if (is_mips_irn(irn)) {
182 const arch_register_t **slots;
183 slots = get_mips_slots(irn);
187 reg = mips_get_firm_reg(irn, cur_reg_set);
193 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn)
196 irn = skip_Proj_const(irn);
199 return arch_irn_class_branch;
200 } else if (is_mips_irn(irn)) {
201 return arch_irn_class_normal;
207 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn)
210 irn = skip_Proj_const(irn);
212 if (is_mips_irn(irn)) {
213 return get_mips_flags(irn);
215 else if (is_Unknown(irn)) {
216 return arch_irn_flags_ignore;
223 ir_entity *mips_get_frame_entity(const void *self, const ir_node *node)
225 const mips_attr_t *attr;
228 if(!is_mips_irn(node))
231 attr = get_mips_attr_const(node);
232 return attr->stack_entity;
236 void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent)
238 mips_attr_t *attr = get_mips_attr(irn);
240 attr->stack_entity = ent;
244 * This function is called by the generic backend to correct offsets for
245 * nodes accessing the stack.
247 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset)
254 mips_attr_t *attr = get_mips_attr(irn);
255 attr->stack_entity_offset = offset;
259 static int mips_get_sp_bias(const void *self, const ir_node *irn)
266 /* fill register allocator interface */
268 static const arch_irn_ops_if_t mips_irn_ops_if = {
269 mips_get_irn_reg_req,
274 mips_get_frame_entity,
275 mips_set_frame_entity,
276 mips_set_frame_offset,
278 NULL, /* get_inverse */
279 NULL, /* get_op_estimated_cost */
280 NULL, /* possible_memory_operand */
281 NULL, /* perform_memory_operand */
284 mips_irn_ops_t mips_irn_ops = {
291 /**************************************************
294 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
295 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
296 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
297 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
300 **************************************************/
310 * Ext-Block walker: create a block schedule
312 static void create_block_list(ir_extblk *blk, void *env) {
316 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
317 ir_node *block = get_extbb_block(blk, i);
319 set_irn_link(block, NULL);
321 set_irn_link(list->end, block);
330 /* return the scheduled block at position pos */
331 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
332 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
333 return cg->bl_list[pos];
337 /* return the number of scheduled blocks */
338 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
339 return ARR_LEN(cg->bl_list);
342 /* set a block schedule number */
343 void mips_set_block_sched_nr(ir_node *block, int nr) {
344 set_irn_link(block, INT_TO_PTR(nr));
347 /* get a block schedule number */
348 int mips_get_block_sched_nr(ir_node *block) {
349 return PTR_TO_INT(get_irn_link(block));
353 * Creates a block schedule for the given graph.
355 static void mips_create_block_sched(mips_code_gen_t *cg) {
357 ir_node **bl_list, *block;
361 DEL_ARR_F(cg->bl_list);
362 free_survive_dce(cg->bl_list_sdce);
365 /* calculate the block schedule here */
366 compute_extbb(cg->irg);
371 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
374 bl_list = NEW_ARR_F(ir_node *, list.cnt);
375 cg->bl_list_sdce = new_survive_dce();
376 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
378 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
382 cg->bl_list = bl_list;
386 typedef struct _wenv_t {
391 * Walker: link all CopyB nodes
393 static void collect_copyb_nodes(ir_node *node, void *env) {
396 if (get_irn_op(node) == op_CopyB) {
397 set_irn_link(node, wenv->list);
403 static void replace_copyb_nodes(mips_code_gen_t *cg) {
406 ir_node *copy, *next;
407 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
408 const ir_edge_t *edge;
410 /* build code for all copyB */
412 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
414 for (copy = env.list; copy; copy = next) {
415 next = get_irn_link(copy);
417 old_bl = get_nodes_block(copy);
419 jmp = get_Block_cfgpred(old_bl, 0);
420 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
422 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
423 set_nodes_block(jmp, new_bl);
425 mem = gen_code_for_CopyB(new_bl, copy);
427 /* fix copyB's out edges */
428 foreach_out_edge(copy, edge) {
429 ir_node *succ = get_edge_src_irn(edge);
431 assert(is_Proj(succ));
432 switch (get_Proj_proj(succ)) {
433 case pn_CopyB_M_regular:
434 case pn_CopyB_M_except:
438 exchange(succ, get_irg_bad(cg->irg));
447 * Transforms the standard firm graph into
450 static void mips_prepare_graph(void *self) {
451 mips_code_gen_t *cg = self;
454 // replace all copyb nodes in the block with a loop
455 // and mips store/load nodes
456 replace_copyb_nodes(cg);
458 // Calculate block schedule
459 mips_create_block_sched(cg);
461 /* enter the block number into every blocks link field */
462 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
463 ir_node *bl = mips_get_sched_block(cg, bl_nr);
464 mips_set_block_sched_nr(bl, bl_nr);
467 // walk the graph and transform firm nodes into mips nodes where possible
468 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
470 dump_ir_block_graph_sched(cg->irg, "-transformed");
474 * Called immediately before emit phase.
476 static void mips_finish_irg(void *self) {
477 mips_code_gen_t *cg = self;
478 ir_graph *irg = cg->irg;
480 dump_ir_block_graph_sched(irg, "-mips-finished");
485 * These are some hooks which must be filled but are probably not needed.
487 static void mips_before_sched(void *self)
492 static void mips_before_ra(void *self)
497 static void mips_after_ra(void* self)
499 mips_code_gen_t *cg = self;
500 be_coalesce_spillslots(cg->birg);
501 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
505 * Emits the code, closes the output file and frees
506 * the code generator interface.
508 static void mips_emit_and_done(void *self)
510 mips_code_gen_t *cg = self;
511 ir_graph *irg = cg->irg;
514 mips_gen_routine(cg, irg);
518 /* de-allocate code generator */
519 del_set(cg->reg_set);
521 DEL_ARR_F(cg->bl_list);
522 free_survive_dce(cg->bl_list_sdce);
527 static void *mips_cg_init(be_irg_t *birg);
529 static const arch_code_generator_if_t mips_code_gen_if = {
531 NULL, /* before abi introduce */
534 mips_before_sched, /* before scheduling hook */
535 mips_before_ra, /* before register allocation hook */
542 * Initializes the code generator.
544 static void *mips_cg_init(be_irg_t *birg)
546 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
547 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
548 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
550 cg->impl = &mips_code_gen_if;
551 cg->irg = be_get_birg_irg(birg);
552 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
553 cg->arch_env = arch_env;
558 cur_reg_set = cg->reg_set;
560 mips_irn_ops.cg = cg;
562 return (arch_code_generator_t *)cg;
566 /*****************************************************************
567 * ____ _ _ _____ _____
568 * | _ \ | | | | |_ _|/ ____| /\
569 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
570 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
571 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
572 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
574 *****************************************************************/
576 static mips_isa_t mips_isa_template = {
579 &mips_gp_regs[REG_SP],
580 &mips_gp_regs[REG_FP],
581 -1, /* stack direction */
582 NULL, /* main environment */
584 5, /* reload costs */
586 NULL_EMITTER, /* emitter environment */
590 * Initializes the backend ISA and opens the output file.
592 static void *mips_init(FILE *file_handle) {
593 static int inited = 0;
600 isa = xcalloc(1, sizeof(isa[0]));
601 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
603 be_emit_init_env(&isa->emit, file_handle);
605 mips_register_init();
606 mips_create_opcodes();
607 // mips_init_opcode_transforms();
609 /* we mark referenced global entities, so we can only emit those which
610 * are actually referenced. (Note: you mustn't use the type visited flag
611 * elsewhere in the backend)
613 inc_master_type_visited();
619 * Closes the output file and frees the ISA structure.
621 static void mips_done(void *self)
623 mips_isa_t *isa = self;
625 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
627 be_emit_destroy_env(&isa->emit);
631 static int mips_get_n_reg_class(const void *self)
637 static const arch_register_class_t *mips_get_reg_class(const void *self, int i)
640 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
641 return &mips_reg_classes[i];
647 * Get the register class which shall be used to store a value of a given mode.
648 * @param self The this pointer.
649 * @param mode The mode in question.
650 * @return A register class which can hold values of the given mode.
652 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
656 ASSERT_NO_FLOAT(mode);
657 return &mips_reg_classes[CLASS_mips_gp];
661 be_abi_call_flags_bits_t flags;
662 const arch_isa_t *isa;
663 const arch_env_t *arch_env;
665 // do special handling to support debuggers
669 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
671 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
672 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
673 env->flags = fl.bits;
675 env->arch_env = arch_env;
676 env->isa = arch_env->isa;
681 static void mips_abi_dont_save_regs(void *self, pset *s)
683 mips_abi_env_t *env = self;
685 if(env->flags.try_omit_fp)
686 pset_insert_ptr(s, env->isa->bp);
689 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
691 mips_abi_env_t *env = self;
692 ir_graph *irg = env->irg;
693 dbg_info *dbg = NULL; // TODO where can I get this from?
694 ir_node *block = get_irg_start_block(env->irg);
696 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
697 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
698 int initialstackframesize;
702 * The calling conventions wants a stack frame of at least 24bytes size with
703 * a0-a3 saved in offset 0-12
704 * fp saved in offset 16
705 * ra saved in offset 20
708 ir_node *sync, *reg, *store;
709 initialstackframesize = 24;
711 // - setup first part of stackframe
712 sp = new_rd_mips_addiu(dbg, irg, block, sp);
713 attr = get_mips_attr(sp);
714 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
715 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
716 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
718 /* TODO: where to get an edge with a0-a3
720 for(i = 0; i < 4; ++i) {
721 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
722 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
723 attr = get_mips_attr(store);
724 attr->load_store_mode = mode_Iu;
725 attr->tv = new_tarval_from_long(i * 4, mode_Is);
727 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
731 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
732 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
733 attr = get_mips_attr(store);
734 attr->tv = new_tarval_from_long(16, mode_Hs);
738 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
739 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
740 attr = get_mips_attr(store);
741 attr->tv = new_tarval_from_long(20, mode_Hs);
745 // TODO ideally we would route these mem edges directly towards the epilogue
746 sync = new_r_Sync(irg, block, 2, mm+4);
749 ir_node *reg, *store;
750 initialstackframesize = 4;
752 // save old framepointer
753 sp = new_rd_mips_addiu(dbg, irg, block, sp);
754 attr = get_mips_attr(sp);
755 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
756 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
757 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
759 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
760 store = new_rd_mips_sw(dbg, irg, block, *mem, sp, reg);
761 attr = get_mips_attr(store);
762 attr->tv = new_tarval_from_long(0, mode_Hs);
767 // setup framepointer
768 fp = new_rd_mips_addiu(dbg, irg, block, sp);
769 attr = get_mips_attr(fp);
770 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
771 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
772 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
774 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
775 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
777 return &mips_gp_regs[REG_SP];
780 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
782 mips_abi_env_t *env = self;
783 ir_graph *irg = env->irg;
784 dbg_info *dbg = NULL; // TODO where can I get this from?
786 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
787 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
789 int initial_frame_size = env->debug ? 24 : 4;
790 int fp_save_offset = env->debug ? 16 : 0;
793 sp = new_rd_mips_move(dbg, irg, block, fp);
794 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
795 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
798 load = new_rd_mips_lw(dbg, irg, block, *mem, sp);
799 attr = get_mips_attr(load);
800 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
801 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Hs);
803 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
804 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
805 arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]);
807 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
808 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
812 * Produces the type which sits between the stack args and the locals on the stack.
813 * it will contain the return address and space to store the old frame pointer.
814 * @return The Firm type modelling the ABI between type.
816 static ir_type *mips_abi_get_between_type(void *self) {
817 mips_abi_env_t *env = self;
819 static ir_type *debug_between_type = NULL;
820 static ir_type *opt_between_type = NULL;
821 static ir_entity *old_fp_ent = NULL;
823 if(env->debug && debug_between_type == NULL) {
824 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
825 ir_entity *ret_addr_ent;
826 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
827 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
828 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
830 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
831 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
832 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
833 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
834 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
835 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
836 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
838 set_entity_offset(a0_ent, 0);
839 set_entity_offset(a1_ent, 4);
840 set_entity_offset(a2_ent, 8);
841 set_entity_offset(a3_ent, 12);
842 set_entity_offset(old_fp_ent, 16);
843 set_entity_offset(ret_addr_ent, 20);
845 set_type_size_bytes(debug_between_type, 24);
846 } else if(!env->debug && opt_between_type == NULL) {
847 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
848 ir_entity *old_fp_ent;
850 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
851 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
852 set_entity_offset(old_fp_ent, 0);
853 set_type_size_bytes(opt_between_type, 4);
856 return env->debug ? debug_between_type : opt_between_type;
859 static const be_abi_callbacks_t mips_abi_callbacks = {
862 mips_abi_get_between_type,
863 mips_abi_dont_save_regs,
869 * Get the ABI restrictions for procedure calls.
870 * @param self The this pointer.
871 * @param method_type The type of the method (procedure) in question.
872 * @param abi The abi object to be modified
874 static void mips_get_call_abi(const void *self, ir_type *method_type,
879 int n = get_method_n_params(method_type);
883 const arch_register_t *reg;
884 be_abi_call_flags_t call_flags;
887 memset(&call_flags, 0, sizeof(call_flags));
888 call_flags.bits.left_to_right = 0;
889 call_flags.bits.store_args_sequential = 0;
890 call_flags.bits.try_omit_fp = 1;
891 call_flags.bits.fp_free = 0;
892 call_flags.bits.call_has_imm = 1;
894 /* set stack parameter passing style */
895 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
897 /* collect the mode for each type */
898 modes = alloca(n * sizeof(modes[0]));
899 for (i = 0; i < n; i++) {
900 tp = get_method_param_type(method_type, i);
901 modes[i] = get_type_mode(tp);
904 // assigns parameters to registers or stack
905 for (i = 0; i < n; i++) {
906 // first 4 params in $a0-$a3, the others on the stack
908 reg = &mips_gp_regs[REG_A0 + i];
909 be_abi_call_param_reg(abi, i, reg);
911 /* default: all parameters on stack */
912 be_abi_call_param_stack(abi, i, 4, 0, 0);
916 /* set return register */
917 /* default: return value is in R0 (and maybe R1) */
918 result_count = get_method_n_ress(method_type);
919 assert(result_count <= 2 && "More than 2 result values not supported");
920 for(i = 0; i < result_count; ++i) {
921 const arch_register_t* reg;
922 tp = get_method_res_type(method_type, i);
923 mode = get_type_mode(tp);
924 ASSERT_NO_FLOAT(mode);
926 reg = &mips_gp_regs[REG_V0 + i];
927 be_abi_call_res_reg(abi, i, reg);
931 static const void *mips_get_irn_ops(const arch_irn_handler_t *self,
936 return &mips_irn_ops;
939 const arch_irn_handler_t mips_irn_handler = {
943 const arch_irn_handler_t *mips_get_irn_handler(const void *self)
946 return &mips_irn_handler;
950 * Initializes the code generator interface.
952 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
955 return &mips_code_gen_if;
959 * Returns the necessary byte alignment for storing a register of given class.
961 static int mips_get_reg_class_alignment(const void *self,
962 const arch_register_class_t *cls)
964 ir_mode *mode = arch_register_class_mode(cls);
966 return get_mode_size_bytes(mode);
969 static const be_execution_unit_t ***mips_get_allowed_execution_units(
970 const void *self, const ir_node *irn)
979 static const be_machine_t *mips_get_machine(const void *self)
988 * Return irp irgs in the desired order.
990 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
998 * Returns the libFirm configuration parameter for this backend.
1000 static const backend_params *mips_get_libfirm_params(void) {
1001 static arch_dep_params_t ad = {
1003 0, /* Muls are fast enough on Mips */
1004 31, /* shift would be ok */
1007 32, /* Mulhs & Mulhu available for 32 bit */
1009 static backend_params p = {
1010 1, /* need dword lowering */
1011 0, /* don't support inlien assembler yet */
1012 NULL, /* no additional opcodes */
1013 NULL, /* will be set later */
1014 NULL, /* but yet no creator function */
1015 NULL, /* context for create_intrinsic_fkt */
1016 NULL, /* no if conversion settings */
1023 const arch_isa_if_t mips_isa_if = {
1026 mips_get_n_reg_class,
1028 mips_get_reg_class_for_mode,
1030 mips_get_irn_handler,
1031 mips_get_code_generator_if,
1032 mips_get_list_sched_selector,
1033 mips_get_ilp_sched_selector,
1034 mips_get_reg_class_alignment,
1035 mips_get_libfirm_params,
1036 mips_get_allowed_execution_units,
1041 void be_init_arch_mips(void)
1043 be_register_isa_if("mips", &mips_isa_if);
1046 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);