2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
46 #include "../bearch_t.h"
47 #include "../benode_t.h"
48 #include "../belower.h"
49 #include "../besched_t.h"
52 #include "../bemachine.h"
53 #include "../bemodule.h"
54 #include "../bespillslots.h"
55 #include "../beemitter.h"
56 #include "../begnuas.h"
58 #include "bearch_mips_t.h"
60 #include "mips_new_nodes.h"
61 #include "gen_mips_regalloc_if.h"
62 #include "mips_transform.h"
63 #include "mips_emitter.h"
64 #include "mips_map_regs.h"
65 #include "mips_util.h"
66 #include "mips_scheduler.h"
68 #define DEBUG_MODULE "firm.be.mips.isa"
70 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
71 static set *cur_reg_set = NULL;
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
85 * Return register requirements for a mips node.
86 * If the node returns a tuple (mode_T) then the proj's
87 * will be asked for this information.
90 arch_register_req_t *mips_get_irn_reg_req(const void *self,
91 const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
97 if (is_Block(node) || mode == mode_X || mode == mode_M) {
98 return arch_no_register_req;
101 if (mode == mode_T && pos < 0) {
102 return arch_no_register_req;
106 /* in case of a proj, we need to get the correct OUT slot */
107 /* of the node corresponding to the proj number */
109 node_pos = mips_translate_proj_pos(node);
115 node = skip_Proj_const(node);
118 /* get requirements for our own nodes */
119 if (is_mips_irn(node)) {
120 const arch_register_req_t *req;
122 req = get_mips_in_req(node, pos);
124 req = get_mips_out_req(node, node_pos);
130 /* unknown should be translated by now */
131 assert(!is_Unknown(node));
133 return arch_no_register_req;
136 static void mips_set_irn_reg(const void *self, ir_node *irn,
137 const arch_register_t *reg)
144 if (get_irn_mode(irn) == mode_X) {
148 pos = mips_translate_proj_pos(irn);
149 irn = skip_Proj(irn);
152 if (is_mips_irn(irn)) {
153 const arch_register_t **slots;
155 slots = get_mips_slots(irn);
158 /* here we set the registers for the Phi nodes */
159 mips_set_firm_reg(irn, reg, cur_reg_set);
163 static const arch_register_t *mips_get_irn_reg(const void *self,
167 const arch_register_t *reg = NULL;
172 if (get_irn_mode(irn) == mode_X) {
176 pos = mips_translate_proj_pos(irn);
177 irn = skip_Proj_const(irn);
180 if (is_mips_irn(irn)) {
181 const arch_register_t **slots;
182 slots = get_mips_slots(irn);
186 reg = mips_get_firm_reg(irn, cur_reg_set);
192 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn)
195 irn = skip_Proj_const(irn);
198 return arch_irn_class_branch;
199 } else if (is_mips_irn(irn)) {
200 return arch_irn_class_normal;
206 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn)
209 irn = skip_Proj_const(irn);
211 if (!is_mips_irn(irn))
214 return get_mips_flags(irn);
217 int mips_is_Load(const ir_node *node)
219 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
220 is_mips_lb(node) || is_mips_lbu(node);
223 int mips_is_Store(const ir_node *node)
225 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
228 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *node)
230 const mips_load_store_attr_t *attr;
233 if(!is_mips_irn(node))
235 if(!mips_is_Load(node) && !mips_is_Store(node))
238 attr = get_mips_load_store_attr_const(node);
239 return attr->stack_entity;
242 static void mips_set_frame_entity(const void *self, ir_node *node,
245 mips_load_store_attr_t *attr;
248 if(!is_mips_irn(node)) {
249 panic("trying to set frame entity on non load/store node %+F\n", node);
251 if(!mips_is_Load(node) && !mips_is_Store(node)) {
252 panic("trying to set frame entity on non load/store node %+F\n", node);
255 attr = get_irn_generic_attr(node);
256 attr->stack_entity = entity;
260 * This function is called by the generic backend to correct offsets for
261 * nodes accessing the stack.
263 static void mips_set_frame_offset(const void *self, ir_node *node, int offset)
265 mips_load_store_attr_t *attr;
268 if(!is_mips_irn(node)) {
269 panic("trying to set frame offset on non load/store node %+F\n", node);
271 if(!mips_is_Load(node) && !mips_is_Store(node)) {
272 panic("trying to set frame offset on non load/store node %+F\n", node);
275 attr = get_irn_generic_attr(node);
276 attr->offset += offset;
278 if(attr->offset < -32768 || attr->offset > 32767) {
279 panic("Out of stack space! (mips supports only 16bit offsets)");
283 static int mips_get_sp_bias(const void *self, const ir_node *irn)
290 /* fill register allocator interface */
292 static const arch_irn_ops_if_t mips_irn_ops_if = {
293 mips_get_irn_reg_req,
298 mips_get_frame_entity,
299 mips_set_frame_entity,
300 mips_set_frame_offset,
302 NULL, /* get_inverse */
303 NULL, /* get_op_estimated_cost */
304 NULL, /* possible_memory_operand */
305 NULL, /* perform_memory_operand */
308 mips_irn_ops_t mips_irn_ops = {
315 /**************************************************
318 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
319 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
320 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
321 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
324 **************************************************/
334 * Ext-Block walker: create a block schedule
336 static void create_block_list(ir_extblk *blk, void *env) {
340 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
341 ir_node *block = get_extbb_block(blk, i);
343 set_irn_link(block, NULL);
345 set_irn_link(list->end, block);
354 /* return the scheduled block at position pos */
355 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
356 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
357 return cg->bl_list[pos];
361 /* return the number of scheduled blocks */
362 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
363 return ARR_LEN(cg->bl_list);
366 /* set a block schedule number */
367 void mips_set_block_sched_nr(ir_node *block, int nr) {
368 set_irn_link(block, INT_TO_PTR(nr));
371 /* get a block schedule number */
372 int mips_get_block_sched_nr(ir_node *block) {
373 return PTR_TO_INT(get_irn_link(block));
377 * Creates a block schedule for the given graph.
379 static void mips_create_block_sched(mips_code_gen_t *cg) {
381 ir_node **bl_list, *block;
385 DEL_ARR_F(cg->bl_list);
386 free_survive_dce(cg->bl_list_sdce);
389 /* calculate the block schedule here */
390 compute_extbb(cg->irg);
395 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
398 bl_list = NEW_ARR_F(ir_node *, list.cnt);
399 cg->bl_list_sdce = new_survive_dce();
400 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
402 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
406 cg->bl_list = bl_list;
410 typedef struct _wenv_t {
415 * Walker: link all CopyB nodes
417 static void collect_copyb_nodes(ir_node *node, void *env) {
420 if (get_irn_op(node) == op_CopyB) {
421 set_irn_link(node, wenv->list);
427 static void replace_copyb_nodes(mips_code_gen_t *cg) {
430 ir_node *copy, *next;
431 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
432 const ir_edge_t *edge;
434 /* build code for all copyB */
436 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
438 for (copy = env.list; copy; copy = next) {
439 next = get_irn_link(copy);
441 old_bl = get_nodes_block(copy);
443 jmp = get_Block_cfgpred(old_bl, 0);
444 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
446 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
447 set_nodes_block(jmp, new_bl);
449 mem = gen_code_for_CopyB(new_bl, copy);
451 /* fix copyB's out edges */
452 foreach_out_edge(copy, edge) {
453 ir_node *succ = get_edge_src_irn(edge);
455 assert(is_Proj(succ));
456 switch (get_Proj_proj(succ)) {
457 case pn_CopyB_M_regular:
458 case pn_CopyB_M_except:
462 exchange(succ, get_irg_bad(cg->irg));
471 * Transforms the standard firm graph into
474 static void mips_prepare_graph(void *self) {
475 mips_code_gen_t *cg = self;
478 // replace all copyb nodes in the block with a loop
479 // and mips store/load nodes
480 replace_copyb_nodes(cg);
482 // Calculate block schedule
483 mips_create_block_sched(cg);
485 /* enter the block number into every blocks link field */
486 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
487 ir_node *bl = mips_get_sched_block(cg, bl_nr);
488 mips_set_block_sched_nr(bl, bl_nr);
491 // walk the graph and transform firm nodes into mips nodes where possible
492 mips_transform_graph(cg);
493 dump_ir_block_graph_sched(cg->irg, "-transformed");
497 * Called immediately before emit phase.
499 static void mips_finish_irg(void *self) {
500 mips_code_gen_t *cg = self;
501 ir_graph *irg = cg->irg;
503 dump_ir_block_graph_sched(irg, "-mips-finished");
508 * These are some hooks which must be filled but are probably not needed.
510 static void mips_before_sched(void *self)
515 static void mips_before_ra(void *self)
520 static void mips_after_ra(void* self)
522 mips_code_gen_t *cg = self;
523 be_coalesce_spillslots(cg->birg);
524 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
528 * Emits the code, closes the output file and frees
529 * the code generator interface.
531 static void mips_emit_and_done(void *self)
533 mips_code_gen_t *cg = self;
534 ir_graph *irg = cg->irg;
537 mips_gen_routine(cg, irg);
541 /* de-allocate code generator */
542 del_set(cg->reg_set);
544 DEL_ARR_F(cg->bl_list);
545 free_survive_dce(cg->bl_list_sdce);
550 static void *mips_cg_init(be_irg_t *birg);
552 static const arch_code_generator_if_t mips_code_gen_if = {
554 NULL, /* before abi introduce */
557 mips_before_sched, /* before scheduling hook */
558 mips_before_ra, /* before register allocation hook */
565 * Initializes the code generator.
567 static void *mips_cg_init(be_irg_t *birg)
569 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
570 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
571 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
573 cg->impl = &mips_code_gen_if;
574 cg->irg = be_get_birg_irg(birg);
575 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
576 cg->arch_env = arch_env;
581 cur_reg_set = cg->reg_set;
583 mips_irn_ops.cg = cg;
587 return (arch_code_generator_t *)cg;
591 /*****************************************************************
592 * ____ _ _ _____ _____
593 * | _ \ | | | | |_ _|/ ____| /\
594 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
595 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
596 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
597 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
599 *****************************************************************/
601 static mips_isa_t mips_isa_template = {
604 &mips_gp_regs[REG_SP],
605 &mips_gp_regs[REG_FP],
606 -1, /* stack direction */
607 NULL, /* main environment */
609 5, /* reload costs */
611 NULL_EMITTER, /* emitter environment */
616 * Initializes the backend ISA and opens the output file.
618 static void *mips_init(FILE *file_handle) {
619 static int inited = 0;
626 isa = xcalloc(1, sizeof(isa[0]));
627 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
629 be_emit_init_env(&isa->emit, file_handle);
631 mips_register_init();
632 mips_create_opcodes();
633 // mips_init_opcode_transforms();
635 /* we mark referenced global entities, so we can only emit those which
636 * are actually referenced. (Note: you mustn't use the type visited flag
637 * elsewhere in the backend)
639 inc_master_type_visited();
645 * Closes the output file and frees the ISA structure.
647 static void mips_done(void *self)
649 mips_isa_t *isa = self;
651 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
653 be_emit_destroy_env(&isa->emit);
657 static int mips_get_n_reg_class(const void *self)
663 static const arch_register_class_t *mips_get_reg_class(const void *self, int i)
666 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
667 return &mips_reg_classes[i];
673 * Get the register class which shall be used to store a value of a given mode.
674 * @param self The this pointer.
675 * @param mode The mode in question.
676 * @return A register class which can hold values of the given mode.
678 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
682 ASSERT_NO_FLOAT(mode);
683 return &mips_reg_classes[CLASS_mips_gp];
687 be_abi_call_flags_bits_t flags;
688 const arch_isa_t *isa;
689 const arch_env_t *arch_env;
691 // do special handling to support debuggers
695 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
697 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
698 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
699 env->flags = fl.bits;
701 env->arch_env = arch_env;
702 env->isa = arch_env->isa;
707 static void mips_abi_dont_save_regs(void *self, pset *s)
709 mips_abi_env_t *env = self;
711 if(env->flags.try_omit_fp)
712 pset_insert_ptr(s, env->isa->bp);
715 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
717 mips_abi_env_t *env = self;
718 ir_graph *irg = env->irg;
719 ir_node *block = get_irg_start_block(env->irg);
720 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
721 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
722 int initialstackframesize;
726 * The calling conventions wants a stack frame of at least 24bytes size with
727 * a0-a3 saved in offset 0-12
728 * fp saved in offset 16
729 * ra saved in offset 20
732 ir_node *sync, *reg, *store;
733 initialstackframesize = 24;
735 // - setup first part of stackframe
736 sp = new_rd_mips_addu(NULL, irg, block, sp,
737 mips_create_Immediate(initialstackframesize));
738 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
739 set_mips_flags(sp, arch_irn_flags_ignore);
741 /* TODO: where to get an edge with a0-a3
743 for(i = 0; i < 4; ++i) {
744 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
745 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
746 attr = get_mips_attr(store);
747 attr->load_store_mode = mode_Iu;
748 attr->tv = new_tarval_from_long(i * 4, mode_Is);
750 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
754 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
755 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16);
759 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
760 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20);
764 /* Note: ideally we would route these mem edges directly towards the
765 * epilogue, but this is currently not supported so we sync all mems
767 sync = new_r_Sync(irg, block, 2, mm+4);
770 ir_node *reg, *store;
771 initialstackframesize = 4;
773 // save old framepointer
774 sp = new_rd_mips_addu(NULL, irg, block, sp,
775 mips_create_Immediate(-initialstackframesize));
776 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
777 set_mips_flags(sp, arch_irn_flags_ignore);
779 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
780 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0);
785 // setup framepointer
786 fp = new_rd_mips_addu(NULL, irg, block, sp,
787 mips_create_Immediate(-initialstackframesize));
788 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
789 set_mips_flags(fp, arch_irn_flags_ignore);
791 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
792 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
794 return &mips_gp_regs[REG_SP];
797 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
799 mips_abi_env_t *env = self;
801 ir_graph *irg = env->irg;
802 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
803 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
805 int initial_frame_size = env->debug ? 24 : 4;
806 int fp_save_offset = env->debug ? 16 : 0;
809 sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero());
810 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
811 set_mips_flags(sp, arch_irn_flags_ignore);
814 load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL,
815 fp_save_offset - initial_frame_size);
816 set_mips_flags(load, arch_irn_flags_ignore);
818 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
819 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
820 arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]);
822 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
823 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
827 * Produces the type which sits between the stack args and the locals on the stack.
828 * it will contain the return address and space to store the old frame pointer.
829 * @return The Firm type modelling the ABI between type.
831 static ir_type *mips_abi_get_between_type(void *self) {
832 mips_abi_env_t *env = self;
834 static ir_type *debug_between_type = NULL;
835 static ir_type *opt_between_type = NULL;
836 static ir_entity *old_fp_ent = NULL;
838 if(env->debug && debug_between_type == NULL) {
839 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
840 ir_entity *ret_addr_ent;
841 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
842 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
843 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
845 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
846 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
847 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
848 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
849 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
850 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
851 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
853 set_entity_offset(a0_ent, 0);
854 set_entity_offset(a1_ent, 4);
855 set_entity_offset(a2_ent, 8);
856 set_entity_offset(a3_ent, 12);
857 set_entity_offset(old_fp_ent, 16);
858 set_entity_offset(ret_addr_ent, 20);
860 set_type_size_bytes(debug_between_type, 24);
861 } else if(!env->debug && opt_between_type == NULL) {
862 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
863 ir_entity *old_fp_ent;
865 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
866 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
867 set_entity_offset(old_fp_ent, 0);
868 set_type_size_bytes(opt_between_type, 4);
871 return env->debug ? debug_between_type : opt_between_type;
874 static const be_abi_callbacks_t mips_abi_callbacks = {
877 mips_abi_get_between_type,
878 mips_abi_dont_save_regs,
884 * Get the ABI restrictions for procedure calls.
885 * @param self The this pointer.
886 * @param method_type The type of the method (procedure) in question.
887 * @param abi The abi object to be modified
889 static void mips_get_call_abi(const void *self, ir_type *method_type,
894 int n = get_method_n_params(method_type);
898 const arch_register_t *reg;
899 be_abi_call_flags_t call_flags;
902 memset(&call_flags, 0, sizeof(call_flags));
903 call_flags.bits.left_to_right = 0;
904 call_flags.bits.store_args_sequential = 0;
905 call_flags.bits.try_omit_fp = 1;
906 call_flags.bits.fp_free = 0;
907 call_flags.bits.call_has_imm = 1;
909 /* set stack parameter passing style */
910 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
912 /* collect the mode for each type */
913 modes = alloca(n * sizeof(modes[0]));
914 for (i = 0; i < n; i++) {
915 tp = get_method_param_type(method_type, i);
916 modes[i] = get_type_mode(tp);
919 // assigns parameters to registers or stack
920 for (i = 0; i < n; i++) {
921 // first 4 params in $a0-$a3, the others on the stack
923 reg = &mips_gp_regs[REG_A0 + i];
924 be_abi_call_param_reg(abi, i, reg);
926 /* default: all parameters on stack */
927 be_abi_call_param_stack(abi, i, 4, 0, 0);
931 /* set return register */
932 /* default: return value is in R0 (and maybe R1) */
933 result_count = get_method_n_ress(method_type);
934 assert(result_count <= 2 && "More than 2 result values not supported");
935 for(i = 0; i < result_count; ++i) {
936 const arch_register_t* reg;
937 tp = get_method_res_type(method_type, i);
938 mode = get_type_mode(tp);
939 ASSERT_NO_FLOAT(mode);
941 reg = &mips_gp_regs[REG_V0 + i];
942 be_abi_call_res_reg(abi, i, reg);
946 static const void *mips_get_irn_ops(const arch_irn_handler_t *self,
951 return &mips_irn_ops;
954 const arch_irn_handler_t mips_irn_handler = {
958 const arch_irn_handler_t *mips_get_irn_handler(const void *self)
961 return &mips_irn_handler;
965 * Initializes the code generator interface.
967 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
970 return &mips_code_gen_if;
974 * Returns the necessary byte alignment for storing a register of given class.
976 static int mips_get_reg_class_alignment(const void *self,
977 const arch_register_class_t *cls)
979 ir_mode *mode = arch_register_class_mode(cls);
981 return get_mode_size_bytes(mode);
984 static const be_execution_unit_t ***mips_get_allowed_execution_units(
985 const void *self, const ir_node *irn)
994 static const be_machine_t *mips_get_machine(const void *self)
1003 * Return irp irgs in the desired order.
1005 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
1013 * Returns the libFirm configuration parameter for this backend.
1015 static const backend_params *mips_get_libfirm_params(void) {
1016 static arch_dep_params_t ad = {
1018 0, /* Muls are fast enough on Mips */
1019 31, /* shift would be ok */
1022 32, /* Mulhs & Mulhu available for 32 bit */
1024 static backend_params p = {
1025 1, /* need dword lowering */
1026 0, /* don't support inlien assembler yet */
1027 NULL, /* no additional opcodes */
1028 NULL, /* will be set later */
1029 NULL, /* but yet no creator function */
1030 NULL, /* context for create_intrinsic_fkt */
1031 NULL, /* no if conversion settings */
1038 const arch_isa_if_t mips_isa_if = {
1041 mips_get_n_reg_class,
1043 mips_get_reg_class_for_mode,
1045 mips_get_irn_handler,
1046 mips_get_code_generator_if,
1047 mips_get_list_sched_selector,
1048 mips_get_ilp_sched_selector,
1049 mips_get_reg_class_alignment,
1050 mips_get_libfirm_params,
1051 mips_get_allowed_execution_units,
1056 void be_init_arch_mips(void)
1058 be_register_isa_if("mips", &mips_isa_if);
1061 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);