2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch_t.h"
46 #include "../benode_t.h"
47 #include "../belower.h"
48 #include "../besched_t.h"
49 #include "../beblocksched.h"
50 #include "../beirg_t.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a mips node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
91 arch_register_req_t *mips_get_irn_reg_req(const ir_node *node, int pos)
93 long node_pos = pos == -1 ? 0 : pos;
94 ir_mode *mode = get_irn_mode(node);
96 if (is_Block(node) || mode == mode_X || mode == mode_M) {
97 return arch_no_register_req;
100 if (mode == mode_T && pos < 0) {
101 return arch_no_register_req;
105 /* in case of a proj, we need to get the correct OUT slot */
106 /* of the node corresponding to the proj number */
108 node_pos = mips_translate_proj_pos(node);
114 node = skip_Proj_const(node);
117 /* get requirements for our own nodes */
118 if (is_mips_irn(node)) {
119 const arch_register_req_t *req;
121 req = get_mips_in_req(node, pos);
123 req = get_mips_out_req(node, node_pos);
129 /* unknown should be translated by now */
130 assert(!is_Unknown(node));
132 return arch_no_register_req;
135 static void mips_set_irn_reg(ir_node *irn, const arch_register_t *reg)
141 if (get_irn_mode(irn) == mode_X) {
145 pos = mips_translate_proj_pos(irn);
146 irn = skip_Proj(irn);
149 if (is_mips_irn(irn)) {
150 const arch_register_t **slots;
152 slots = get_mips_slots(irn);
155 /* here we set the registers for the Phi nodes */
156 mips_set_firm_reg(irn, reg, cur_reg_set);
160 static const arch_register_t *mips_get_irn_reg(const ir_node *irn)
163 const arch_register_t *reg = NULL;
167 if (get_irn_mode(irn) == mode_X) {
171 pos = mips_translate_proj_pos(irn);
172 irn = skip_Proj_const(irn);
175 if (is_mips_irn(irn)) {
176 const arch_register_t **slots;
177 slots = get_mips_slots(irn);
181 reg = mips_get_firm_reg(irn, cur_reg_set);
187 static arch_irn_class_t mips_classify(const ir_node *irn)
189 irn = skip_Proj_const(irn);
192 return arch_irn_class_branch;
193 } else if (is_mips_irn(irn)) {
194 return arch_irn_class_normal;
200 static arch_irn_flags_t mips_get_flags(const ir_node *irn)
202 irn = skip_Proj_const(irn);
204 if (!is_mips_irn(irn))
207 return get_mips_flags(irn);
210 int mips_is_Load(const ir_node *node)
212 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
213 is_mips_lb(node) || is_mips_lbu(node);
216 int mips_is_Store(const ir_node *node)
218 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
221 static ir_entity *mips_get_frame_entity(const ir_node *node)
223 const mips_load_store_attr_t *attr;
225 if(!is_mips_irn(node))
227 if(!mips_is_Load(node) && !mips_is_Store(node))
230 attr = get_mips_load_store_attr_const(node);
231 return attr->stack_entity;
234 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
236 mips_load_store_attr_t *attr;
238 if(!is_mips_irn(node)) {
239 panic("trying to set frame entity on non load/store node %+F", node);
241 if(!mips_is_Load(node) && !mips_is_Store(node)) {
242 panic("trying to set frame entity on non load/store node %+F", node);
245 attr = get_irn_generic_attr(node);
246 attr->stack_entity = entity;
250 * This function is called by the generic backend to correct offsets for
251 * nodes accessing the stack.
253 static void mips_set_frame_offset(ir_node *node, int offset)
255 mips_load_store_attr_t *attr;
257 if(!is_mips_irn(node)) {
258 panic("trying to set frame offset on non load/store node %+F", node);
260 if(!mips_is_Load(node) && !mips_is_Store(node)) {
261 panic("trying to set frame offset on non load/store node %+F", node);
264 attr = get_irn_generic_attr(node);
265 attr->offset += offset;
267 if(attr->offset < -32768 || attr->offset > 32767) {
268 panic("Out of stack space! (mips supports only 16bit offsets)");
272 static int mips_get_sp_bias(const ir_node *irn)
278 /* fill register allocator interface */
280 static const arch_irn_ops_t mips_irn_ops = {
281 mips_get_irn_reg_req,
286 mips_get_frame_entity,
287 mips_set_frame_entity,
288 mips_set_frame_offset,
290 NULL, /* get_inverse */
291 NULL, /* get_op_estimated_cost */
292 NULL, /* possible_memory_operand */
293 NULL, /* perform_memory_operand */
296 /**************************************************
299 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
300 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
301 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
302 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
305 **************************************************/
308 * Transforms the standard firm graph into
311 static void mips_prepare_graph(void *self) {
312 mips_code_gen_t *cg = self;
314 /* do local optimizations */
315 optimize_graph_df(cg->irg);
317 /* TODO: we often have dead code reachable through out-edges here. So for
318 * now we rebuild edges (as we need correct user count for code selection)
321 edges_deactivate(cg->irg);
322 edges_activate(cg->irg);
325 // walk the graph and transform firm nodes into mips nodes where possible
326 mips_transform_graph(cg);
327 dump_ir_block_graph_sched(cg->irg, "-transformed");
329 /* do local optimizations (mainly CSE) */
330 optimize_graph_df(cg->irg);
332 /* do code placement, to optimize the position of constants */
335 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
339 * Called immediately before emit phase.
341 static void mips_finish_irg(void *self) {
342 mips_code_gen_t *cg = self;
343 ir_graph *irg = cg->irg;
345 /* create block schedule, this also removes empty blocks which might
346 * produce critical edges */
347 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
349 dump_ir_block_graph_sched(irg, "-mips-finished");
354 * These are some hooks which must be filled but are probably not needed.
356 static void mips_before_sched(void *self)
361 static void mips_before_ra(void *self)
366 static void mips_after_ra(void* self)
368 mips_code_gen_t *cg = self;
369 be_coalesce_spillslots(cg->birg);
370 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
374 * Emits the code, closes the output file and frees
375 * the code generator interface.
377 static void mips_emit_and_done(void *self)
379 mips_code_gen_t *cg = self;
380 ir_graph *irg = cg->irg;
383 mips_gen_routine(cg, irg);
387 /* de-allocate code generator */
388 del_set(cg->reg_set);
392 static void *mips_cg_init(be_irg_t *birg);
394 static const arch_code_generator_if_t mips_code_gen_if = {
396 NULL, /* get_pic_base */
397 NULL, /* before abi introduce */
400 mips_before_sched, /* before scheduling hook */
401 mips_before_ra, /* before register allocation hook */
408 * Initializes the code generator.
410 static void *mips_cg_init(be_irg_t *birg)
412 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
413 mips_isa_t *isa = (mips_isa_t *) arch_env;
414 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
416 cg->impl = &mips_code_gen_if;
417 cg->irg = be_get_birg_irg(birg);
418 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
422 cur_reg_set = cg->reg_set;
426 return (arch_code_generator_t *)cg;
430 /*****************************************************************
431 * ____ _ _ _____ _____
432 * | _ \ | | | | |_ _|/ ____| /\
433 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
434 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
435 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
436 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
438 *****************************************************************/
440 static mips_isa_t mips_isa_template = {
443 &mips_gp_regs[REG_SP],
444 &mips_gp_regs[REG_FP],
445 -1, /* stack direction */
446 2, /* power of two stack alignment for calls, 2^2 == 4 */
447 NULL, /* main environment */
449 5, /* reload costs */
455 * Initializes the backend ISA and opens the output file.
457 static arch_env_t *mips_init(FILE *file_handle) {
458 static int inited = 0;
465 isa = XMALLOC(mips_isa_t);
466 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
468 be_emit_init(file_handle);
470 mips_register_init();
471 mips_create_opcodes(&mips_irn_ops);
472 // mips_init_opcode_transforms();
474 /* we mark referenced global entities, so we can only emit those which
475 * are actually referenced. (Note: you mustn't use the type visited flag
476 * elsewhere in the backend)
478 inc_master_type_visited();
480 return &isa->arch_env;
484 * Closes the output file and frees the ISA structure.
486 static void mips_done(void *self)
488 mips_isa_t *isa = self;
490 be_gas_emit_decls(isa->arch_env.main_env, 1);
496 static unsigned mips_get_n_reg_class(const void *self)
502 static const arch_register_class_t *mips_get_reg_class(const void *self,
506 assert(i < N_CLASSES);
507 return &mips_reg_classes[i];
513 * Get the register class which shall be used to store a value of a given mode.
514 * @param self The this pointer.
515 * @param mode The mode in question.
516 * @return A register class which can hold values of the given mode.
518 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
523 ASSERT_NO_FLOAT(mode);
524 return &mips_reg_classes[CLASS_mips_gp];
528 be_abi_call_flags_bits_t flags;
529 const arch_env_t *arch_env;
531 // do special handling to support debuggers
535 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
537 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
538 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
539 env->flags = fl.bits;
541 env->arch_env = arch_env;
546 static void mips_abi_dont_save_regs(void *self, pset *s)
548 mips_abi_env_t *env = self;
550 if(env->flags.try_omit_fp)
551 pset_insert_ptr(s, env->arch_env->bp);
554 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
556 mips_abi_env_t *env = self;
557 ir_graph *irg = env->irg;
558 ir_node *block = get_irg_start_block(env->irg);
559 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
560 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
561 int initialstackframesize;
567 * The calling conventions wants a stack frame of at least 24bytes size with
568 * a0-a3 saved in offset 0-12
569 * fp saved in offset 16
570 * ra saved in offset 20
573 ir_node *sync, *reg, *store;
574 initialstackframesize = 24;
576 // - setup first part of stackframe
577 sp = new_rd_mips_addu(NULL, irg, block, sp,
578 mips_create_Immediate(initialstackframesize));
579 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
580 set_mips_flags(sp, arch_irn_flags_ignore);
582 /* TODO: where to get an edge with a0-a3
584 for(i = 0; i < 4; ++i) {
585 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
586 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
587 attr = get_mips_attr(store);
588 attr->load_store_mode = mode_Iu;
589 attr->tv = new_tarval_from_long(i * 4, mode_Is);
591 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
595 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
596 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16);
600 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
601 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20);
605 /* Note: ideally we would route these mem edges directly towards the
606 * epilogue, but this is currently not supported so we sync all mems
608 sync = new_r_Sync(irg, block, 2, mm+4);
611 ir_node *reg, *store;
612 initialstackframesize = 4;
614 // save old framepointer
615 sp = new_rd_mips_addu(NULL, irg, block, sp,
616 mips_create_Immediate(-initialstackframesize));
617 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
618 set_mips_flags(sp, arch_irn_flags_ignore);
620 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
621 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0);
626 // setup framepointer
627 fp = new_rd_mips_addu(NULL, irg, block, sp,
628 mips_create_Immediate(-initialstackframesize));
629 mips_set_irn_reg(fp, &mips_gp_regs[REG_FP]);
630 set_mips_flags(fp, arch_irn_flags_ignore);
632 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
633 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
635 return &mips_gp_regs[REG_SP];
638 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
640 mips_abi_env_t *env = self;
642 ir_graph *irg = env->irg;
643 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
644 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
646 int initial_frame_size = env->debug ? 24 : 4;
647 int fp_save_offset = env->debug ? 16 : 0;
650 sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero());
651 mips_set_irn_reg(sp, &mips_gp_regs[REG_SP]);
652 set_mips_flags(sp, arch_irn_flags_ignore);
655 load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL,
656 fp_save_offset - initial_frame_size);
657 set_mips_flags(load, arch_irn_flags_ignore);
659 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
660 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
661 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
663 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
664 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
668 * Produces the type which sits between the stack args and the locals on the stack.
669 * it will contain the return address and space to store the old frame pointer.
670 * @return The Firm type modelling the ABI between type.
672 static ir_type *mips_abi_get_between_type(void *self) {
673 mips_abi_env_t *env = self;
675 static ir_type *debug_between_type = NULL;
676 static ir_type *opt_between_type = NULL;
677 static ir_entity *old_fp_ent = NULL;
679 if(env->debug && debug_between_type == NULL) {
680 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
681 ir_entity *ret_addr_ent;
682 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
683 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
684 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
686 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
687 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
688 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
689 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
690 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
691 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
692 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
694 set_entity_offset(a0_ent, 0);
695 set_entity_offset(a1_ent, 4);
696 set_entity_offset(a2_ent, 8);
697 set_entity_offset(a3_ent, 12);
698 set_entity_offset(old_fp_ent, 16);
699 set_entity_offset(ret_addr_ent, 20);
701 set_type_size_bytes(debug_between_type, 24);
702 } else if(!env->debug && opt_between_type == NULL) {
703 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
704 ir_entity *old_fp_ent;
706 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
707 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
708 set_entity_offset(old_fp_ent, 0);
709 set_type_size_bytes(opt_between_type, 4);
712 return env->debug ? debug_between_type : opt_between_type;
715 static const be_abi_callbacks_t mips_abi_callbacks = {
718 mips_abi_get_between_type,
719 mips_abi_dont_save_regs,
725 * Get the ABI restrictions for procedure calls.
726 * @param self The this pointer.
727 * @param method_type The type of the method (procedure) in question.
728 * @param abi The abi object to be modified
730 static void mips_get_call_abi(const void *self, ir_type *method_type,
735 int n = get_method_n_params(method_type);
739 const arch_register_t *reg;
740 be_abi_call_flags_t call_flags;
743 memset(&call_flags, 0, sizeof(call_flags));
744 call_flags.bits.left_to_right = 0;
745 call_flags.bits.store_args_sequential = 0;
746 call_flags.bits.try_omit_fp = 1;
747 call_flags.bits.fp_free = 0;
748 call_flags.bits.call_has_imm = 1;
750 /* set stack parameter passing style */
751 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
753 /* collect the mode for each type */
754 modes = alloca(n * sizeof(modes[0]));
755 for (i = 0; i < n; i++) {
756 tp = get_method_param_type(method_type, i);
757 modes[i] = get_type_mode(tp);
760 // assigns parameters to registers or stack
761 for (i = 0; i < n; i++) {
762 // first 4 params in $a0-$a3, the others on the stack
764 reg = &mips_gp_regs[REG_A0 + i];
765 be_abi_call_param_reg(abi, i, reg);
767 /* default: all parameters on stack */
768 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
772 /* set return register */
773 /* default: return value is in R0 (and maybe R1) */
774 result_count = get_method_n_ress(method_type);
775 assert(result_count <= 2 && "More than 2 result values not supported");
776 for(i = 0; i < result_count; ++i) {
777 const arch_register_t* reg;
778 tp = get_method_res_type(method_type, i);
779 mode = get_type_mode(tp);
780 ASSERT_NO_FLOAT(mode);
782 reg = &mips_gp_regs[REG_V0 + i];
783 be_abi_call_res_reg(abi, i, reg);
788 * Initializes the code generator interface.
790 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
793 return &mips_code_gen_if;
797 * Returns the necessary byte alignment for storing a register of given class.
799 static int mips_get_reg_class_alignment(const void *self,
800 const arch_register_class_t *cls)
802 ir_mode *mode = arch_register_class_mode(cls);
804 return get_mode_size_bytes(mode);
807 static const be_execution_unit_t ***mips_get_allowed_execution_units(
808 const void *self, const ir_node *irn)
813 panic("Unimplemented mips_get_allowed_execution_units()");
816 static const be_machine_t *mips_get_machine(const void *self)
820 panic("Unimplemented mips_get_machine()");
824 * Return irp irgs in the desired order.
826 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
834 * Returns the libFirm configuration parameter for this backend.
836 static const backend_params *mips_get_libfirm_params(void) {
837 static backend_params p = {
838 1, /* need dword lowering */
839 0, /* don't support inline assembler yet */
840 0, /* no immediate floating point mode. */
841 NULL, /* no additional opcodes */
842 NULL, /* will be set later */
843 NULL, /* but yet no creator function */
844 NULL, /* context for create_intrinsic_fkt */
845 NULL, /* no if conversion settings */
846 NULL /* no immediate fp mode */
852 static asm_constraint_flags_t mips_parse_asm_constraint(const void *self,
857 return ASM_CONSTRAINT_FLAG_INVALID;
860 static int mips_is_valid_clobber(const void *self, const char *clobber)
867 const arch_isa_if_t mips_isa_if = {
870 mips_get_n_reg_class,
872 mips_get_reg_class_for_mode,
874 mips_get_code_generator_if,
875 mips_get_list_sched_selector,
876 mips_get_ilp_sched_selector,
877 mips_get_reg_class_alignment,
878 mips_get_libfirm_params,
879 mips_get_allowed_execution_units,
882 NULL, /* mark remat */
883 mips_parse_asm_constraint,
884 mips_is_valid_clobber
887 void be_init_arch_mips(void)
889 be_register_isa_if("mips", &mips_isa_if);
892 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);