1 /* The main mips backend driver file. */
8 #include "pseudo_irg.h"
23 #include "../bearch.h" /* the general register allocator interface */
24 #include "../benode_t.h"
25 #include "../belower.h"
26 #include "../besched_t.h"
30 #include "bearch_mips_t.h"
32 #include "mips_new_nodes.h" /* mips nodes interface */
33 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "mips_gen_decls.h" /* interface declaration emitter */
35 #include "mips_transform.h"
36 #include "mips_emitter.h"
37 #include "mips_map_regs.h"
38 #include "mips_util.h"
39 #include "mips_scheduler.h"
41 #define DEBUG_MODULE "firm.be.mips.isa"
43 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
44 static set *cur_reg_set = NULL;
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
57 static ir_node *my_skip_proj(const ir_node *n) {
64 * Return register requirements for a mips node.
65 * If the node returns a tuple (mode_T) then the proj's
66 * will be asked for this information.
68 static const arch_register_req_t *mips_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
69 const mips_register_req_t *irn_req;
70 long node_pos = pos == -1 ? 0 : pos;
71 ir_mode *mode = get_irn_mode(irn);
72 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
74 if (is_Block(irn) || mode == mode_X || mode == mode_M) {
75 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
79 if (mode == mode_T && pos < 0) {
80 DBG((mod, LEVEL_1, "ignoring request for OUT requirements at %+F\n", irn));
84 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
87 /* in case of a proj, we need to get the correct OUT slot */
88 /* of the node corresponding to the proj number */
90 node_pos = mips_translate_proj_pos(irn);
96 irn = my_skip_proj(irn);
98 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
101 /* get requirements for our own nodes */
102 if (is_mips_irn(irn)) {
104 irn_req = get_mips_in_req(irn, pos);
107 irn_req = get_mips_out_req(irn, node_pos);
110 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
112 memcpy(req, &(irn_req->req), sizeof(*req));
114 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
115 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
116 req->other_same = get_irn_n(irn, irn_req->same_pos);
119 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
120 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
121 req->other_different = get_irn_n(irn, irn_req->different_pos);
124 /* get requirements for FIRM nodes */
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
130 if (mode_is_float(mode)) {
131 //memcpy(req, &(mips_default_req_mips_floating_point.req), sizeof(*req));
132 assert(0 && "floating point not supported (yet)");
134 else if (mode_is_int(mode) || mode_is_reference(mode)) {
135 memcpy(req, &(mips_default_req_mips_gp.req), sizeof(*req));
137 else if (mode == mode_T || mode == mode_M) {
138 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
142 assert(0 && "unsupported Phi-Mode");
146 DB((mod, LEVEL_1, "returning NULL for %+F (node not supported)\n", irn));
154 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
159 if (get_irn_mode(irn) == mode_X) {
163 pos = mips_translate_proj_pos(irn);
164 irn = my_skip_proj(irn);
167 if (is_mips_irn(irn)) {
168 const arch_register_t **slots;
170 slots = get_mips_slots(irn);
174 /* here we set the registers for the Phi nodes */
175 mips_set_firm_reg(irn, reg, cur_reg_set);
179 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
181 const arch_register_t *reg = NULL;
185 if (get_irn_mode(irn) == mode_X) {
189 pos = mips_translate_proj_pos(irn);
190 irn = my_skip_proj(irn);
193 if (is_mips_irn(irn)) {
194 const arch_register_t **slots;
195 slots = get_mips_slots(irn);
199 reg = mips_get_firm_reg(irn, cur_reg_set);
205 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
206 irn = my_skip_proj(irn);
209 return arch_irn_class_branch;
210 } else if (is_mips_irn(irn)) {
211 return arch_irn_class_normal;
217 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
218 irn = my_skip_proj(irn);
220 if (is_mips_irn(irn)) {
221 return get_mips_flags(irn);
223 else if (is_Unknown(irn)) {
224 return arch_irn_flags_ignore;
230 static entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
231 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
232 mips_attr_t *attr = get_mips_attr(irn);
234 return attr->stack_entity;
240 static void mips_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
241 mips_attr_t *attr = get_mips_attr(irn);
242 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
243 attr->stack_entity = ent;
247 * This function is called by the generic backend to correct offsets for
248 * nodes accessing the stack.
250 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
251 mips_attr_t *attr = get_mips_attr(irn);
252 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
254 attr->stack_entity_offset = offset;
257 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
261 /* fill register allocator interface */
263 static const arch_irn_ops_if_t mips_irn_ops_if = {
264 mips_get_irn_reg_req,
269 mips_get_frame_entity,
270 mips_set_frame_entity,
271 mips_set_frame_offset,
273 NULL, /* get_inverse */
274 NULL, /* get_op_estimated_cost */
275 NULL, /* possible_memory_operand */
276 NULL, /* perform_memory_operand */
279 mips_irn_ops_t mips_irn_ops = {
286 /**************************************************
289 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
290 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
291 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
292 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
295 **************************************************/
305 * Ext-Block walker: create a block schedule
307 static void create_block_list(ir_extblk *blk, void *env) {
311 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
312 ir_node *block = get_extbb_block(blk, i);
314 set_irn_link(block, NULL);
316 set_irn_link(list->end, block);
325 /* return the scheduled block at position pos */
326 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
327 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
328 return cg->bl_list[pos];
332 /* return the number of scheduled blocks */
333 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
334 return ARR_LEN(cg->bl_list);
337 /* set a block schedule number */
338 void mips_set_block_sched_nr(ir_node *block, int nr) {
339 set_irn_link(block, INT_TO_PTR(nr));
342 /* get a block schedule number */
343 int mips_get_block_sched_nr(ir_node *block) {
344 return PTR_TO_INT(get_irn_link(block));
348 * Creates a block schedule for the given graph.
350 static void mips_create_block_sched(mips_code_gen_t *cg) {
352 ir_node **bl_list, *block;
356 DEL_ARR_F(cg->bl_list);
357 free_survive_dce(cg->bl_list_sdce);
360 /* calculate the block schedule here */
361 compute_extbb(cg->irg);
366 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
369 bl_list = NEW_ARR_F(ir_node *, list.cnt);
370 cg->bl_list_sdce = new_survive_dce();
371 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
373 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
377 cg->bl_list = bl_list;
380 typedef struct _wenv_t {
385 * Walker: link all CopyB nodes
387 static void collect_copyb_nodes(ir_node *node, void *env) {
390 if (get_irn_op(node) == op_CopyB) {
391 set_irn_link(node, wenv->list);
396 static void replace_copyb_nodes(mips_code_gen_t *cg) {
398 ir_node *copy, *next;
399 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
400 const ir_edge_t *edge;
402 /* build code for all copyB */
404 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
406 for (copy = env.list; copy; copy = next) {
407 next = get_irn_link(copy);
409 old_bl = get_nodes_block(copy);
411 jmp = get_Block_cfgpred(old_bl, 0);
412 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
414 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
415 set_nodes_block(jmp, new_bl);
417 mem = gen_code_for_CopyB(new_bl, copy);
419 /* fix copyB's out edges */
420 foreach_out_edge(copy, edge) {
421 ir_node *succ = get_edge_src_irn(edge);
423 assert(is_Proj(succ));
424 switch (get_Proj_proj(succ)) {
425 case pn_CopyB_M_regular:
426 case pn_CopyB_M_except:
430 exchange(succ, get_irg_bad(cg->irg));
437 * Transforms the standard firm graph into
440 static void mips_prepare_graph(void *self) {
441 mips_code_gen_t *cg = self;
444 // replace all copyb nodes in the block with a loop
445 // and mips store/load nodes
446 replace_copyb_nodes(cg);
448 // Calculate block schedule
449 mips_create_block_sched(cg);
451 /* enter the block number into every blocks link field */
452 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
453 ir_node *bl = mips_get_sched_block(cg, bl_nr);
454 mips_set_block_sched_nr(bl, bl_nr);
457 // walk the graph and transform firm nodes into mips nodes where possible
458 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
460 dump_ir_block_graph_sched(cg->irg, "-transformed");
464 * Called immediately before emit phase.
466 static void mips_finish_irg(void *self) {
467 mips_code_gen_t *cg = self;
468 ir_graph *irg = cg->irg;
470 dump_ir_block_graph_sched(irg, "-mips-finished");
475 * These are some hooks which must be filled but are probably not needed.
477 static void mips_before_sched(void *self) {
478 /* Some stuff you need to do after scheduling but before register allocation */
481 static void mips_before_ra(void *self) {
482 /* Some stuff you need to do immediately after register allocation */
485 static void mips_after_ra(void* self) {
486 mips_code_gen_t *cg = self;
487 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
491 * Emits the code, closes the output file and frees
492 * the code generator interface.
494 static void mips_emit_and_done(void *self) {
495 mips_code_gen_t *cg = self;
496 ir_graph *irg = cg->irg;
497 FILE *out = cg->isa->out;
499 mips_register_emitters();
501 if (cg->emit_decls) {
506 mips_gen_routine(out, irg, cg);
510 /* de-allocate code generator */
511 del_set(cg->reg_set);
513 DEL_ARR_F(cg->bl_list);
514 free_survive_dce(cg->bl_list_sdce);
519 static void *mips_cg_init(const be_irg_t *birg);
521 static const arch_code_generator_if_t mips_code_gen_if = {
523 NULL, /* before abi introduce */
525 mips_before_sched, /* before scheduling hook */
526 mips_before_ra, /* before register allocation hook */
533 * Initializes the code generator.
535 static void *mips_cg_init(const be_irg_t *birg) {
536 mips_isa_t *isa = (mips_isa_t *)birg->main_env->arch_env->isa;
537 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
539 cg->impl = &mips_code_gen_if;
541 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
542 cg->arch_env = birg->main_env->arch_env;
546 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
550 if (isa->num_codegens > 1)
555 cur_reg_set = cg->reg_set;
557 mips_irn_ops.cg = cg;
559 return (arch_code_generator_t *)cg;
563 /*****************************************************************
564 * ____ _ _ _____ _____
565 * | _ \ | | | | |_ _|/ ____| /\
566 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
567 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
568 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
569 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
571 *****************************************************************/
573 static mips_isa_t mips_isa_template = {
575 &mips_gp_regs[REG_SP],
576 &mips_gp_regs[REG_FP],
577 -1, // stack direction
578 0, // num codegens?!? TODO what is this?
583 * Initializes the backend ISA and opens the output file.
585 static void *mips_init(FILE *file_handle) {
586 static int inited = 0;
592 isa = xcalloc(1, sizeof(*isa));
593 memcpy(isa, &mips_isa_template, sizeof(*isa));
595 isa->out = file_handle;
597 mips_register_init(isa);
598 mips_create_opcodes();
599 mips_init_opcode_transforms();
607 * Closes the output file and frees the ISA structure.
609 static void mips_done(void *self) {
613 static int mips_get_n_reg_class(const void *self) {
617 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
618 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
619 return &mips_reg_classes[i];
625 * Get the register class which shall be used to store a value of a given mode.
626 * @param self The this pointer.
627 * @param mode The mode in question.
628 * @return A register class which can hold values of the given mode.
630 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
631 ASSERT_NO_FLOAT(mode);
632 return &mips_reg_classes[CLASS_mips_gp];
636 be_abi_call_flags_bits_t flags;
637 const mips_isa_t *isa;
638 const arch_env_t *arch_env;
640 // do special handling to support debuggers
644 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
646 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
647 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
648 env->flags = fl.bits;
650 env->arch_env = arch_env;
651 env->isa = (const mips_isa_t*) arch_env->isa;
656 static void mips_abi_dont_save_regs(void *self, pset *s)
658 mips_abi_env_t *env = self;
659 if(env->flags.try_omit_fp)
660 pset_insert_ptr(s, env->isa->fp);
663 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
665 mips_abi_env_t *env = self;
666 ir_graph *irg = env->irg;
667 dbg_info *dbg = NULL; // TODO where can I get this from?
668 ir_node *block = get_irg_start_block(env->irg);
670 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
671 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
672 int initialstackframesize;
676 * The calling conventions wants a stack frame of at least 24bytes size with
677 * a0-a3 saved in offset 0-12
678 * fp saved in offset 16
679 * ra saved in offset 20
682 ir_node *sync, *reg, *store;
683 initialstackframesize = 24;
685 // - setup first part of stackframe
686 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
687 attr = get_mips_attr(sp);
688 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
689 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
690 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
692 /* TODO: where to get an edge with a0-a3
694 for(i = 0; i < 4; ++i) {
695 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
696 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
697 attr = get_mips_attr(store);
698 attr->load_store_mode = mode_Iu;
699 attr->tv = new_tarval_from_long(i * 4, mode_Is);
701 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
705 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
706 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
707 attr = get_mips_attr(store);
708 attr->modes.load_store_mode = mode_Iu;
709 attr->tv = new_tarval_from_long(16, mode_Is);
711 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
713 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
714 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
715 attr = get_mips_attr(store);
716 attr->modes.load_store_mode = mode_Iu;
717 attr->tv = new_tarval_from_long(20, mode_Is);
719 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
721 // TODO ideally we would route these mem edges directly towards the epilogue
722 sync = new_r_Sync(irg, block, 2, mm+4);
725 ir_node *reg, *store;
726 initialstackframesize = 4;
728 // save old framepointer
729 sp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
730 attr = get_mips_attr(sp);
731 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
732 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
733 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
735 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
736 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
737 attr = get_mips_attr(store);
738 attr->modes.load_store_mode = mode_Iu;
739 attr->tv = new_tarval_from_long(0, mode_Is);
741 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
744 // setup framepointer
745 fp = new_rd_mips_addi(dbg, irg, block, sp, mode_Is);
746 attr = get_mips_attr(fp);
747 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
748 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
749 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
751 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
752 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
754 return &mips_gp_regs[REG_SP];
757 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
759 mips_abi_env_t *env = self;
760 ir_graph *irg = env->irg;
761 dbg_info *dbg = NULL; // TODO where can I get this from?
763 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
764 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
766 int initial_frame_size = env->debug ? 24 : 4;
767 int fp_save_offset = env->debug ? 16 : 0;
770 sp = new_rd_mips_move(dbg, irg, block, fp, mode_Iu);
771 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
772 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
775 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
776 attr = get_mips_attr(load);
777 attr->modes.load_store_mode = mode_Iu;
778 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
779 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
781 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
782 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
783 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
785 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
786 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
790 * Produces the type which sits between the stack args and the locals on the stack.
791 * it will contain the return address and space to store the old frame pointer.
792 * @return The Firm type modelling the ABI between type.
794 static ir_type *mips_abi_get_between_type(void *self) {
795 mips_abi_env_t *env = self;
797 static ir_type *debug_between_type = NULL;
798 static ir_type *opt_between_type = NULL;
799 static entity *old_fp_ent = NULL;
801 if(env->debug && debug_between_type == NULL) {
802 entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
803 entity *ret_addr_ent;
804 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
805 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
806 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
808 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
809 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
810 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
811 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
812 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
813 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
814 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
816 set_entity_offset_bytes(a0_ent, 0);
817 set_entity_offset_bytes(a1_ent, 4);
818 set_entity_offset_bytes(a2_ent, 8);
819 set_entity_offset_bytes(a3_ent, 12);
820 set_entity_offset_bytes(old_fp_ent, 16);
821 set_entity_offset_bytes(ret_addr_ent, 20);
823 set_type_size_bytes(debug_between_type, 24);
824 } else if(!env->debug && opt_between_type == NULL) {
825 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
828 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
829 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
830 set_entity_offset_bytes(old_fp_ent, 0);
831 set_type_size_bytes(opt_between_type, 4);
834 return env->debug ? debug_between_type : opt_between_type;
837 static const be_abi_callbacks_t mips_abi_callbacks = {
840 mips_abi_get_between_type,
841 mips_abi_dont_save_regs,
847 * Get the ABI restrictions for procedure calls.
848 * @param self The this pointer.
849 * @param method_type The type of the method (procedure) in question.
850 * @param abi The abi object to be modified
852 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
855 int n = get_method_n_params(method_type);
859 const arch_register_t *reg;
860 be_abi_call_flags_t call_flags;
862 memset(&call_flags, 0, sizeof(call_flags));
863 call_flags.bits.left_to_right = 0;
864 call_flags.bits.store_args_sequential = 0;
865 call_flags.bits.try_omit_fp = 1;
866 call_flags.bits.fp_free = 0;
867 call_flags.bits.call_has_imm = 1;
869 /* set stack parameter passing style */
870 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
872 /* collect the mode for each type */
873 modes = alloca(n * sizeof(modes[0]));
874 for (i = 0; i < n; i++) {
875 tp = get_method_param_type(method_type, i);
876 modes[i] = get_type_mode(tp);
879 // assigns parameters to registers or stack
880 for (i = 0; i < n; i++) {
881 // first 4 params in $a0-$a3, the others on the stack
883 reg = &mips_gp_regs[REG_A0 + i];
884 be_abi_call_param_reg(abi, i, reg);
886 /* default: all parameters on stack */
887 be_abi_call_param_stack(abi, i, 4, 0, 0);
891 /* set return register */
892 /* default: return value is in R0 (and maybe R1) */
893 result_count = get_method_n_ress(method_type);
894 assert(result_count <= 2 && "More than 2 result values not supported");
895 for(i = 0; i < result_count; ++i) {
896 const arch_register_t* reg;
897 tp = get_method_res_type(method_type, i);
898 mode = get_type_mode(tp);
899 ASSERT_NO_FLOAT(mode);
901 reg = &mips_gp_regs[REG_V0 + i];
902 be_abi_call_res_reg(abi, i, reg);
906 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
907 return &mips_irn_ops;
910 const arch_irn_handler_t mips_irn_handler = {
914 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
915 return &mips_irn_handler;
919 * Initializes the code generator interface.
921 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
922 return &mips_code_gen_if;
926 * Returns the necessary byte alignment for storing a register of given class.
928 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
929 ir_mode *mode = arch_register_class_mode(cls);
930 return get_mode_size_bytes(mode);
934 * Returns the libFirm configuration parameter for this backend.
936 static const backend_params *mips_get_libfirm_params(void) {
937 static arch_dep_params_t ad = {
939 0, /* Muls are fast enough on Mips */
940 31, /* shift would be ok */
943 32, /* Mulhs & Mulhu available for 32 bit */
945 static backend_params p = {
946 NULL, /* no additional opcodes */
947 NULL, /* will be set later */
948 1, /* need dword lowering */
949 NULL, /* but yet no creator function */
950 NULL, /* context for create_intrinsic_fkt */
958 static void mips_register_options(lc_opt_entry_t *ent)
961 #endif /* WITH_LIBCORE */
963 const arch_isa_if_t mips_isa_if = {
966 mips_get_n_reg_class,
968 mips_get_reg_class_for_mode,
970 mips_get_irn_handler,
971 mips_get_code_generator_if,
972 mips_get_list_sched_selector,
973 mips_get_reg_class_alignment,
974 mips_get_libfirm_params,
976 mips_register_options