2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 /* The main mips backend driver file. */
26 #include "pseudo_irg.h"
41 #include "../bearch_t.h" /* the general register allocator interface */
42 #include "../benode_t.h"
43 #include "../belower.h"
44 #include "../besched_t.h"
47 #include "../bemachine.h"
48 #include "../bemodule.h"
50 #include "bearch_mips_t.h"
52 #include "mips_new_nodes.h" /* mips nodes interface */
53 #include "gen_mips_regalloc_if.h" /* the generated interface (register type and class defenitions) */
54 #include "mips_gen_decls.h" /* interface declaration emitter */
55 #include "mips_transform.h"
56 #include "mips_emitter.h"
57 #include "mips_map_regs.h"
58 #include "mips_util.h"
59 #include "mips_scheduler.h"
61 #define DEBUG_MODULE "firm.be.mips.isa"
63 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
64 static set *cur_reg_set = NULL;
66 /**************************************************
69 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
70 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
71 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
72 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
75 **************************************************/
78 * Return register requirements for a mips node.
79 * If the node returns a tuple (mode_T) then the proj's
80 * will be asked for this information.
83 arch_register_req_t *mips_get_irn_reg_req(const void *self,
84 const ir_node *node, int pos) {
85 long node_pos = pos == -1 ? 0 : pos;
86 ir_mode *mode = get_irn_mode(node);
88 if (is_Block(node) || mode == mode_X || mode == mode_M) {
89 return arch_no_register_req;
92 if (mode == mode_T && pos < 0) {
93 return arch_no_register_req;
97 /* in case of a proj, we need to get the correct OUT slot */
98 /* of the node corresponding to the proj number */
100 node_pos = mips_translate_proj_pos(node);
106 node = skip_Proj_const(node);
109 /* get requirements for our own nodes */
110 if (is_mips_irn(node)) {
111 const arch_register_req_t *req;
113 req = get_mips_in_req(node, pos);
115 req = get_mips_out_req(node, node_pos);
121 /* unknown should be translated by now */
122 assert(!is_Unknown(node));
124 return arch_no_register_req;
127 static void mips_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
132 if (get_irn_mode(irn) == mode_X) {
136 pos = mips_translate_proj_pos(irn);
137 irn = skip_Proj(irn);
140 if (is_mips_irn(irn)) {
141 const arch_register_t **slots;
143 slots = get_mips_slots(irn);
147 /* here we set the registers for the Phi nodes */
148 mips_set_firm_reg(irn, reg, cur_reg_set);
152 static const arch_register_t *mips_get_irn_reg(const void *self, const ir_node *irn) {
154 const arch_register_t *reg = NULL;
158 if (get_irn_mode(irn) == mode_X) {
162 pos = mips_translate_proj_pos(irn);
163 irn = skip_Proj_const(irn);
166 if (is_mips_irn(irn)) {
167 const arch_register_t **slots;
168 slots = get_mips_slots(irn);
172 reg = mips_get_firm_reg(irn, cur_reg_set);
178 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn) {
179 irn = skip_Proj_const(irn);
182 return arch_irn_class_branch;
183 } else if (is_mips_irn(irn)) {
184 return arch_irn_class_normal;
190 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn) {
191 irn = skip_Proj_const(irn);
193 if (is_mips_irn(irn)) {
194 return get_mips_flags(irn);
196 else if (is_Unknown(irn)) {
197 return arch_irn_flags_ignore;
203 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *irn) {
204 if(is_mips_load_r(irn) || is_mips_store_r(irn)) {
205 mips_attr_t *attr = get_mips_attr(irn);
207 return attr->stack_entity;
213 static void mips_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
214 mips_attr_t *attr = get_mips_attr(irn);
215 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
216 attr->stack_entity = ent;
220 * This function is called by the generic backend to correct offsets for
221 * nodes accessing the stack.
223 static void mips_set_frame_offset(const void *self, ir_node *irn, int offset) {
224 mips_attr_t *attr = get_mips_attr(irn);
225 assert(is_mips_load_r(irn) || is_mips_store_r(irn));
227 attr->stack_entity_offset = offset;
230 static int mips_get_sp_bias(const void *self, const ir_node *irn) {
234 /* fill register allocator interface */
236 static const arch_irn_ops_if_t mips_irn_ops_if = {
237 mips_get_irn_reg_req,
242 mips_get_frame_entity,
243 mips_set_frame_entity,
244 mips_set_frame_offset,
246 NULL, /* get_inverse */
247 NULL, /* get_op_estimated_cost */
248 NULL, /* possible_memory_operand */
249 NULL, /* perform_memory_operand */
252 mips_irn_ops_t mips_irn_ops = {
259 /**************************************************
262 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
263 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
264 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
265 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
268 **************************************************/
278 * Ext-Block walker: create a block schedule
280 static void create_block_list(ir_extblk *blk, void *env) {
284 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
285 ir_node *block = get_extbb_block(blk, i);
287 set_irn_link(block, NULL);
289 set_irn_link(list->end, block);
298 /* return the scheduled block at position pos */
299 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
300 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
301 return cg->bl_list[pos];
305 /* return the number of scheduled blocks */
306 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
307 return ARR_LEN(cg->bl_list);
310 /* set a block schedule number */
311 void mips_set_block_sched_nr(ir_node *block, int nr) {
312 set_irn_link(block, INT_TO_PTR(nr));
315 /* get a block schedule number */
316 int mips_get_block_sched_nr(ir_node *block) {
317 return PTR_TO_INT(get_irn_link(block));
321 * Creates a block schedule for the given graph.
323 static void mips_create_block_sched(mips_code_gen_t *cg) {
325 ir_node **bl_list, *block;
329 DEL_ARR_F(cg->bl_list);
330 free_survive_dce(cg->bl_list_sdce);
333 /* calculate the block schedule here */
334 compute_extbb(cg->irg);
339 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
342 bl_list = NEW_ARR_F(ir_node *, list.cnt);
343 cg->bl_list_sdce = new_survive_dce();
344 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
346 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
350 cg->bl_list = bl_list;
353 typedef struct _wenv_t {
358 * Walker: link all CopyB nodes
360 static void collect_copyb_nodes(ir_node *node, void *env) {
363 if (get_irn_op(node) == op_CopyB) {
364 set_irn_link(node, wenv->list);
369 static void replace_copyb_nodes(mips_code_gen_t *cg) {
371 ir_node *copy, *next;
372 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
373 const ir_edge_t *edge;
375 /* build code for all copyB */
377 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
379 for (copy = env.list; copy; copy = next) {
380 next = get_irn_link(copy);
382 old_bl = get_nodes_block(copy);
384 jmp = get_Block_cfgpred(old_bl, 0);
385 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
387 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
388 set_nodes_block(jmp, new_bl);
390 mem = gen_code_for_CopyB(new_bl, copy);
392 /* fix copyB's out edges */
393 foreach_out_edge(copy, edge) {
394 ir_node *succ = get_edge_src_irn(edge);
396 assert(is_Proj(succ));
397 switch (get_Proj_proj(succ)) {
398 case pn_CopyB_M_regular:
399 case pn_CopyB_M_except:
403 exchange(succ, get_irg_bad(cg->irg));
410 * Transforms the standard firm graph into
413 static void mips_prepare_graph(void *self) {
414 mips_code_gen_t *cg = self;
417 // replace all copyb nodes in the block with a loop
418 // and mips store/load nodes
419 replace_copyb_nodes(cg);
421 // Calculate block schedule
422 mips_create_block_sched(cg);
424 /* enter the block number into every blocks link field */
425 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
426 ir_node *bl = mips_get_sched_block(cg, bl_nr);
427 mips_set_block_sched_nr(bl, bl_nr);
430 // walk the graph and transform firm nodes into mips nodes where possible
431 irg_walk_blkwise_graph(cg->irg, mips_pre_transform_node, mips_transform_node, cg);
433 dump_ir_block_graph_sched(cg->irg, "-transformed");
437 * Called immediately before emit phase.
439 static void mips_finish_irg(void *self) {
440 mips_code_gen_t *cg = self;
441 ir_graph *irg = cg->irg;
443 dump_ir_block_graph_sched(irg, "-mips-finished");
448 * These are some hooks which must be filled but are probably not needed.
450 static void mips_before_sched(void *self) {
451 /* Some stuff you need to do after scheduling but before register allocation */
454 static void mips_before_ra(void *self) {
455 /* Some stuff you need to do immediately after register allocation */
458 static void mips_after_ra(void* self) {
459 mips_code_gen_t *cg = self;
460 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
464 * Emits the code, closes the output file and frees
465 * the code generator interface.
467 static void mips_emit_and_done(void *self) {
468 mips_code_gen_t *cg = self;
469 ir_graph *irg = cg->irg;
470 FILE *out = cg->isa->out;
472 mips_register_emitters();
474 if (cg->emit_decls) {
479 mips_gen_routine(out, irg, cg);
483 /* de-allocate code generator */
484 del_set(cg->reg_set);
486 DEL_ARR_F(cg->bl_list);
487 free_survive_dce(cg->bl_list_sdce);
492 static void *mips_cg_init(be_irg_t *birg);
494 static const arch_code_generator_if_t mips_code_gen_if = {
496 NULL, /* before abi introduce */
499 mips_before_sched, /* before scheduling hook */
500 mips_before_ra, /* before register allocation hook */
507 * Initializes the code generator.
509 static void *mips_cg_init(be_irg_t *birg) {
510 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
511 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
512 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
514 cg->impl = &mips_code_gen_if;
515 cg->irg = be_get_birg_irg(birg);
516 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
517 cg->arch_env = arch_env;
521 FIRM_DBG_REGISTER(cg->mod, "firm.be.mips.cg");
525 if (isa->num_codegens > 1)
530 cur_reg_set = cg->reg_set;
532 mips_irn_ops.cg = cg;
534 return (arch_code_generator_t *)cg;
538 /*****************************************************************
539 * ____ _ _ _____ _____
540 * | _ \ | | | | |_ _|/ ____| /\
541 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
542 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
543 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
544 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
546 *****************************************************************/
548 static mips_isa_t mips_isa_template = {
550 &mips_gp_regs[REG_SP],
551 &mips_gp_regs[REG_FP],
552 -1, // stack direction
553 0, // num codegens?!? TODO what is this?
558 * Initializes the backend ISA and opens the output file.
560 static void *mips_init(FILE *file_handle) {
561 static int inited = 0;
567 isa = xcalloc(1, sizeof(*isa));
568 memcpy(isa, &mips_isa_template, sizeof(*isa));
570 isa->out = file_handle;
572 mips_register_init(isa);
573 mips_create_opcodes();
574 mips_init_opcode_transforms();
582 * Closes the output file and frees the ISA structure.
584 static void mips_done(void *self) {
588 static int mips_get_n_reg_class(const void *self) {
592 static const arch_register_class_t *mips_get_reg_class(const void *self, int i) {
593 assert(i >= 0 && i < N_CLASSES && "Invalid mips register class requested.");
594 return &mips_reg_classes[i];
600 * Get the register class which shall be used to store a value of a given mode.
601 * @param self The this pointer.
602 * @param mode The mode in question.
603 * @return A register class which can hold values of the given mode.
605 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
606 ASSERT_NO_FLOAT(mode);
607 return &mips_reg_classes[CLASS_mips_gp];
611 be_abi_call_flags_bits_t flags;
612 const mips_isa_t *isa;
613 const arch_env_t *arch_env;
615 // do special handling to support debuggers
619 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
621 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
622 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
623 env->flags = fl.bits;
625 env->arch_env = arch_env;
626 env->isa = (const mips_isa_t*) arch_env->isa;
631 static void mips_abi_dont_save_regs(void *self, pset *s)
633 mips_abi_env_t *env = self;
634 if(env->flags.try_omit_fp)
635 pset_insert_ptr(s, env->isa->fp);
638 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
640 mips_abi_env_t *env = self;
641 ir_graph *irg = env->irg;
642 dbg_info *dbg = NULL; // TODO where can I get this from?
643 ir_node *block = get_irg_start_block(env->irg);
645 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
646 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
647 int initialstackframesize;
651 * The calling conventions wants a stack frame of at least 24bytes size with
652 * a0-a3 saved in offset 0-12
653 * fp saved in offset 16
654 * ra saved in offset 20
657 ir_node *sync, *reg, *store;
658 initialstackframesize = 24;
660 // - setup first part of stackframe
661 sp = new_rd_mips_addiu(dbg, irg, block, sp);
662 attr = get_mips_attr(sp);
663 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
664 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
665 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
667 /* TODO: where to get an edge with a0-a3
669 for(i = 0; i < 4; ++i) {
670 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
671 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
672 attr = get_mips_attr(store);
673 attr->load_store_mode = mode_Iu;
674 attr->tv = new_tarval_from_long(i * 4, mode_Is);
676 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
680 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
681 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
682 attr = get_mips_attr(store);
683 attr->modes.load_store_mode = mode_Iu;
684 attr->tv = new_tarval_from_long(16, mode_Is);
686 mm[4] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
688 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
689 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
690 attr = get_mips_attr(store);
691 attr->modes.load_store_mode = mode_Iu;
692 attr->tv = new_tarval_from_long(20, mode_Is);
694 mm[5] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
696 // TODO ideally we would route these mem edges directly towards the epilogue
697 sync = new_r_Sync(irg, block, 2, mm+4);
700 ir_node *reg, *store;
701 initialstackframesize = 4;
703 // save old framepointer
704 sp = new_rd_mips_addiu(dbg, irg, block, sp);
705 attr = get_mips_attr(sp);
706 attr->tv = new_tarval_from_long(-initialstackframesize, mode_Is);
707 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
708 //arch_set_irn_register(mips_get_arg_env(), sp, &mips_gp_regs[REG_SP]);
710 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
711 store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
712 attr = get_mips_attr(store);
713 attr->modes.load_store_mode = mode_Iu;
714 attr->tv = new_tarval_from_long(0, mode_Is);
716 *mem = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
719 // setup framepointer
720 fp = new_rd_mips_addiu(dbg, irg, block, sp);
721 attr = get_mips_attr(fp);
722 attr->tv = new_tarval_from_long(initialstackframesize, mode_Is);
723 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
724 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
726 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
727 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
729 return &mips_gp_regs[REG_SP];
732 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
734 mips_abi_env_t *env = self;
735 ir_graph *irg = env->irg;
736 dbg_info *dbg = NULL; // TODO where can I get this from?
738 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
739 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
741 int initial_frame_size = env->debug ? 24 : 4;
742 int fp_save_offset = env->debug ? 16 : 0;
745 sp = new_rd_mips_move(dbg, irg, block, fp);
746 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
747 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_SP]);
750 load = new_rd_mips_load_r(dbg, irg, block, *mem, sp, mode_T);
751 attr = get_mips_attr(load);
752 attr->modes.load_store_mode = mode_Iu;
753 // sp is at the fp address already, so we have to do fp_save_offset - initial_frame_size
754 attr->tv = new_tarval_from_long(fp_save_offset - initial_frame_size, mode_Is);
756 fp = new_r_Proj(irg, block, load, mode_Iu, pn_Load_res);
757 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
758 //arch_set_irn_register(mips_get_arg_env(), fp, &mips_gp_regs[REG_FP]);
760 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
761 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
765 * Produces the type which sits between the stack args and the locals on the stack.
766 * it will contain the return address and space to store the old frame pointer.
767 * @return The Firm type modelling the ABI between type.
769 static ir_type *mips_abi_get_between_type(void *self) {
770 mips_abi_env_t *env = self;
772 static ir_type *debug_between_type = NULL;
773 static ir_type *opt_between_type = NULL;
774 static ir_entity *old_fp_ent = NULL;
776 if(env->debug && debug_between_type == NULL) {
777 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
778 ir_entity *ret_addr_ent;
779 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
780 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
781 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
783 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
784 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
785 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
786 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
787 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
788 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
789 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
791 set_entity_offset(a0_ent, 0);
792 set_entity_offset(a1_ent, 4);
793 set_entity_offset(a2_ent, 8);
794 set_entity_offset(a3_ent, 12);
795 set_entity_offset(old_fp_ent, 16);
796 set_entity_offset(ret_addr_ent, 20);
798 set_type_size_bytes(debug_between_type, 24);
799 } else if(!env->debug && opt_between_type == NULL) {
800 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
801 ir_entity *old_fp_ent;
803 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
804 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
805 set_entity_offset(old_fp_ent, 0);
806 set_type_size_bytes(opt_between_type, 4);
809 return env->debug ? debug_between_type : opt_between_type;
812 static const be_abi_callbacks_t mips_abi_callbacks = {
815 mips_abi_get_between_type,
816 mips_abi_dont_save_regs,
822 * Get the ABI restrictions for procedure calls.
823 * @param self The this pointer.
824 * @param method_type The type of the method (procedure) in question.
825 * @param abi The abi object to be modified
827 static void mips_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
830 int n = get_method_n_params(method_type);
834 const arch_register_t *reg;
835 be_abi_call_flags_t call_flags;
837 memset(&call_flags, 0, sizeof(call_flags));
838 call_flags.bits.left_to_right = 0;
839 call_flags.bits.store_args_sequential = 0;
840 call_flags.bits.try_omit_fp = 1;
841 call_flags.bits.fp_free = 0;
842 call_flags.bits.call_has_imm = 1;
844 /* set stack parameter passing style */
845 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
847 /* collect the mode for each type */
848 modes = alloca(n * sizeof(modes[0]));
849 for (i = 0; i < n; i++) {
850 tp = get_method_param_type(method_type, i);
851 modes[i] = get_type_mode(tp);
854 // assigns parameters to registers or stack
855 for (i = 0; i < n; i++) {
856 // first 4 params in $a0-$a3, the others on the stack
858 reg = &mips_gp_regs[REG_A0 + i];
859 be_abi_call_param_reg(abi, i, reg);
861 /* default: all parameters on stack */
862 be_abi_call_param_stack(abi, i, 4, 0, 0);
866 /* set return register */
867 /* default: return value is in R0 (and maybe R1) */
868 result_count = get_method_n_ress(method_type);
869 assert(result_count <= 2 && "More than 2 result values not supported");
870 for(i = 0; i < result_count; ++i) {
871 const arch_register_t* reg;
872 tp = get_method_res_type(method_type, i);
873 mode = get_type_mode(tp);
874 ASSERT_NO_FLOAT(mode);
876 reg = &mips_gp_regs[REG_V0 + i];
877 be_abi_call_res_reg(abi, i, reg);
881 static const void *mips_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
882 return &mips_irn_ops;
885 const arch_irn_handler_t mips_irn_handler = {
889 const arch_irn_handler_t *mips_get_irn_handler(const void *self) {
890 return &mips_irn_handler;
894 * Initializes the code generator interface.
896 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self) {
897 return &mips_code_gen_if;
901 * Returns the necessary byte alignment for storing a register of given class.
903 static int mips_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
904 ir_mode *mode = arch_register_class_mode(cls);
905 return get_mode_size_bytes(mode);
908 static const be_execution_unit_t ***mips_get_allowed_execution_units(const void *self, const ir_node *irn) {
914 static const be_machine_t *mips_get_machine(const void *self) {
921 * Return irp irgs in the desired order.
923 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list) {
928 * Returns the libFirm configuration parameter for this backend.
930 static const backend_params *mips_get_libfirm_params(void) {
931 static arch_dep_params_t ad = {
933 0, /* Muls are fast enough on Mips */
934 31, /* shift would be ok */
937 32, /* Mulhs & Mulhu available for 32 bit */
939 static backend_params p = {
940 NULL, /* no additional opcodes */
941 NULL, /* will be set later */
942 1, /* need dword lowering */
943 NULL, /* but yet no creator function */
944 NULL, /* context for create_intrinsic_fkt */
951 const arch_isa_if_t mips_isa_if = {
954 mips_get_n_reg_class,
956 mips_get_reg_class_for_mode,
958 mips_get_irn_handler,
959 mips_get_code_generator_if,
960 mips_get_list_sched_selector,
961 mips_get_ilp_sched_selector,
962 mips_get_reg_class_alignment,
963 mips_get_libfirm_params,
964 mips_get_allowed_execution_units,
969 void be_init_arch_mips(void)
971 be_register_isa_if("mips", &mips_isa_if);
974 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);