2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
30 #include "pseudo_irg.h"
47 #include "../bearch_t.h"
48 #include "../benode_t.h"
49 #include "../belower.h"
50 #include "../besched_t.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /* TODO: ugly, but we need it to get access to the registers assigned to Phi nodes */
72 static set *cur_reg_set = NULL;
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
86 * Return register requirements for a mips node.
87 * If the node returns a tuple (mode_T) then the proj's
88 * will be asked for this information.
91 arch_register_req_t *mips_get_irn_reg_req(const void *self,
92 const ir_node *node, int pos)
94 long node_pos = pos == -1 ? 0 : pos;
95 ir_mode *mode = get_irn_mode(node);
98 if (is_Block(node) || mode == mode_X || mode == mode_M) {
99 return arch_no_register_req;
102 if (mode == mode_T && pos < 0) {
103 return arch_no_register_req;
107 /* in case of a proj, we need to get the correct OUT slot */
108 /* of the node corresponding to the proj number */
110 node_pos = mips_translate_proj_pos(node);
116 node = skip_Proj_const(node);
119 /* get requirements for our own nodes */
120 if (is_mips_irn(node)) {
121 const arch_register_req_t *req;
123 req = get_mips_in_req(node, pos);
125 req = get_mips_out_req(node, node_pos);
131 /* unknown should be translated by now */
132 assert(!is_Unknown(node));
134 return arch_no_register_req;
137 static void mips_set_irn_reg(const void *self, ir_node *irn,
138 const arch_register_t *reg)
145 if (get_irn_mode(irn) == mode_X) {
149 pos = mips_translate_proj_pos(irn);
150 irn = skip_Proj(irn);
153 if (is_mips_irn(irn)) {
154 const arch_register_t **slots;
156 slots = get_mips_slots(irn);
159 /* here we set the registers for the Phi nodes */
160 mips_set_firm_reg(irn, reg, cur_reg_set);
164 static const arch_register_t *mips_get_irn_reg(const void *self,
168 const arch_register_t *reg = NULL;
173 if (get_irn_mode(irn) == mode_X) {
177 pos = mips_translate_proj_pos(irn);
178 irn = skip_Proj_const(irn);
181 if (is_mips_irn(irn)) {
182 const arch_register_t **slots;
183 slots = get_mips_slots(irn);
187 reg = mips_get_firm_reg(irn, cur_reg_set);
193 static arch_irn_class_t mips_classify(const void *self, const ir_node *irn)
196 irn = skip_Proj_const(irn);
199 return arch_irn_class_branch;
200 } else if (is_mips_irn(irn)) {
201 return arch_irn_class_normal;
207 static arch_irn_flags_t mips_get_flags(const void *self, const ir_node *irn)
210 irn = skip_Proj_const(irn);
212 if (!is_mips_irn(irn))
215 return get_mips_flags(irn);
218 int mips_is_Load(const ir_node *node)
220 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
221 is_mips_lb(node) || is_mips_lbu(node);
224 int mips_is_Store(const ir_node *node)
226 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
229 static ir_entity *mips_get_frame_entity(const void *self, const ir_node *node)
231 const mips_load_store_attr_t *attr;
234 if(!is_mips_irn(node))
236 if(!mips_is_Load(node) && !mips_is_Store(node))
239 attr = get_mips_load_store_attr_const(node);
240 return attr->stack_entity;
243 static void mips_set_frame_entity(const void *self, ir_node *node,
246 mips_load_store_attr_t *attr;
249 if(!is_mips_irn(node)) {
250 panic("trying to set frame entity on non load/store node %+F\n", node);
252 if(!mips_is_Load(node) && !mips_is_Store(node)) {
253 panic("trying to set frame entity on non load/store node %+F\n", node);
256 attr = get_irn_generic_attr(node);
257 attr->stack_entity = entity;
261 * This function is called by the generic backend to correct offsets for
262 * nodes accessing the stack.
264 static void mips_set_frame_offset(const void *self, ir_node *node, int offset)
266 mips_load_store_attr_t *attr;
269 if(!is_mips_irn(node)) {
270 panic("trying to set frame offset on non load/store node %+F\n", node);
272 if(!mips_is_Load(node) && !mips_is_Store(node)) {
273 panic("trying to set frame offset on non load/store node %+F\n", node);
276 attr = get_irn_generic_attr(node);
277 attr->offset += offset;
279 if(attr->offset < -32768 || attr->offset > 32767) {
280 panic("Out of stack space! (mips supports only 16bit offsets)");
284 static int mips_get_sp_bias(const void *self, const ir_node *irn)
291 /* fill register allocator interface */
293 static const arch_irn_ops_if_t mips_irn_ops_if = {
294 mips_get_irn_reg_req,
299 mips_get_frame_entity,
300 mips_set_frame_entity,
301 mips_set_frame_offset,
303 NULL, /* get_inverse */
304 NULL, /* get_op_estimated_cost */
305 NULL, /* possible_memory_operand */
306 NULL, /* perform_memory_operand */
309 mips_irn_ops_t mips_irn_ops = {
316 /**************************************************
319 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
320 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
321 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
322 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
325 **************************************************/
335 * Ext-Block walker: create a block schedule
337 static void create_block_list(ir_extblk *blk, void *env) {
341 for (i = 0, n = get_extbb_n_blocks(blk); i < n; ++i) {
342 ir_node *block = get_extbb_block(blk, i);
344 set_irn_link(block, NULL);
346 set_irn_link(list->end, block);
355 /* return the scheduled block at position pos */
356 ir_node *mips_get_sched_block(const mips_code_gen_t *cg, int pos) {
357 if (0 <= pos && pos < ARR_LEN(cg->bl_list))
358 return cg->bl_list[pos];
362 /* return the number of scheduled blocks */
363 int mips_get_sched_n_blocks(const mips_code_gen_t *cg) {
364 return ARR_LEN(cg->bl_list);
367 /* set a block schedule number */
368 void mips_set_block_sched_nr(ir_node *block, int nr) {
369 set_irn_link(block, INT_TO_PTR(nr));
372 /* get a block schedule number */
373 int mips_get_block_sched_nr(ir_node *block) {
374 return PTR_TO_INT(get_irn_link(block));
378 * Creates a block schedule for the given graph.
380 static void mips_create_block_sched(mips_code_gen_t *cg) {
382 ir_node **bl_list, *block;
386 DEL_ARR_F(cg->bl_list);
387 free_survive_dce(cg->bl_list_sdce);
390 /* calculate the block schedule here */
391 compute_extbb(cg->irg);
396 irg_extblock_walk_graph(cg->irg, NULL, create_block_list, &list);
399 bl_list = NEW_ARR_F(ir_node *, list.cnt);
400 cg->bl_list_sdce = new_survive_dce();
401 for (i = 0, block = list.start; block; block = get_irn_link(block)) {
403 survive_dce_register_irn(cg->bl_list_sdce, &bl_list[i]);
407 cg->bl_list = bl_list;
411 typedef struct _wenv_t {
416 * Walker: link all CopyB nodes
418 static void collect_copyb_nodes(ir_node *node, void *env) {
421 if (get_irn_op(node) == op_CopyB) {
422 set_irn_link(node, wenv->list);
428 static void replace_copyb_nodes(mips_code_gen_t *cg) {
431 ir_node *copy, *next;
432 ir_node *old_bl, *new_bl, *jmp, *new_jmp, *mem;
433 const ir_edge_t *edge;
435 /* build code for all copyB */
437 irg_walk_graph(cg->irg, NULL, collect_copyb_nodes, &env);
439 for (copy = env.list; copy; copy = next) {
440 next = get_irn_link(copy);
442 old_bl = get_nodes_block(copy);
444 jmp = get_Block_cfgpred(old_bl, 0);
445 new_jmp = new_r_Jmp(cg->irg, get_nodes_block(copy));
447 new_bl = new_r_Block(cg->irg, 1, &new_jmp);
448 set_nodes_block(jmp, new_bl);
450 mem = gen_code_for_CopyB(new_bl, copy);
452 /* fix copyB's out edges */
453 foreach_out_edge(copy, edge) {
454 ir_node *succ = get_edge_src_irn(edge);
456 assert(is_Proj(succ));
457 switch (get_Proj_proj(succ)) {
458 case pn_CopyB_M_regular:
459 case pn_CopyB_M_except:
463 exchange(succ, get_irg_bad(cg->irg));
472 * Transforms the standard firm graph into
475 static void mips_prepare_graph(void *self) {
476 mips_code_gen_t *cg = self;
479 // replace all copyb nodes in the block with a loop
480 // and mips store/load nodes
481 replace_copyb_nodes(cg);
483 // Calculate block schedule
484 mips_create_block_sched(cg);
486 /* enter the block number into every blocks link field */
487 for (bl_nr = 0, n = mips_get_sched_n_blocks(cg); bl_nr < n; ++bl_nr) {
488 ir_node *bl = mips_get_sched_block(cg, bl_nr);
489 mips_set_block_sched_nr(bl, bl_nr);
492 // walk the graph and transform firm nodes into mips nodes where possible
493 mips_transform_graph(cg);
494 dump_ir_block_graph_sched(cg->irg, "-transformed");
498 * Called immediately before emit phase.
500 static void mips_finish_irg(void *self) {
501 mips_code_gen_t *cg = self;
502 ir_graph *irg = cg->irg;
504 dump_ir_block_graph_sched(irg, "-mips-finished");
509 * These are some hooks which must be filled but are probably not needed.
511 static void mips_before_sched(void *self)
516 static void mips_before_ra(void *self)
521 static void mips_after_ra(void* self)
523 mips_code_gen_t *cg = self;
524 be_coalesce_spillslots(cg->birg);
525 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
529 * Emits the code, closes the output file and frees
530 * the code generator interface.
532 static void mips_emit_and_done(void *self)
534 mips_code_gen_t *cg = self;
535 ir_graph *irg = cg->irg;
538 mips_gen_routine(cg, irg);
542 /* de-allocate code generator */
543 del_set(cg->reg_set);
545 DEL_ARR_F(cg->bl_list);
546 free_survive_dce(cg->bl_list_sdce);
551 static void *mips_cg_init(be_irg_t *birg);
553 static const arch_code_generator_if_t mips_code_gen_if = {
555 NULL, /* before abi introduce */
558 mips_before_sched, /* before scheduling hook */
559 mips_before_ra, /* before register allocation hook */
566 * Initializes the code generator.
568 static void *mips_cg_init(be_irg_t *birg)
570 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
571 mips_isa_t *isa = (mips_isa_t *) arch_env->isa;
572 mips_code_gen_t *cg = xmalloc(sizeof(*cg));
574 cg->impl = &mips_code_gen_if;
575 cg->irg = be_get_birg_irg(birg);
576 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
577 cg->arch_env = arch_env;
582 cur_reg_set = cg->reg_set;
584 mips_irn_ops.cg = cg;
588 return (arch_code_generator_t *)cg;
592 /*****************************************************************
593 * ____ _ _ _____ _____
594 * | _ \ | | | | |_ _|/ ____| /\
595 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
596 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
597 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
598 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
600 *****************************************************************/
602 static mips_isa_t mips_isa_template = {
605 &mips_gp_regs[REG_SP],
606 &mips_gp_regs[REG_FP],
607 -1, /* stack direction */
608 NULL, /* main environment */
610 5, /* reload costs */
616 * Initializes the backend ISA and opens the output file.
618 static void *mips_init(FILE *file_handle) {
619 static int inited = 0;
626 isa = xcalloc(1, sizeof(isa[0]));
627 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
629 be_emit_init(file_handle);
631 mips_register_init();
632 mips_create_opcodes();
633 // mips_init_opcode_transforms();
635 /* we mark referenced global entities, so we can only emit those which
636 * are actually referenced. (Note: you mustn't use the type visited flag
637 * elsewhere in the backend)
639 inc_master_type_visited();
645 * Closes the output file and frees the ISA structure.
647 static void mips_done(void *self)
649 mips_isa_t *isa = self;
651 be_gas_emit_decls(isa->arch_isa.main_env, 1);
657 static unsigned mips_get_n_reg_class(const void *self)
663 static const arch_register_class_t *mips_get_reg_class(const void *self,
667 assert(i < N_CLASSES);
668 return &mips_reg_classes[i];
674 * Get the register class which shall be used to store a value of a given mode.
675 * @param self The this pointer.
676 * @param mode The mode in question.
677 * @return A register class which can hold values of the given mode.
679 const arch_register_class_t *mips_get_reg_class_for_mode(const void *self,
684 ASSERT_NO_FLOAT(mode);
685 return &mips_reg_classes[CLASS_mips_gp];
689 be_abi_call_flags_bits_t flags;
690 const arch_isa_t *isa;
691 const arch_env_t *arch_env;
693 // do special handling to support debuggers
697 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
699 mips_abi_env_t *env = xmalloc(sizeof(env[0]));
700 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
701 env->flags = fl.bits;
703 env->arch_env = arch_env;
704 env->isa = arch_env->isa;
709 static void mips_abi_dont_save_regs(void *self, pset *s)
711 mips_abi_env_t *env = self;
713 if(env->flags.try_omit_fp)
714 pset_insert_ptr(s, env->isa->bp);
717 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map)
719 mips_abi_env_t *env = self;
720 ir_graph *irg = env->irg;
721 ir_node *block = get_irg_start_block(env->irg);
722 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
723 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
724 int initialstackframesize;
728 * The calling conventions wants a stack frame of at least 24bytes size with
729 * a0-a3 saved in offset 0-12
730 * fp saved in offset 16
731 * ra saved in offset 20
734 ir_node *sync, *reg, *store;
735 initialstackframesize = 24;
737 // - setup first part of stackframe
738 sp = new_rd_mips_addu(NULL, irg, block, sp,
739 mips_create_Immediate(initialstackframesize));
740 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
741 set_mips_flags(sp, arch_irn_flags_ignore);
743 /* TODO: where to get an edge with a0-a3
745 for(i = 0; i < 4; ++i) {
746 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
747 ir_node *store = new_rd_mips_store_r(dbg, irg, block, *mem, sp, reg, mode_T);
748 attr = get_mips_attr(store);
749 attr->load_store_mode = mode_Iu;
750 attr->tv = new_tarval_from_long(i * 4, mode_Is);
752 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
756 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
757 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 16);
761 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
762 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 20);
766 /* Note: ideally we would route these mem edges directly towards the
767 * epilogue, but this is currently not supported so we sync all mems
769 sync = new_r_Sync(irg, block, 2, mm+4);
772 ir_node *reg, *store;
773 initialstackframesize = 4;
775 // save old framepointer
776 sp = new_rd_mips_addu(NULL, irg, block, sp,
777 mips_create_Immediate(-initialstackframesize));
778 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
779 set_mips_flags(sp, arch_irn_flags_ignore);
781 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
782 store = new_rd_mips_sw(NULL, irg, block, sp, reg, *mem, NULL, 0);
787 // setup framepointer
788 fp = new_rd_mips_addu(NULL, irg, block, sp,
789 mips_create_Immediate(-initialstackframesize));
790 mips_set_irn_reg(NULL, fp, &mips_gp_regs[REG_FP]);
791 set_mips_flags(fp, arch_irn_flags_ignore);
793 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
794 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
796 return &mips_gp_regs[REG_SP];
799 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
801 mips_abi_env_t *env = self;
803 ir_graph *irg = env->irg;
804 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
805 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
807 int initial_frame_size = env->debug ? 24 : 4;
808 int fp_save_offset = env->debug ? 16 : 0;
811 sp = new_rd_mips_or(NULL, irg, block, fp, mips_create_zero());
812 mips_set_irn_reg(NULL, sp, &mips_gp_regs[REG_SP]);
813 set_mips_flags(sp, arch_irn_flags_ignore);
816 load = new_rd_mips_lw(NULL, irg, block, sp, *mem, NULL,
817 fp_save_offset - initial_frame_size);
818 set_mips_flags(load, arch_irn_flags_ignore);
820 fp = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_res);
821 *mem = new_r_Proj(irg, block, load, mode_Iu, pn_mips_lw_M);
822 arch_set_irn_register(env->arch_env, fp, &mips_gp_regs[REG_FP]);
824 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
825 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
829 * Produces the type which sits between the stack args and the locals on the stack.
830 * it will contain the return address and space to store the old frame pointer.
831 * @return The Firm type modelling the ABI between type.
833 static ir_type *mips_abi_get_between_type(void *self) {
834 mips_abi_env_t *env = self;
836 static ir_type *debug_between_type = NULL;
837 static ir_type *opt_between_type = NULL;
838 static ir_entity *old_fp_ent = NULL;
840 if(env->debug && debug_between_type == NULL) {
841 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
842 ir_entity *ret_addr_ent;
843 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
844 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
845 ir_type *old_param_type = new_type_primitive(new_id_from_str("param"), mode_Iu);
847 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
848 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
849 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
850 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
851 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
852 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
853 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
855 set_entity_offset(a0_ent, 0);
856 set_entity_offset(a1_ent, 4);
857 set_entity_offset(a2_ent, 8);
858 set_entity_offset(a3_ent, 12);
859 set_entity_offset(old_fp_ent, 16);
860 set_entity_offset(ret_addr_ent, 20);
862 set_type_size_bytes(debug_between_type, 24);
863 } else if(!env->debug && opt_between_type == NULL) {
864 ir_type *old_fp_type = new_type_primitive(new_id_from_str("fp"), mode_P);
865 ir_entity *old_fp_ent;
867 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
868 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
869 set_entity_offset(old_fp_ent, 0);
870 set_type_size_bytes(opt_between_type, 4);
873 return env->debug ? debug_between_type : opt_between_type;
876 static const be_abi_callbacks_t mips_abi_callbacks = {
879 mips_abi_get_between_type,
880 mips_abi_dont_save_regs,
886 * Get the ABI restrictions for procedure calls.
887 * @param self The this pointer.
888 * @param method_type The type of the method (procedure) in question.
889 * @param abi The abi object to be modified
891 static void mips_get_call_abi(const void *self, ir_type *method_type,
896 int n = get_method_n_params(method_type);
900 const arch_register_t *reg;
901 be_abi_call_flags_t call_flags;
904 memset(&call_flags, 0, sizeof(call_flags));
905 call_flags.bits.left_to_right = 0;
906 call_flags.bits.store_args_sequential = 0;
907 call_flags.bits.try_omit_fp = 1;
908 call_flags.bits.fp_free = 0;
909 call_flags.bits.call_has_imm = 1;
911 /* set stack parameter passing style */
912 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
914 /* collect the mode for each type */
915 modes = alloca(n * sizeof(modes[0]));
916 for (i = 0; i < n; i++) {
917 tp = get_method_param_type(method_type, i);
918 modes[i] = get_type_mode(tp);
921 // assigns parameters to registers or stack
922 for (i = 0; i < n; i++) {
923 // first 4 params in $a0-$a3, the others on the stack
925 reg = &mips_gp_regs[REG_A0 + i];
926 be_abi_call_param_reg(abi, i, reg);
928 /* default: all parameters on stack */
929 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
933 /* set return register */
934 /* default: return value is in R0 (and maybe R1) */
935 result_count = get_method_n_ress(method_type);
936 assert(result_count <= 2 && "More than 2 result values not supported");
937 for(i = 0; i < result_count; ++i) {
938 const arch_register_t* reg;
939 tp = get_method_res_type(method_type, i);
940 mode = get_type_mode(tp);
941 ASSERT_NO_FLOAT(mode);
943 reg = &mips_gp_regs[REG_V0 + i];
944 be_abi_call_res_reg(abi, i, reg);
948 static const void *mips_get_irn_ops(const arch_irn_handler_t *self,
953 return &mips_irn_ops;
956 const arch_irn_handler_t mips_irn_handler = {
960 const arch_irn_handler_t *mips_get_irn_handler(const void *self)
963 return &mips_irn_handler;
967 * Initializes the code generator interface.
969 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
972 return &mips_code_gen_if;
976 * Returns the necessary byte alignment for storing a register of given class.
978 static int mips_get_reg_class_alignment(const void *self,
979 const arch_register_class_t *cls)
981 ir_mode *mode = arch_register_class_mode(cls);
983 return get_mode_size_bytes(mode);
986 static const be_execution_unit_t ***mips_get_allowed_execution_units(
987 const void *self, const ir_node *irn)
996 static const be_machine_t *mips_get_machine(const void *self)
1005 * Return irp irgs in the desired order.
1007 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
1015 * Returns the libFirm configuration parameter for this backend.
1017 static const backend_params *mips_get_libfirm_params(void) {
1018 static backend_params p = {
1019 1, /* need dword lowering */
1020 0, /* don't support inline assembler yet */
1021 NULL, /* no additional opcodes */
1022 NULL, /* will be set later */
1023 NULL, /* but yet no creator function */
1024 NULL, /* context for create_intrinsic_fkt */
1025 NULL, /* no if conversion settings */
1031 const arch_isa_if_t mips_isa_if = {
1034 mips_get_n_reg_class,
1036 mips_get_reg_class_for_mode,
1038 mips_get_irn_handler,
1039 mips_get_code_generator_if,
1040 mips_get_list_sched_selector,
1041 mips_get_ilp_sched_selector,
1042 mips_get_reg_class_alignment,
1043 mips_get_libfirm_params,
1044 mips_get_allowed_execution_units,
1049 void be_init_arch_mips(void)
1051 be_register_isa_if("mips", &mips_isa_if);
1054 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);