2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main mips backend driver file.
23 * @author Matthias Braun, Mehdi
28 #include "pseudo_irg.h"
45 #include "../bearch.h"
46 #include "../benode.h"
47 #include "../belower.h"
48 #include "../besched.h"
49 #include "../beblocksched.h"
53 #include "../bemachine.h"
54 #include "../bemodule.h"
55 #include "../bespillslots.h"
56 #include "../beemitter.h"
57 #include "../begnuas.h"
59 #include "bearch_mips_t.h"
61 #include "mips_new_nodes.h"
62 #include "gen_mips_regalloc_if.h"
63 #include "mips_transform.h"
64 #include "mips_emitter.h"
65 #include "mips_map_regs.h"
66 #include "mips_util.h"
67 #include "mips_scheduler.h"
69 #define DEBUG_MODULE "firm.be.mips.isa"
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
82 static arch_irn_class_t mips_classify(const ir_node *irn)
88 int mips_is_Load(const ir_node *node)
90 return is_mips_lw(node) || is_mips_lh(node) || is_mips_lhu(node) ||
91 is_mips_lb(node) || is_mips_lbu(node);
94 int mips_is_Store(const ir_node *node)
96 return is_mips_sw(node) || is_mips_sh(node) || is_mips_sb(node);
99 static ir_entity *mips_get_frame_entity(const ir_node *node)
101 const mips_load_store_attr_t *attr;
103 if (!is_mips_irn(node))
105 if (!mips_is_Load(node) && !mips_is_Store(node))
108 attr = get_mips_load_store_attr_const(node);
109 return attr->stack_entity;
112 static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
114 mips_load_store_attr_t *attr;
116 if (!is_mips_irn(node)) {
117 panic("trying to set frame entity on non load/store node %+F", node);
119 if (!mips_is_Load(node) && !mips_is_Store(node)) {
120 panic("trying to set frame entity on non load/store node %+F", node);
123 attr = get_irn_generic_attr(node);
124 attr->stack_entity = entity;
128 * This function is called by the generic backend to correct offsets for
129 * nodes accessing the stack.
131 static void mips_set_frame_offset(ir_node *node, int offset)
133 mips_load_store_attr_t *attr;
135 if (!is_mips_irn(node)) {
136 panic("trying to set frame offset on non load/store node %+F", node);
138 if (!mips_is_Load(node) && !mips_is_Store(node)) {
139 panic("trying to set frame offset on non load/store node %+F", node);
142 attr = get_irn_generic_attr(node);
143 attr->offset += offset;
145 if (attr->offset < -32768 || attr->offset > 32767) {
146 panic("Out of stack space! (mips supports only 16bit offsets)");
150 static int mips_get_sp_bias(const ir_node *irn)
156 /* fill register allocator interface */
158 static const arch_irn_ops_t mips_irn_ops = {
161 mips_get_frame_entity,
162 mips_set_frame_entity,
163 mips_set_frame_offset,
165 NULL, /* get_inverse */
166 NULL, /* get_op_estimated_cost */
167 NULL, /* possible_memory_operand */
168 NULL, /* perform_memory_operand */
171 /**************************************************
174 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
175 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
176 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
177 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
180 **************************************************/
183 * Transforms the standard firm graph into
186 static void mips_prepare_graph(void *self)
188 mips_code_gen_t *cg = self;
190 /* do local optimizations */
191 optimize_graph_df(cg->irg);
193 /* TODO: we often have dead code reachable through out-edges here. So for
194 * now we rebuild edges (as we need correct user count for code selection)
197 edges_deactivate(cg->irg);
198 edges_activate(cg->irg);
201 // walk the graph and transform firm nodes into mips nodes where possible
202 mips_transform_graph(cg);
203 dump_ir_block_graph_sched(cg->irg, "-transformed");
205 /* do local optimizations (mainly CSE) */
206 optimize_graph_df(cg->irg);
208 /* do code placement, to optimize the position of constants */
211 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
215 * Called immediately before emit phase.
217 static void mips_finish_irg(void *self)
219 mips_code_gen_t *cg = self;
220 ir_graph *irg = cg->irg;
222 /* create block schedule, this also removes empty blocks which might
223 * produce critical edges */
224 cg->block_schedule = be_create_block_schedule(irg, cg->birg->exec_freq);
226 dump_ir_block_graph_sched(irg, "-mips-finished");
230 static void mips_before_ra(void *self)
235 static void mips_after_ra(void* self)
237 mips_code_gen_t *cg = self;
238 be_coalesce_spillslots(cg->birg);
239 irg_walk_blkwise_graph(cg->irg, NULL, mips_after_ra_walker, self);
243 * Emits the code, closes the output file and frees
244 * the code generator interface.
246 static void mips_emit_and_done(void *self)
248 mips_code_gen_t *cg = self;
249 ir_graph *irg = cg->irg;
252 mips_gen_routine(cg, irg);
254 /* de-allocate code generator */
255 del_set(cg->reg_set);
259 static void *mips_cg_init(be_irg_t *birg);
261 static const arch_code_generator_if_t mips_code_gen_if = {
263 NULL, /* get_pic_base */
264 NULL, /* before abi introduce */
267 mips_before_ra, /* before register allocation hook */
274 * Initializes the code generator.
276 static void *mips_cg_init(be_irg_t *birg)
278 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
279 mips_isa_t *isa = (mips_isa_t *) arch_env;
280 mips_code_gen_t *cg = XMALLOCZ(mips_code_gen_t);
282 cg->impl = &mips_code_gen_if;
283 cg->irg = be_get_birg_irg(birg);
284 cg->reg_set = new_set(mips_cmp_irn_reg_assoc, 1024);
290 return (arch_code_generator_t *)cg;
294 /*****************************************************************
295 * ____ _ _ _____ _____
296 * | _ \ | | | | |_ _|/ ____| /\
297 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
298 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
299 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
300 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
302 *****************************************************************/
304 static mips_isa_t mips_isa_template = {
307 &mips_gp_regs[REG_SP],
308 &mips_gp_regs[REG_FP],
309 &mips_reg_classes[CLASS_mips_gp],
310 -1, /* stack direction */
311 2, /* power of two stack alignment for calls, 2^2 == 4 */
312 NULL, /* main environment */
314 5, /* reload costs */
320 * Initializes the backend ISA and opens the output file.
322 static arch_env_t *mips_init(FILE *file_handle)
324 static int inited = 0;
331 isa = XMALLOC(mips_isa_t);
332 memcpy(isa, &mips_isa_template, sizeof(isa[0]));
334 be_emit_init(file_handle);
336 mips_register_init();
337 mips_create_opcodes(&mips_irn_ops);
338 // mips_init_opcode_transforms();
340 return &isa->arch_env;
344 * Closes the output file and frees the ISA structure.
346 static void mips_done(void *self)
348 mips_isa_t *isa = self;
350 be_gas_emit_decls(isa->arch_env.main_env);
356 static unsigned mips_get_n_reg_class(void)
361 static const arch_register_class_t *mips_get_reg_class(unsigned i)
363 assert(i < N_CLASSES);
364 return &mips_reg_classes[i];
370 * Get the register class which shall be used to store a value of a given mode.
371 * @param self The this pointer.
372 * @param mode The mode in question.
373 * @return A register class which can hold values of the given mode.
375 const arch_register_class_t *mips_get_reg_class_for_mode(const ir_mode *mode)
378 ASSERT_NO_FLOAT(mode);
379 return &mips_reg_classes[CLASS_mips_gp];
383 be_abi_call_flags_bits_t flags;
384 const arch_env_t *arch_env;
386 // do special handling to support debuggers
390 static void *mips_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
392 mips_abi_env_t *env = XMALLOC(mips_abi_env_t);
393 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
394 env->flags = fl.bits;
396 env->arch_env = arch_env;
401 static const arch_register_t *mips_abi_prologue(void *self, ir_node** mem, pmap *reg_map, int *stack_bias)
403 mips_abi_env_t *env = self;
404 ir_graph *irg = env->irg;
405 ir_node *block = get_irg_start_block(irg);
406 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
407 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
408 int initialstackframesize;
414 * The calling conventions wants a stack frame of at least 24bytes size with
415 * a0-a3 saved in offset 0-12
416 * fp saved in offset 16
417 * ra saved in offset 20
420 ir_node *sync, *reg, *store;
421 initialstackframesize = 24;
423 // - setup first part of stackframe
424 sp = new_bd_mips_addu(NULL, block, sp,
425 mips_create_Immediate(initialstackframesize));
426 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
427 panic("FIXME Use IncSP or set register requirement with ignore");
429 /* TODO: where to get an edge with a0-a3
431 for (i = 0; i < 4; ++i) {
432 ir_node *reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_A0 + i]);
433 ir_node *store = new_bd_mips_store_r(dbg, block, *mem, sp, reg, mode_T);
434 attr = get_mips_attr(store);
435 attr->load_store_mode = mode_Iu;
436 attr->tv = new_tarval_from_long(i * 4, mode_Is);
438 mm[i] = new_r_Proj(irg, block, store, mode_M, pn_Store_M);
442 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
443 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 16);
447 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_RA]);
448 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 20);
452 /* Note: ideally we would route these mem edges directly towards the
453 * epilogue, but this is currently not supported so we sync all mems
455 sync = new_r_Sync(block, 2, mm+4);
458 ir_node *reg, *store;
459 initialstackframesize = 4;
461 // save old framepointer
462 sp = new_bd_mips_addu(NULL, block, sp,
463 mips_create_Immediate(-initialstackframesize));
464 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
465 panic("FIXME Use IncSP or set register requirement with ignore");
467 reg = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
468 store = new_bd_mips_sw(NULL, block, sp, reg, *mem, NULL, 0);
473 // setup framepointer
474 fp = new_bd_mips_addu(NULL, block, sp,
475 mips_create_Immediate(-initialstackframesize));
476 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
477 panic("FIXME Use IncSP or set register requirement with ignore");
479 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
480 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
482 return &mips_gp_regs[REG_SP];
485 static void mips_abi_epilogue(void *self, ir_node *block, ir_node **mem, pmap *reg_map)
487 mips_abi_env_t *env = self;
489 ir_node *sp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_SP]);
490 ir_node *fp = be_abi_reg_map_get(reg_map, &mips_gp_regs[REG_FP]);
492 int initial_frame_size = env->debug ? 24 : 4;
493 int fp_save_offset = env->debug ? 16 : 0;
496 sp = new_bd_mips_or(NULL, block, fp, mips_create_zero());
497 arch_set_irn_register(sp, &mips_gp_regs[REG_SP]);
498 panic("FIXME Use be_Copy or set register requirement with ignore");
501 load = new_bd_mips_lw(NULL, block, sp, *mem, NULL,
502 fp_save_offset - initial_frame_size);
503 panic("FIXME register requirement with ignore");
505 fp = new_r_Proj(block, load, mode_Iu, pn_mips_lw_res);
506 *mem = new_r_Proj(block, load, mode_Iu, pn_mips_lw_M);
507 arch_set_irn_register(fp, &mips_gp_regs[REG_FP]);
509 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_FP], fp);
510 be_abi_reg_map_set(reg_map, &mips_gp_regs[REG_SP], sp);
514 * Produces the type which sits between the stack args and the locals on the stack.
515 * it will contain the return address and space to store the old frame pointer.
516 * @return The Firm type modelling the ABI between type.
518 static ir_type *mips_abi_get_between_type(void *self)
520 mips_abi_env_t *env = self;
522 static ir_type *debug_between_type = NULL;
523 static ir_type *opt_between_type = NULL;
524 static ir_entity *old_fp_ent = NULL;
526 if (env->debug && debug_between_type == NULL) {
527 ir_entity *a0_ent, *a1_ent, *a2_ent, *a3_ent;
528 ir_entity *ret_addr_ent;
529 ir_type *ret_addr_type = new_type_primitive(mode_P);
530 ir_type *old_fp_type = new_type_primitive(mode_P);
531 ir_type *old_param_type = new_type_primitive(mode_Iu);
533 debug_between_type = new_type_class(new_id_from_str("mips_between_type"));
534 a0_ent = new_entity(debug_between_type, new_id_from_str("a0_ent"), old_param_type);
535 a1_ent = new_entity(debug_between_type, new_id_from_str("a1_ent"), old_param_type);
536 a2_ent = new_entity(debug_between_type, new_id_from_str("a2_ent"), old_param_type);
537 a3_ent = new_entity(debug_between_type, new_id_from_str("a3_ent"), old_param_type);
538 old_fp_ent = new_entity(debug_between_type, new_id_from_str("old_fp"), old_fp_type);
539 ret_addr_ent = new_entity(debug_between_type, new_id_from_str("ret_addr"), ret_addr_type);
541 set_entity_offset(a0_ent, 0);
542 set_entity_offset(a1_ent, 4);
543 set_entity_offset(a2_ent, 8);
544 set_entity_offset(a3_ent, 12);
545 set_entity_offset(old_fp_ent, 16);
546 set_entity_offset(ret_addr_ent, 20);
548 set_type_size_bytes(debug_between_type, 24);
549 } else if (!env->debug && opt_between_type == NULL) {
550 ir_type *old_fp_type = new_type_primitive(mode_P);
551 ir_entity *old_fp_ent;
553 opt_between_type = new_type_class(new_id_from_str("mips_between_type"));
554 old_fp_ent = new_entity(opt_between_type, new_id_from_str("old_fp"), old_fp_type);
555 set_entity_offset(old_fp_ent, 0);
556 set_type_size_bytes(opt_between_type, 4);
559 return env->debug ? debug_between_type : opt_between_type;
562 static const be_abi_callbacks_t mips_abi_callbacks = {
565 mips_abi_get_between_type,
571 * Get the ABI restrictions for procedure calls.
572 * @param self The this pointer.
573 * @param method_type The type of the method (procedure) in question.
574 * @param abi The abi object to be modified
576 static void mips_get_call_abi(const void *self, ir_type *method_type,
581 int n = get_method_n_params(method_type);
585 const arch_register_t *reg;
586 be_abi_call_flags_t call_flags;
589 memset(&call_flags, 0, sizeof(call_flags));
590 call_flags.bits.left_to_right = 0;
591 call_flags.bits.store_args_sequential = 0;
592 call_flags.bits.try_omit_fp = 1;
593 call_flags.bits.fp_free = 0;
594 call_flags.bits.call_has_imm = 1;
596 /* set stack parameter passing style */
597 be_abi_call_set_flags(abi, call_flags, &mips_abi_callbacks);
599 /* collect the mode for each type */
600 modes = ALLOCAN(ir_mode*, n);
601 for (i = 0; i < n; i++) {
602 tp = get_method_param_type(method_type, i);
603 modes[i] = get_type_mode(tp);
606 // assigns parameters to registers or stack
607 for (i = 0; i < n; i++) {
608 // first 4 params in $a0-$a3, the others on the stack
610 reg = &mips_gp_regs[REG_A0 + i];
611 be_abi_call_param_reg(abi, i, reg);
613 /* default: all parameters on stack */
614 be_abi_call_param_stack(abi, i, modes[i], 4, 0, 0);
618 /* set return register */
619 /* default: return value is in R0 (and maybe R1) */
620 result_count = get_method_n_ress(method_type);
621 assert(result_count <= 2 && "More than 2 result values not supported");
622 for (i = 0; i < result_count; ++i) {
623 const arch_register_t* reg;
624 tp = get_method_res_type(method_type, i);
625 mode = get_type_mode(tp);
626 ASSERT_NO_FLOAT(mode);
628 reg = &mips_gp_regs[REG_V0 + i];
629 be_abi_call_res_reg(abi, i, reg);
634 * Initializes the code generator interface.
636 static const arch_code_generator_if_t *mips_get_code_generator_if(void *self)
639 return &mips_code_gen_if;
643 * Returns the necessary byte alignment for storing a register of given class.
645 static int mips_get_reg_class_alignment(const arch_register_class_t *cls)
647 ir_mode *mode = arch_register_class_mode(cls);
648 return get_mode_size_bytes(mode);
651 static const be_execution_unit_t ***mips_get_allowed_execution_units(
656 panic("Unimplemented mips_get_allowed_execution_units()");
659 static const be_machine_t *mips_get_machine(const void *self)
663 panic("Unimplemented mips_get_machine()");
667 * Return irp irgs in the desired order.
669 static ir_graph **mips_get_irg_list(const void *self, ir_graph ***irg_list)
677 * Returns the libFirm configuration parameter for this backend.
679 static const backend_params *mips_get_libfirm_params(void)
681 static backend_params p = {
682 1, /* need dword lowering */
683 0, /* don't support inline assembler yet */
684 NULL, /* will be set later */
685 NULL, /* but yet no creator function */
686 NULL, /* context for create_intrinsic_fkt */
687 NULL, /* no if conversion settings */
688 NULL, /* float arithmetic mode (TODO) */
689 0, /* no trampoline support: size 0 */
690 0, /* no trampoline support: align 0 */
691 NULL, /* no trampoline support: no trampoline builder */
692 4 /* alignment of stack parameter */
698 static asm_constraint_flags_t mips_parse_asm_constraint(const char **c)
701 return ASM_CONSTRAINT_FLAG_INVALID;
704 static int mips_is_valid_clobber(const char *clobber)
710 const arch_isa_if_t mips_isa_if = {
713 NULL, /* handle intrinsics */
714 mips_get_n_reg_class,
716 mips_get_reg_class_for_mode,
718 mips_get_code_generator_if,
719 mips_get_list_sched_selector,
720 mips_get_ilp_sched_selector,
721 mips_get_reg_class_alignment,
722 mips_get_libfirm_params,
723 mips_get_allowed_execution_units,
726 NULL, /* mark remat */
727 mips_parse_asm_constraint,
728 mips_is_valid_clobber
731 void be_init_arch_mips(void)
733 be_register_isa_if("mips", &mips_isa_if);
736 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_mips);